1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
3 */
4
5 #include <linux/clk-provider.h>
6 #include <linux/kernel.h>
7 #include <linux/init.h>
8 #include <linux/err.h>
9 #include <linux/ctype.h>
10 #include <linux/io.h>
11 #include <linux/of.h>
12 #include <linux/of_device.h>
13 #include <linux/platform_device.h>
14 #include <linux/module.h>
15 #include <linux/regmap.h>
16
17 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
18
19 #include "common.h"
20 #include "clk-regmap.h"
21 #include "clk-alpha-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
24 #include "reset.h"
25 #include "gdsc.h"
26
27 enum {
28 P_XO,
29 P_GPLL0,
30 P_GPLL4,
31 };
32
33 static struct clk_alpha_pll gpll0_early = {
34 .offset = 0,
35 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
36 .clkr = {
37 .enable_reg = 0x1480,
38 .enable_mask = BIT(0),
39 .hw.init = &(struct clk_init_data){
40 .name = "gpll0_early",
41 .parent_data = &(const struct clk_parent_data){
42 .fw_name = "xo",
43 },
44 .num_parents = 1,
45 .ops = &clk_alpha_pll_ops,
46 },
47 },
48 };
49
50 static struct clk_alpha_pll_postdiv gpll0 = {
51 .offset = 0,
52 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
53 .clkr.hw.init = &(struct clk_init_data){
54 .name = "gpll0",
55 .parent_hws = (const struct clk_hw*[]){
56 &gpll0_early.clkr.hw
57 },
58 .num_parents = 1,
59 .ops = &clk_alpha_pll_postdiv_ops,
60 },
61 };
62
63 static struct clk_alpha_pll gpll4_early = {
64 .offset = 0x1dc0,
65 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
66 .clkr = {
67 .enable_reg = 0x1480,
68 .enable_mask = BIT(4),
69 .hw.init = &(struct clk_init_data){
70 .name = "gpll4_early",
71 .parent_data = &(const struct clk_parent_data){
72 .fw_name = "xo",
73 },
74 .num_parents = 1,
75 .ops = &clk_alpha_pll_ops,
76 },
77 },
78 };
79
80 static struct clk_alpha_pll_postdiv gpll4 = {
81 .offset = 0x1dc0,
82 .width = 4,
83 .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],
84 .clkr.hw.init = &(struct clk_init_data){
85 .name = "gpll4",
86 .parent_hws = (const struct clk_hw*[]){
87 &gpll4_early.clkr.hw
88 },
89 .num_parents = 1,
90 .ops = &clk_alpha_pll_postdiv_ops,
91 },
92 };
93
94 static const struct parent_map gcc_xo_gpll0_map[] = {
95 { P_XO, 0 },
96 { P_GPLL0, 1 },
97 };
98
99 static const struct clk_parent_data gcc_xo_gpll0[] = {
100 { .fw_name = "xo" },
101 { .hw = &gpll0.clkr.hw },
102 };
103
104 static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
105 { P_XO, 0 },
106 { P_GPLL0, 1 },
107 { P_GPLL4, 5 },
108 };
109
110 static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {
111 { .fw_name = "xo" },
112 { .hw = &gpll0.clkr.hw },
113 { .hw = &gpll4.clkr.hw },
114 };
115
116 static struct freq_tbl ftbl_ufs_axi_clk_src[] = {
117 F(50000000, P_GPLL0, 12, 0, 0),
118 F(100000000, P_GPLL0, 6, 0, 0),
119 F(150000000, P_GPLL0, 4, 0, 0),
120 F(171430000, P_GPLL0, 3.5, 0, 0),
121 F(200000000, P_GPLL0, 3, 0, 0),
122 F(240000000, P_GPLL0, 2.5, 0, 0),
123 { }
124 };
125
126 static struct clk_rcg2 ufs_axi_clk_src = {
127 .cmd_rcgr = 0x1d68,
128 .mnd_width = 8,
129 .hid_width = 5,
130 .parent_map = gcc_xo_gpll0_map,
131 .freq_tbl = ftbl_ufs_axi_clk_src,
132 .clkr.hw.init = &(struct clk_init_data){
133 .name = "ufs_axi_clk_src",
134 .parent_data = gcc_xo_gpll0,
135 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
136 .ops = &clk_rcg2_ops,
137 },
138 };
139
140 static struct freq_tbl ftbl_usb30_master_clk_src[] = {
141 F(19200000, P_XO, 1, 0, 0),
142 F(125000000, P_GPLL0, 1, 5, 24),
143 { }
144 };
145
146 static struct clk_rcg2 usb30_master_clk_src = {
147 .cmd_rcgr = 0x03d4,
148 .mnd_width = 8,
149 .hid_width = 5,
150 .parent_map = gcc_xo_gpll0_map,
151 .freq_tbl = ftbl_usb30_master_clk_src,
152 .clkr.hw.init = &(struct clk_init_data){
153 .name = "usb30_master_clk_src",
154 .parent_data = gcc_xo_gpll0,
155 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
156 .ops = &clk_rcg2_ops,
157 },
158 };
159
160 static struct freq_tbl ftbl_blsp_i2c_apps_clk_src[] = {
161 F(19200000, P_XO, 1, 0, 0),
162 F(50000000, P_GPLL0, 12, 0, 0),
163 { }
164 };
165
166 static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {
167 .cmd_rcgr = 0x0660,
168 .hid_width = 5,
169 .parent_map = gcc_xo_gpll0_map,
170 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
171 .clkr.hw.init = &(struct clk_init_data){
172 .name = "blsp1_qup1_i2c_apps_clk_src",
173 .parent_data = gcc_xo_gpll0,
174 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
175 .ops = &clk_rcg2_ops,
176 },
177 };
178
179 static struct freq_tbl ftbl_blsp1_qup1_spi_apps_clk_src[] = {
180 F(960000, P_XO, 10, 1, 2),
181 F(4800000, P_XO, 4, 0, 0),
182 F(9600000, P_XO, 2, 0, 0),
183 F(15000000, P_GPLL0, 10, 1, 4),
184 F(19200000, P_XO, 1, 0, 0),
185 F(24000000, P_GPLL0, 12.5, 1, 2),
186 F(25000000, P_GPLL0, 12, 1, 2),
187 F(48000000, P_GPLL0, 12.5, 0, 0),
188 F(50000000, P_GPLL0, 12, 0, 0),
189 { }
190 };
191
192 static struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src_8992[] = {
193 F(960000, P_XO, 10, 1, 2),
194 F(4800000, P_XO, 4, 0, 0),
195 F(9600000, P_XO, 2, 0, 0),
196 F(15000000, P_GPLL0, 10, 1, 4),
197 F(19200000, P_XO, 1, 0, 0),
198 F(25000000, P_GPLL0, 12, 1, 2),
199 F(50000000, P_GPLL0, 12, 0, 0),
200 { }
201 };
202
203 static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {
204 .cmd_rcgr = 0x064c,
205 .mnd_width = 8,
206 .hid_width = 5,
207 .parent_map = gcc_xo_gpll0_map,
208 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
209 .clkr.hw.init = &(struct clk_init_data){
210 .name = "blsp1_qup1_spi_apps_clk_src",
211 .parent_data = gcc_xo_gpll0,
212 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
213 .ops = &clk_rcg2_ops,
214 },
215 };
216
217 static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {
218 .cmd_rcgr = 0x06e0,
219 .hid_width = 5,
220 .parent_map = gcc_xo_gpll0_map,
221 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
222 .clkr.hw.init = &(struct clk_init_data){
223 .name = "blsp1_qup2_i2c_apps_clk_src",
224 .parent_data = gcc_xo_gpll0,
225 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
226 .ops = &clk_rcg2_ops,
227 },
228 };
229
230 static struct freq_tbl ftbl_blsp1_qup2_spi_apps_clk_src[] = {
231 F(960000, P_XO, 10, 1, 2),
232 F(4800000, P_XO, 4, 0, 0),
233 F(9600000, P_XO, 2, 0, 0),
234 F(15000000, P_GPLL0, 10, 1, 4),
235 F(19200000, P_XO, 1, 0, 0),
236 F(24000000, P_GPLL0, 12.5, 1, 2),
237 F(25000000, P_GPLL0, 12, 1, 2),
238 F(42860000, P_GPLL0, 14, 0, 0),
239 F(46150000, P_GPLL0, 13, 0, 0),
240 { }
241 };
242
243 static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {
244 .cmd_rcgr = 0x06cc,
245 .mnd_width = 8,
246 .hid_width = 5,
247 .parent_map = gcc_xo_gpll0_map,
248 .freq_tbl = ftbl_blsp1_qup2_spi_apps_clk_src,
249 .clkr.hw.init = &(struct clk_init_data){
250 .name = "blsp1_qup2_spi_apps_clk_src",
251 .parent_data = gcc_xo_gpll0,
252 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
253 .ops = &clk_rcg2_ops,
254 },
255 };
256
257 static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {
258 .cmd_rcgr = 0x0760,
259 .hid_width = 5,
260 .parent_map = gcc_xo_gpll0_map,
261 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
262 .clkr.hw.init = &(struct clk_init_data){
263 .name = "blsp1_qup3_i2c_apps_clk_src",
264 .parent_data = gcc_xo_gpll0,
265 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
266 .ops = &clk_rcg2_ops,
267 },
268 };
269
270 static struct freq_tbl ftbl_blsp1_qup3_4_spi_apps_clk_src[] = {
271 F(960000, P_XO, 10, 1, 2),
272 F(4800000, P_XO, 4, 0, 0),
273 F(9600000, P_XO, 2, 0, 0),
274 F(15000000, P_GPLL0, 10, 1, 4),
275 F(19200000, P_XO, 1, 0, 0),
276 F(24000000, P_GPLL0, 12.5, 1, 2),
277 F(25000000, P_GPLL0, 12, 1, 2),
278 F(42860000, P_GPLL0, 14, 0, 0),
279 F(44440000, P_GPLL0, 13.5, 0, 0),
280 { }
281 };
282
283 static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {
284 .cmd_rcgr = 0x074c,
285 .mnd_width = 8,
286 .hid_width = 5,
287 .parent_map = gcc_xo_gpll0_map,
288 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
289 .clkr.hw.init = &(struct clk_init_data){
290 .name = "blsp1_qup3_spi_apps_clk_src",
291 .parent_data = gcc_xo_gpll0,
292 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
293 .ops = &clk_rcg2_ops,
294 },
295 };
296
297 static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {
298 .cmd_rcgr = 0x07e0,
299 .hid_width = 5,
300 .parent_map = gcc_xo_gpll0_map,
301 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
302 .clkr.hw.init = &(struct clk_init_data){
303 .name = "blsp1_qup4_i2c_apps_clk_src",
304 .parent_data = gcc_xo_gpll0,
305 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
306 .ops = &clk_rcg2_ops,
307 },
308 };
309
310 static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {
311 .cmd_rcgr = 0x07cc,
312 .mnd_width = 8,
313 .hid_width = 5,
314 .parent_map = gcc_xo_gpll0_map,
315 .freq_tbl = ftbl_blsp1_qup3_4_spi_apps_clk_src,
316 .clkr.hw.init = &(struct clk_init_data){
317 .name = "blsp1_qup4_spi_apps_clk_src",
318 .parent_data = gcc_xo_gpll0,
319 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
320 .ops = &clk_rcg2_ops,
321 },
322 };
323
324 static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {
325 .cmd_rcgr = 0x0860,
326 .hid_width = 5,
327 .parent_map = gcc_xo_gpll0_map,
328 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
329 .clkr.hw.init = &(struct clk_init_data){
330 .name = "blsp1_qup5_i2c_apps_clk_src",
331 .parent_data = gcc_xo_gpll0,
332 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
333 .ops = &clk_rcg2_ops,
334 },
335 };
336
337 static struct freq_tbl ftbl_blsp1_qup5_spi_apps_clk_src[] = {
338 F(960000, P_XO, 10, 1, 2),
339 F(4800000, P_XO, 4, 0, 0),
340 F(9600000, P_XO, 2, 0, 0),
341 F(15000000, P_GPLL0, 10, 1, 4),
342 F(19200000, P_XO, 1, 0, 0),
343 F(24000000, P_GPLL0, 12.5, 1, 2),
344 F(25000000, P_GPLL0, 12, 1, 2),
345 F(40000000, P_GPLL0, 15, 0, 0),
346 F(42860000, P_GPLL0, 14, 0, 0),
347 { }
348 };
349
350 static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {
351 .cmd_rcgr = 0x084c,
352 .mnd_width = 8,
353 .hid_width = 5,
354 .parent_map = gcc_xo_gpll0_map,
355 .freq_tbl = ftbl_blsp1_qup5_spi_apps_clk_src,
356 .clkr.hw.init = &(struct clk_init_data){
357 .name = "blsp1_qup5_spi_apps_clk_src",
358 .parent_data = gcc_xo_gpll0,
359 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
360 .ops = &clk_rcg2_ops,
361 },
362 };
363
364 static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {
365 .cmd_rcgr = 0x08e0,
366 .hid_width = 5,
367 .parent_map = gcc_xo_gpll0_map,
368 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
369 .clkr.hw.init = &(struct clk_init_data){
370 .name = "blsp1_qup6_i2c_apps_clk_src",
371 .parent_data = gcc_xo_gpll0,
372 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
373 .ops = &clk_rcg2_ops,
374 },
375 };
376
377 static struct freq_tbl ftbl_blsp1_qup6_spi_apps_clk_src[] = {
378 F(960000, P_XO, 10, 1, 2),
379 F(4800000, P_XO, 4, 0, 0),
380 F(9600000, P_XO, 2, 0, 0),
381 F(15000000, P_GPLL0, 10, 1, 4),
382 F(19200000, P_XO, 1, 0, 0),
383 F(24000000, P_GPLL0, 12.5, 1, 2),
384 F(27906976, P_GPLL0, 1, 2, 43),
385 F(41380000, P_GPLL0, 15, 0, 0),
386 F(42860000, P_GPLL0, 14, 0, 0),
387 { }
388 };
389
390 static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {
391 .cmd_rcgr = 0x08cc,
392 .mnd_width = 8,
393 .hid_width = 5,
394 .parent_map = gcc_xo_gpll0_map,
395 .freq_tbl = ftbl_blsp1_qup6_spi_apps_clk_src,
396 .clkr.hw.init = &(struct clk_init_data){
397 .name = "blsp1_qup6_spi_apps_clk_src",
398 .parent_data = gcc_xo_gpll0,
399 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
400 .ops = &clk_rcg2_ops,
401 },
402 };
403
404 static struct freq_tbl ftbl_blsp_uart_apps_clk_src[] = {
405 F(3686400, P_GPLL0, 1, 96, 15625),
406 F(7372800, P_GPLL0, 1, 192, 15625),
407 F(14745600, P_GPLL0, 1, 384, 15625),
408 F(16000000, P_GPLL0, 5, 2, 15),
409 F(19200000, P_XO, 1, 0, 0),
410 F(24000000, P_GPLL0, 5, 1, 5),
411 F(32000000, P_GPLL0, 1, 4, 75),
412 F(40000000, P_GPLL0, 15, 0, 0),
413 F(46400000, P_GPLL0, 1, 29, 375),
414 F(48000000, P_GPLL0, 12.5, 0, 0),
415 F(51200000, P_GPLL0, 1, 32, 375),
416 F(56000000, P_GPLL0, 1, 7, 75),
417 F(58982400, P_GPLL0, 1, 1536, 15625),
418 F(60000000, P_GPLL0, 10, 0, 0),
419 F(63160000, P_GPLL0, 9.5, 0, 0),
420 { }
421 };
422
423 static struct clk_rcg2 blsp1_uart1_apps_clk_src = {
424 .cmd_rcgr = 0x068c,
425 .mnd_width = 16,
426 .hid_width = 5,
427 .parent_map = gcc_xo_gpll0_map,
428 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
429 .clkr.hw.init = &(struct clk_init_data){
430 .name = "blsp1_uart1_apps_clk_src",
431 .parent_data = gcc_xo_gpll0,
432 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
433 .ops = &clk_rcg2_ops,
434 },
435 };
436
437 static struct clk_rcg2 blsp1_uart2_apps_clk_src = {
438 .cmd_rcgr = 0x070c,
439 .mnd_width = 16,
440 .hid_width = 5,
441 .parent_map = gcc_xo_gpll0_map,
442 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
443 .clkr.hw.init = &(struct clk_init_data){
444 .name = "blsp1_uart2_apps_clk_src",
445 .parent_data = gcc_xo_gpll0,
446 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
447 .ops = &clk_rcg2_ops,
448 },
449 };
450
451 static struct clk_rcg2 blsp1_uart3_apps_clk_src = {
452 .cmd_rcgr = 0x078c,
453 .mnd_width = 16,
454 .hid_width = 5,
455 .parent_map = gcc_xo_gpll0_map,
456 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
457 .clkr.hw.init = &(struct clk_init_data){
458 .name = "blsp1_uart3_apps_clk_src",
459 .parent_data = gcc_xo_gpll0,
460 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
461 .ops = &clk_rcg2_ops,
462 },
463 };
464
465 static struct clk_rcg2 blsp1_uart4_apps_clk_src = {
466 .cmd_rcgr = 0x080c,
467 .mnd_width = 16,
468 .hid_width = 5,
469 .parent_map = gcc_xo_gpll0_map,
470 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
471 .clkr.hw.init = &(struct clk_init_data){
472 .name = "blsp1_uart4_apps_clk_src",
473 .parent_data = gcc_xo_gpll0,
474 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
475 .ops = &clk_rcg2_ops,
476 },
477 };
478
479 static struct clk_rcg2 blsp1_uart5_apps_clk_src = {
480 .cmd_rcgr = 0x088c,
481 .mnd_width = 16,
482 .hid_width = 5,
483 .parent_map = gcc_xo_gpll0_map,
484 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
485 .clkr.hw.init = &(struct clk_init_data){
486 .name = "blsp1_uart5_apps_clk_src",
487 .parent_data = gcc_xo_gpll0,
488 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
489 .ops = &clk_rcg2_ops,
490 },
491 };
492
493 static struct clk_rcg2 blsp1_uart6_apps_clk_src = {
494 .cmd_rcgr = 0x090c,
495 .mnd_width = 16,
496 .hid_width = 5,
497 .parent_map = gcc_xo_gpll0_map,
498 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
499 .clkr.hw.init = &(struct clk_init_data){
500 .name = "blsp1_uart6_apps_clk_src",
501 .parent_data = gcc_xo_gpll0,
502 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
503 .ops = &clk_rcg2_ops,
504 },
505 };
506
507 static struct clk_rcg2 blsp2_qup1_i2c_apps_clk_src = {
508 .cmd_rcgr = 0x09a0,
509 .hid_width = 5,
510 .parent_map = gcc_xo_gpll0_map,
511 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
512 .clkr.hw.init = &(struct clk_init_data){
513 .name = "blsp2_qup1_i2c_apps_clk_src",
514 .parent_data = gcc_xo_gpll0,
515 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
516 .ops = &clk_rcg2_ops,
517 },
518 };
519
520 static struct freq_tbl ftbl_blsp2_qup1_2_spi_apps_clk_src[] = {
521 F(960000, P_XO, 10, 1, 2),
522 F(4800000, P_XO, 4, 0, 0),
523 F(9600000, P_XO, 2, 0, 0),
524 F(15000000, P_GPLL0, 10, 1, 4),
525 F(19200000, P_XO, 1, 0, 0),
526 F(24000000, P_GPLL0, 12.5, 1, 2),
527 F(25000000, P_GPLL0, 12, 1, 2),
528 F(42860000, P_GPLL0, 14, 0, 0),
529 F(44440000, P_GPLL0, 13.5, 0, 0),
530 { }
531 };
532
533 static struct clk_rcg2 blsp2_qup1_spi_apps_clk_src = {
534 .cmd_rcgr = 0x098c,
535 .mnd_width = 8,
536 .hid_width = 5,
537 .parent_map = gcc_xo_gpll0_map,
538 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
539 .clkr.hw.init = &(struct clk_init_data){
540 .name = "blsp2_qup1_spi_apps_clk_src",
541 .parent_data = gcc_xo_gpll0,
542 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
543 .ops = &clk_rcg2_ops,
544 },
545 };
546
547 static struct clk_rcg2 blsp2_qup2_i2c_apps_clk_src = {
548 .cmd_rcgr = 0x0a20,
549 .hid_width = 5,
550 .parent_map = gcc_xo_gpll0_map,
551 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
552 .clkr.hw.init = &(struct clk_init_data){
553 .name = "blsp2_qup2_i2c_apps_clk_src",
554 .parent_data = gcc_xo_gpll0,
555 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
556 .ops = &clk_rcg2_ops,
557 },
558 };
559
560 static struct clk_rcg2 blsp2_qup2_spi_apps_clk_src = {
561 .cmd_rcgr = 0x0a0c,
562 .mnd_width = 8,
563 .hid_width = 5,
564 .parent_map = gcc_xo_gpll0_map,
565 .freq_tbl = ftbl_blsp2_qup1_2_spi_apps_clk_src,
566 .clkr.hw.init = &(struct clk_init_data){
567 .name = "blsp2_qup2_spi_apps_clk_src",
568 .parent_data = gcc_xo_gpll0,
569 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
570 .ops = &clk_rcg2_ops,
571 },
572 };
573
574 static struct freq_tbl ftbl_blsp2_qup3_4_spi_apps_clk_src[] = {
575 F(960000, P_XO, 10, 1, 2),
576 F(4800000, P_XO, 4, 0, 0),
577 F(9600000, P_XO, 2, 0, 0),
578 F(15000000, P_GPLL0, 10, 1, 4),
579 F(19200000, P_XO, 1, 0, 0),
580 F(24000000, P_GPLL0, 12.5, 1, 2),
581 F(25000000, P_GPLL0, 12, 1, 2),
582 F(42860000, P_GPLL0, 14, 0, 0),
583 F(48000000, P_GPLL0, 12.5, 0, 0),
584 { }
585 };
586
587 static struct clk_rcg2 blsp2_qup3_i2c_apps_clk_src = {
588 .cmd_rcgr = 0x0aa0,
589 .hid_width = 5,
590 .parent_map = gcc_xo_gpll0_map,
591 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
592 .clkr.hw.init = &(struct clk_init_data){
593 .name = "blsp2_qup3_i2c_apps_clk_src",
594 .parent_data = gcc_xo_gpll0,
595 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
596 .ops = &clk_rcg2_ops,
597 },
598 };
599
600 static struct clk_rcg2 blsp2_qup3_spi_apps_clk_src = {
601 .cmd_rcgr = 0x0a8c,
602 .mnd_width = 8,
603 .hid_width = 5,
604 .parent_map = gcc_xo_gpll0_map,
605 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
606 .clkr.hw.init = &(struct clk_init_data){
607 .name = "blsp2_qup3_spi_apps_clk_src",
608 .parent_data = gcc_xo_gpll0,
609 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
610 .ops = &clk_rcg2_ops,
611 },
612 };
613
614 static struct clk_rcg2 blsp2_qup4_i2c_apps_clk_src = {
615 .cmd_rcgr = 0x0b20,
616 .hid_width = 5,
617 .parent_map = gcc_xo_gpll0_map,
618 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
619 .clkr.hw.init = &(struct clk_init_data){
620 .name = "blsp2_qup4_i2c_apps_clk_src",
621 .parent_data = gcc_xo_gpll0,
622 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
623 .ops = &clk_rcg2_ops,
624 },
625 };
626
627 static struct clk_rcg2 blsp2_qup4_spi_apps_clk_src = {
628 .cmd_rcgr = 0x0b0c,
629 .mnd_width = 8,
630 .hid_width = 5,
631 .parent_map = gcc_xo_gpll0_map,
632 .freq_tbl = ftbl_blsp2_qup3_4_spi_apps_clk_src,
633 .clkr.hw.init = &(struct clk_init_data){
634 .name = "blsp2_qup4_spi_apps_clk_src",
635 .parent_data = gcc_xo_gpll0,
636 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
637 .ops = &clk_rcg2_ops,
638 },
639 };
640
641 static struct clk_rcg2 blsp2_qup5_i2c_apps_clk_src = {
642 .cmd_rcgr = 0x0ba0,
643 .hid_width = 5,
644 .parent_map = gcc_xo_gpll0_map,
645 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
646 .clkr.hw.init = &(struct clk_init_data){
647 .name = "blsp2_qup5_i2c_apps_clk_src",
648 .parent_data = gcc_xo_gpll0,
649 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
650 .ops = &clk_rcg2_ops,
651 },
652 };
653
654 static struct clk_rcg2 blsp2_qup5_spi_apps_clk_src = {
655 .cmd_rcgr = 0x0b8c,
656 .mnd_width = 8,
657 .hid_width = 5,
658 .parent_map = gcc_xo_gpll0_map,
659 /* BLSP1 QUP1 and BLSP2 QUP5 use the same freqs */
660 .freq_tbl = ftbl_blsp1_qup1_spi_apps_clk_src,
661 .clkr.hw.init = &(struct clk_init_data){
662 .name = "blsp2_qup5_spi_apps_clk_src",
663 .parent_data = gcc_xo_gpll0,
664 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
665 .ops = &clk_rcg2_ops,
666 },
667 };
668
669 static struct clk_rcg2 blsp2_qup6_i2c_apps_clk_src = {
670 .cmd_rcgr = 0x0c20,
671 .hid_width = 5,
672 .parent_map = gcc_xo_gpll0_map,
673 .freq_tbl = ftbl_blsp_i2c_apps_clk_src,
674 .clkr.hw.init = &(struct clk_init_data){
675 .name = "blsp2_qup6_i2c_apps_clk_src",
676 .parent_data = gcc_xo_gpll0,
677 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
678 .ops = &clk_rcg2_ops,
679 },
680 };
681
682 static struct freq_tbl ftbl_blsp2_qup6_spi_apps_clk_src[] = {
683 F(960000, P_XO, 10, 1, 2),
684 F(4800000, P_XO, 4, 0, 0),
685 F(9600000, P_XO, 2, 0, 0),
686 F(15000000, P_GPLL0, 10, 1, 4),
687 F(19200000, P_XO, 1, 0, 0),
688 F(24000000, P_GPLL0, 12.5, 1, 2),
689 F(25000000, P_GPLL0, 12, 1, 2),
690 F(44440000, P_GPLL0, 13.5, 0, 0),
691 F(48000000, P_GPLL0, 12.5, 0, 0),
692 { }
693 };
694
695 static struct clk_rcg2 blsp2_qup6_spi_apps_clk_src = {
696 .cmd_rcgr = 0x0c0c,
697 .mnd_width = 8,
698 .hid_width = 5,
699 .parent_map = gcc_xo_gpll0_map,
700 .freq_tbl = ftbl_blsp2_qup6_spi_apps_clk_src,
701 .clkr.hw.init = &(struct clk_init_data){
702 .name = "blsp2_qup6_spi_apps_clk_src",
703 .parent_data = gcc_xo_gpll0,
704 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
705 .ops = &clk_rcg2_ops,
706 },
707 };
708
709 static struct clk_rcg2 blsp2_uart1_apps_clk_src = {
710 .cmd_rcgr = 0x09cc,
711 .mnd_width = 16,
712 .hid_width = 5,
713 .parent_map = gcc_xo_gpll0_map,
714 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
715 .clkr.hw.init = &(struct clk_init_data){
716 .name = "blsp2_uart1_apps_clk_src",
717 .parent_data = gcc_xo_gpll0,
718 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
719 .ops = &clk_rcg2_ops,
720 },
721 };
722
723 static struct clk_rcg2 blsp2_uart2_apps_clk_src = {
724 .cmd_rcgr = 0x0a4c,
725 .mnd_width = 16,
726 .hid_width = 5,
727 .parent_map = gcc_xo_gpll0_map,
728 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
729 .clkr.hw.init = &(struct clk_init_data){
730 .name = "blsp2_uart2_apps_clk_src",
731 .parent_data = gcc_xo_gpll0,
732 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
733 .ops = &clk_rcg2_ops,
734 },
735 };
736
737 static struct clk_rcg2 blsp2_uart3_apps_clk_src = {
738 .cmd_rcgr = 0x0acc,
739 .mnd_width = 16,
740 .hid_width = 5,
741 .parent_map = gcc_xo_gpll0_map,
742 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
743 .clkr.hw.init = &(struct clk_init_data){
744 .name = "blsp2_uart3_apps_clk_src",
745 .parent_data = gcc_xo_gpll0,
746 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
747 .ops = &clk_rcg2_ops,
748 },
749 };
750
751 static struct clk_rcg2 blsp2_uart4_apps_clk_src = {
752 .cmd_rcgr = 0x0b4c,
753 .mnd_width = 16,
754 .hid_width = 5,
755 .parent_map = gcc_xo_gpll0_map,
756 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
757 .clkr.hw.init = &(struct clk_init_data){
758 .name = "blsp2_uart4_apps_clk_src",
759 .parent_data = gcc_xo_gpll0,
760 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
761 .ops = &clk_rcg2_ops,
762 },
763 };
764
765 static struct clk_rcg2 blsp2_uart5_apps_clk_src = {
766 .cmd_rcgr = 0x0bcc,
767 .mnd_width = 16,
768 .hid_width = 5,
769 .parent_map = gcc_xo_gpll0_map,
770 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
771 .clkr.hw.init = &(struct clk_init_data){
772 .name = "blsp2_uart5_apps_clk_src",
773 .parent_data = gcc_xo_gpll0,
774 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
775 .ops = &clk_rcg2_ops,
776 },
777 };
778
779 static struct clk_rcg2 blsp2_uart6_apps_clk_src = {
780 .cmd_rcgr = 0x0c4c,
781 .mnd_width = 16,
782 .hid_width = 5,
783 .parent_map = gcc_xo_gpll0_map,
784 .freq_tbl = ftbl_blsp_uart_apps_clk_src,
785 .clkr.hw.init = &(struct clk_init_data){
786 .name = "blsp2_uart6_apps_clk_src",
787 .parent_data = gcc_xo_gpll0,
788 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
789 .ops = &clk_rcg2_ops,
790 },
791 };
792
793 static struct freq_tbl ftbl_gp1_clk_src[] = {
794 F(19200000, P_XO, 1, 0, 0),
795 F(100000000, P_GPLL0, 6, 0, 0),
796 F(200000000, P_GPLL0, 3, 0, 0),
797 { }
798 };
799
800 static struct clk_rcg2 gp1_clk_src = {
801 .cmd_rcgr = 0x1904,
802 .mnd_width = 8,
803 .hid_width = 5,
804 .parent_map = gcc_xo_gpll0_map,
805 .freq_tbl = ftbl_gp1_clk_src,
806 .clkr.hw.init = &(struct clk_init_data){
807 .name = "gp1_clk_src",
808 .parent_data = gcc_xo_gpll0,
809 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
810 .ops = &clk_rcg2_ops,
811 },
812 };
813
814 static struct freq_tbl ftbl_gp2_clk_src[] = {
815 F(19200000, P_XO, 1, 0, 0),
816 F(100000000, P_GPLL0, 6, 0, 0),
817 F(200000000, P_GPLL0, 3, 0, 0),
818 { }
819 };
820
821 static struct clk_rcg2 gp2_clk_src = {
822 .cmd_rcgr = 0x1944,
823 .mnd_width = 8,
824 .hid_width = 5,
825 .parent_map = gcc_xo_gpll0_map,
826 .freq_tbl = ftbl_gp2_clk_src,
827 .clkr.hw.init = &(struct clk_init_data){
828 .name = "gp2_clk_src",
829 .parent_data = gcc_xo_gpll0,
830 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
831 .ops = &clk_rcg2_ops,
832 },
833 };
834
835 static struct freq_tbl ftbl_gp3_clk_src[] = {
836 F(19200000, P_XO, 1, 0, 0),
837 F(100000000, P_GPLL0, 6, 0, 0),
838 F(200000000, P_GPLL0, 3, 0, 0),
839 { }
840 };
841
842 static struct clk_rcg2 gp3_clk_src = {
843 .cmd_rcgr = 0x1984,
844 .mnd_width = 8,
845 .hid_width = 5,
846 .parent_map = gcc_xo_gpll0_map,
847 .freq_tbl = ftbl_gp3_clk_src,
848 .clkr.hw.init = &(struct clk_init_data){
849 .name = "gp3_clk_src",
850 .parent_data = gcc_xo_gpll0,
851 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
852 .ops = &clk_rcg2_ops,
853 },
854 };
855
856 static struct freq_tbl ftbl_pcie_0_aux_clk_src[] = {
857 F(1011000, P_XO, 1, 1, 19),
858 { }
859 };
860
861 static struct clk_rcg2 pcie_0_aux_clk_src = {
862 .cmd_rcgr = 0x1b00,
863 .mnd_width = 8,
864 .hid_width = 5,
865 .freq_tbl = ftbl_pcie_0_aux_clk_src,
866 .clkr.hw.init = &(struct clk_init_data){
867 .name = "pcie_0_aux_clk_src",
868 .parent_data = &(const struct clk_parent_data){
869 .fw_name = "xo",
870 },
871 .num_parents = 1,
872 .ops = &clk_rcg2_ops,
873 },
874 };
875
876 static struct freq_tbl ftbl_pcie_pipe_clk_src[] = {
877 F(125000000, P_XO, 1, 0, 0),
878 { }
879 };
880
881 static struct clk_rcg2 pcie_0_pipe_clk_src = {
882 .cmd_rcgr = 0x1adc,
883 .hid_width = 5,
884 .freq_tbl = ftbl_pcie_pipe_clk_src,
885 .clkr.hw.init = &(struct clk_init_data){
886 .name = "pcie_0_pipe_clk_src",
887 .parent_data = &(const struct clk_parent_data){
888 .fw_name = "xo",
889 },
890 .num_parents = 1,
891 .ops = &clk_rcg2_ops,
892 },
893 };
894
895 static struct freq_tbl ftbl_pcie_1_aux_clk_src[] = {
896 F(1011000, P_XO, 1, 1, 19),
897 { }
898 };
899
900 static struct clk_rcg2 pcie_1_aux_clk_src = {
901 .cmd_rcgr = 0x1b80,
902 .mnd_width = 8,
903 .hid_width = 5,
904 .freq_tbl = ftbl_pcie_1_aux_clk_src,
905 .clkr.hw.init = &(struct clk_init_data){
906 .name = "pcie_1_aux_clk_src",
907 .parent_data = &(const struct clk_parent_data){
908 .fw_name = "xo",
909 },
910 .num_parents = 1,
911 .ops = &clk_rcg2_ops,
912 },
913 };
914
915 static struct clk_rcg2 pcie_1_pipe_clk_src = {
916 .cmd_rcgr = 0x1b5c,
917 .hid_width = 5,
918 .freq_tbl = ftbl_pcie_pipe_clk_src,
919 .clkr.hw.init = &(struct clk_init_data){
920 .name = "pcie_1_pipe_clk_src",
921 .parent_data = &(const struct clk_parent_data){
922 .fw_name = "xo",
923 },
924 .num_parents = 1,
925 .ops = &clk_rcg2_ops,
926 },
927 };
928
929 static struct freq_tbl ftbl_pdm2_clk_src[] = {
930 F(60000000, P_GPLL0, 10, 0, 0),
931 { }
932 };
933
934 static struct clk_rcg2 pdm2_clk_src = {
935 .cmd_rcgr = 0x0cd0,
936 .hid_width = 5,
937 .parent_map = gcc_xo_gpll0_map,
938 .freq_tbl = ftbl_pdm2_clk_src,
939 .clkr.hw.init = &(struct clk_init_data){
940 .name = "pdm2_clk_src",
941 .parent_data = gcc_xo_gpll0,
942 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
943 .ops = &clk_rcg2_ops,
944 },
945 };
946
947 static struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {
948 F(144000, P_XO, 16, 3, 25),
949 F(400000, P_XO, 12, 1, 4),
950 F(20000000, P_GPLL0, 15, 1, 2),
951 F(25000000, P_GPLL0, 12, 1, 2),
952 F(50000000, P_GPLL0, 12, 0, 0),
953 F(100000000, P_GPLL0, 6, 0, 0),
954 F(192000000, P_GPLL4, 2, 0, 0),
955 F(384000000, P_GPLL4, 1, 0, 0),
956 { }
957 };
958
959 static struct freq_tbl ftbl_sdcc1_apps_clk_src_8992[] = {
960 F(144000, P_XO, 16, 3, 25),
961 F(400000, P_XO, 12, 1, 4),
962 F(20000000, P_GPLL0, 15, 1, 2),
963 F(25000000, P_GPLL0, 12, 1, 2),
964 F(50000000, P_GPLL0, 12, 0, 0),
965 F(100000000, P_GPLL0, 6, 0, 0),
966 F(172000000, P_GPLL4, 2, 0, 0),
967 F(344000000, P_GPLL4, 1, 0, 0),
968 { }
969 };
970
971 static struct clk_rcg2 sdcc1_apps_clk_src = {
972 .cmd_rcgr = 0x04d0,
973 .mnd_width = 8,
974 .hid_width = 5,
975 .parent_map = gcc_xo_gpll0_gpll4_map,
976 .freq_tbl = ftbl_sdcc1_apps_clk_src,
977 .clkr.hw.init = &(struct clk_init_data){
978 .name = "sdcc1_apps_clk_src",
979 .parent_data = gcc_xo_gpll0_gpll4,
980 .num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),
981 .ops = &clk_rcg2_floor_ops,
982 },
983 };
984
985 static struct freq_tbl ftbl_sdcc2_4_apps_clk_src[] = {
986 F(144000, P_XO, 16, 3, 25),
987 F(400000, P_XO, 12, 1, 4),
988 F(20000000, P_GPLL0, 15, 1, 2),
989 F(25000000, P_GPLL0, 12, 1, 2),
990 F(50000000, P_GPLL0, 12, 0, 0),
991 F(100000000, P_GPLL0, 6, 0, 0),
992 F(200000000, P_GPLL0, 3, 0, 0),
993 { }
994 };
995
996 static struct clk_rcg2 sdcc2_apps_clk_src = {
997 .cmd_rcgr = 0x0510,
998 .mnd_width = 8,
999 .hid_width = 5,
1000 .parent_map = gcc_xo_gpll0_map,
1001 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1002 .clkr.hw.init = &(struct clk_init_data){
1003 .name = "sdcc2_apps_clk_src",
1004 .parent_data = gcc_xo_gpll0,
1005 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1006 .ops = &clk_rcg2_floor_ops,
1007 },
1008 };
1009
1010 static struct clk_rcg2 sdcc3_apps_clk_src = {
1011 .cmd_rcgr = 0x0550,
1012 .mnd_width = 8,
1013 .hid_width = 5,
1014 .parent_map = gcc_xo_gpll0_map,
1015 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1016 .clkr.hw.init = &(struct clk_init_data){
1017 .name = "sdcc3_apps_clk_src",
1018 .parent_data = gcc_xo_gpll0,
1019 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1020 .ops = &clk_rcg2_floor_ops,
1021 },
1022 };
1023
1024 static struct clk_rcg2 sdcc4_apps_clk_src = {
1025 .cmd_rcgr = 0x0590,
1026 .mnd_width = 8,
1027 .hid_width = 5,
1028 .parent_map = gcc_xo_gpll0_map,
1029 .freq_tbl = ftbl_sdcc2_4_apps_clk_src,
1030 .clkr.hw.init = &(struct clk_init_data){
1031 .name = "sdcc4_apps_clk_src",
1032 .parent_data = gcc_xo_gpll0,
1033 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1034 .ops = &clk_rcg2_floor_ops,
1035 },
1036 };
1037
1038 static struct freq_tbl ftbl_tsif_ref_clk_src[] = {
1039 F(105500, P_XO, 1, 1, 182),
1040 { }
1041 };
1042
1043 static struct clk_rcg2 tsif_ref_clk_src = {
1044 .cmd_rcgr = 0x0d90,
1045 .mnd_width = 8,
1046 .hid_width = 5,
1047 .freq_tbl = ftbl_tsif_ref_clk_src,
1048 .clkr.hw.init = &(struct clk_init_data){
1049 .name = "tsif_ref_clk_src",
1050 .parent_data = &(const struct clk_parent_data){
1051 .fw_name = "xo",
1052 },
1053 .num_parents = 1,
1054 .ops = &clk_rcg2_ops,
1055 },
1056 };
1057
1058 static struct freq_tbl ftbl_usb30_mock_utmi_clk_src[] = {
1059 F(19200000, P_XO, 1, 0, 0),
1060 F(60000000, P_GPLL0, 10, 0, 0),
1061 { }
1062 };
1063
1064 static struct clk_rcg2 usb30_mock_utmi_clk_src = {
1065 .cmd_rcgr = 0x03e8,
1066 .hid_width = 5,
1067 .parent_map = gcc_xo_gpll0_map,
1068 .freq_tbl = ftbl_usb30_mock_utmi_clk_src,
1069 .clkr.hw.init = &(struct clk_init_data){
1070 .name = "usb30_mock_utmi_clk_src",
1071 .parent_data = gcc_xo_gpll0,
1072 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1073 .ops = &clk_rcg2_ops,
1074 },
1075 };
1076
1077 static struct freq_tbl ftbl_usb3_phy_aux_clk_src[] = {
1078 F(1200000, P_XO, 16, 0, 0),
1079 { }
1080 };
1081
1082 static struct clk_rcg2 usb3_phy_aux_clk_src = {
1083 .cmd_rcgr = 0x1414,
1084 .hid_width = 5,
1085 .freq_tbl = ftbl_usb3_phy_aux_clk_src,
1086 .clkr.hw.init = &(struct clk_init_data){
1087 .name = "usb3_phy_aux_clk_src",
1088 .parent_data = &(const struct clk_parent_data){
1089 .fw_name = "xo",
1090 },
1091 .num_parents = 1,
1092 .ops = &clk_rcg2_ops,
1093 },
1094 };
1095
1096 static struct freq_tbl ftbl_usb_hs_system_clk_src[] = {
1097 F(75000000, P_GPLL0, 8, 0, 0),
1098 { }
1099 };
1100
1101 static struct clk_rcg2 usb_hs_system_clk_src = {
1102 .cmd_rcgr = 0x0490,
1103 .hid_width = 5,
1104 .parent_map = gcc_xo_gpll0_map,
1105 .freq_tbl = ftbl_usb_hs_system_clk_src,
1106 .clkr.hw.init = &(struct clk_init_data){
1107 .name = "usb_hs_system_clk_src",
1108 .parent_data = gcc_xo_gpll0,
1109 .num_parents = ARRAY_SIZE(gcc_xo_gpll0),
1110 .ops = &clk_rcg2_ops,
1111 },
1112 };
1113
1114 static struct clk_branch gcc_blsp1_ahb_clk = {
1115 .halt_reg = 0x05c4,
1116 .halt_check = BRANCH_HALT_VOTED,
1117 .clkr = {
1118 .enable_reg = 0x1484,
1119 .enable_mask = BIT(17),
1120 .hw.init = &(struct clk_init_data){
1121 .name = "gcc_blsp1_ahb_clk",
1122 .ops = &clk_branch2_ops,
1123 },
1124 },
1125 };
1126
1127 static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1128 .halt_reg = 0x0648,
1129 .clkr = {
1130 .enable_reg = 0x0648,
1131 .enable_mask = BIT(0),
1132 .hw.init = &(struct clk_init_data){
1133 .name = "gcc_blsp1_qup1_i2c_apps_clk",
1134 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_i2c_apps_clk_src.clkr.hw },
1135 .num_parents = 1,
1136 .flags = CLK_SET_RATE_PARENT,
1137 .ops = &clk_branch2_ops,
1138 },
1139 },
1140 };
1141
1142 static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1143 .halt_reg = 0x0644,
1144 .clkr = {
1145 .enable_reg = 0x0644,
1146 .enable_mask = BIT(0),
1147 .hw.init = &(struct clk_init_data){
1148 .name = "gcc_blsp1_qup1_spi_apps_clk",
1149 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup1_spi_apps_clk_src.clkr.hw },
1150 .num_parents = 1,
1151 .flags = CLK_SET_RATE_PARENT,
1152 .ops = &clk_branch2_ops,
1153 },
1154 },
1155 };
1156
1157 static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1158 .halt_reg = 0x06c8,
1159 .clkr = {
1160 .enable_reg = 0x06c8,
1161 .enable_mask = BIT(0),
1162 .hw.init = &(struct clk_init_data){
1163 .name = "gcc_blsp1_qup2_i2c_apps_clk",
1164 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_i2c_apps_clk_src.clkr.hw },
1165 .num_parents = 1,
1166 .flags = CLK_SET_RATE_PARENT,
1167 .ops = &clk_branch2_ops,
1168 },
1169 },
1170 };
1171
1172 static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1173 .halt_reg = 0x06c4,
1174 .clkr = {
1175 .enable_reg = 0x06c4,
1176 .enable_mask = BIT(0),
1177 .hw.init = &(struct clk_init_data){
1178 .name = "gcc_blsp1_qup2_spi_apps_clk",
1179 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup2_spi_apps_clk_src.clkr.hw },
1180 .num_parents = 1,
1181 .flags = CLK_SET_RATE_PARENT,
1182 .ops = &clk_branch2_ops,
1183 },
1184 },
1185 };
1186
1187 static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1188 .halt_reg = 0x0748,
1189 .clkr = {
1190 .enable_reg = 0x0748,
1191 .enable_mask = BIT(0),
1192 .hw.init = &(struct clk_init_data){
1193 .name = "gcc_blsp1_qup3_i2c_apps_clk",
1194 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_i2c_apps_clk_src.clkr.hw },
1195 .num_parents = 1,
1196 .flags = CLK_SET_RATE_PARENT,
1197 .ops = &clk_branch2_ops,
1198 },
1199 },
1200 };
1201
1202 static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1203 .halt_reg = 0x0744,
1204 .clkr = {
1205 .enable_reg = 0x0744,
1206 .enable_mask = BIT(0),
1207 .hw.init = &(struct clk_init_data){
1208 .name = "gcc_blsp1_qup3_spi_apps_clk",
1209 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup3_spi_apps_clk_src.clkr.hw },
1210 .num_parents = 1,
1211 .flags = CLK_SET_RATE_PARENT,
1212 .ops = &clk_branch2_ops,
1213 },
1214 },
1215 };
1216
1217 static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1218 .halt_reg = 0x07c8,
1219 .clkr = {
1220 .enable_reg = 0x07c8,
1221 .enable_mask = BIT(0),
1222 .hw.init = &(struct clk_init_data){
1223 .name = "gcc_blsp1_qup4_i2c_apps_clk",
1224 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_i2c_apps_clk_src.clkr.hw },
1225 .num_parents = 1,
1226 .flags = CLK_SET_RATE_PARENT,
1227 .ops = &clk_branch2_ops,
1228 },
1229 },
1230 };
1231
1232 static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1233 .halt_reg = 0x07c4,
1234 .clkr = {
1235 .enable_reg = 0x07c4,
1236 .enable_mask = BIT(0),
1237 .hw.init = &(struct clk_init_data){
1238 .name = "gcc_blsp1_qup4_spi_apps_clk",
1239 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup4_spi_apps_clk_src.clkr.hw },
1240 .num_parents = 1,
1241 .flags = CLK_SET_RATE_PARENT,
1242 .ops = &clk_branch2_ops,
1243 },
1244 },
1245 };
1246
1247 static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1248 .halt_reg = 0x0848,
1249 .clkr = {
1250 .enable_reg = 0x0848,
1251 .enable_mask = BIT(0),
1252 .hw.init = &(struct clk_init_data){
1253 .name = "gcc_blsp1_qup5_i2c_apps_clk",
1254 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_i2c_apps_clk_src.clkr.hw },
1255 .num_parents = 1,
1256 .flags = CLK_SET_RATE_PARENT,
1257 .ops = &clk_branch2_ops,
1258 },
1259 },
1260 };
1261
1262 static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1263 .halt_reg = 0x0844,
1264 .clkr = {
1265 .enable_reg = 0x0844,
1266 .enable_mask = BIT(0),
1267 .hw.init = &(struct clk_init_data){
1268 .name = "gcc_blsp1_qup5_spi_apps_clk",
1269 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup5_spi_apps_clk_src.clkr.hw },
1270 .num_parents = 1,
1271 .flags = CLK_SET_RATE_PARENT,
1272 .ops = &clk_branch2_ops,
1273 },
1274 },
1275 };
1276
1277 static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1278 .halt_reg = 0x08c8,
1279 .clkr = {
1280 .enable_reg = 0x08c8,
1281 .enable_mask = BIT(0),
1282 .hw.init = &(struct clk_init_data){
1283 .name = "gcc_blsp1_qup6_i2c_apps_clk",
1284 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_i2c_apps_clk_src.clkr.hw },
1285 .num_parents = 1,
1286 .flags = CLK_SET_RATE_PARENT,
1287 .ops = &clk_branch2_ops,
1288 },
1289 },
1290 };
1291
1292 static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1293 .halt_reg = 0x08c4,
1294 .clkr = {
1295 .enable_reg = 0x08c4,
1296 .enable_mask = BIT(0),
1297 .hw.init = &(struct clk_init_data){
1298 .name = "gcc_blsp1_qup6_spi_apps_clk",
1299 .parent_hws = (const struct clk_hw *[]){ &blsp1_qup6_spi_apps_clk_src.clkr.hw },
1300 .num_parents = 1,
1301 .flags = CLK_SET_RATE_PARENT,
1302 .ops = &clk_branch2_ops,
1303 },
1304 },
1305 };
1306
1307 static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1308 .halt_reg = 0x0684,
1309 .clkr = {
1310 .enable_reg = 0x0684,
1311 .enable_mask = BIT(0),
1312 .hw.init = &(struct clk_init_data){
1313 .name = "gcc_blsp1_uart1_apps_clk",
1314 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart1_apps_clk_src.clkr.hw },
1315 .num_parents = 1,
1316 .flags = CLK_SET_RATE_PARENT,
1317 .ops = &clk_branch2_ops,
1318 },
1319 },
1320 };
1321
1322 static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1323 .halt_reg = 0x0704,
1324 .clkr = {
1325 .enable_reg = 0x0704,
1326 .enable_mask = BIT(0),
1327 .hw.init = &(struct clk_init_data){
1328 .name = "gcc_blsp1_uart2_apps_clk",
1329 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart2_apps_clk_src.clkr.hw },
1330 .num_parents = 1,
1331 .flags = CLK_SET_RATE_PARENT,
1332 .ops = &clk_branch2_ops,
1333 },
1334 },
1335 };
1336
1337 static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1338 .halt_reg = 0x0784,
1339 .clkr = {
1340 .enable_reg = 0x0784,
1341 .enable_mask = BIT(0),
1342 .hw.init = &(struct clk_init_data){
1343 .name = "gcc_blsp1_uart3_apps_clk",
1344 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart3_apps_clk_src.clkr.hw },
1345 .num_parents = 1,
1346 .flags = CLK_SET_RATE_PARENT,
1347 .ops = &clk_branch2_ops,
1348 },
1349 },
1350 };
1351
1352 static struct clk_branch gcc_blsp1_uart4_apps_clk = {
1353 .halt_reg = 0x0804,
1354 .clkr = {
1355 .enable_reg = 0x0804,
1356 .enable_mask = BIT(0),
1357 .hw.init = &(struct clk_init_data){
1358 .name = "gcc_blsp1_uart4_apps_clk",
1359 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart4_apps_clk_src.clkr.hw },
1360 .num_parents = 1,
1361 .flags = CLK_SET_RATE_PARENT,
1362 .ops = &clk_branch2_ops,
1363 },
1364 },
1365 };
1366
1367 static struct clk_branch gcc_blsp1_uart5_apps_clk = {
1368 .halt_reg = 0x0884,
1369 .clkr = {
1370 .enable_reg = 0x0884,
1371 .enable_mask = BIT(0),
1372 .hw.init = &(struct clk_init_data){
1373 .name = "gcc_blsp1_uart5_apps_clk",
1374 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart5_apps_clk_src.clkr.hw },
1375 .num_parents = 1,
1376 .flags = CLK_SET_RATE_PARENT,
1377 .ops = &clk_branch2_ops,
1378 },
1379 },
1380 };
1381
1382 static struct clk_branch gcc_blsp1_uart6_apps_clk = {
1383 .halt_reg = 0x0904,
1384 .clkr = {
1385 .enable_reg = 0x0904,
1386 .enable_mask = BIT(0),
1387 .hw.init = &(struct clk_init_data){
1388 .name = "gcc_blsp1_uart6_apps_clk",
1389 .parent_hws = (const struct clk_hw *[]){ &blsp1_uart6_apps_clk_src.clkr.hw },
1390 .num_parents = 1,
1391 .flags = CLK_SET_RATE_PARENT,
1392 .ops = &clk_branch2_ops,
1393 },
1394 },
1395 };
1396
1397 static struct clk_branch gcc_blsp2_ahb_clk = {
1398 .halt_reg = 0x0944,
1399 .halt_check = BRANCH_HALT_VOTED,
1400 .clkr = {
1401 .enable_reg = 0x1484,
1402 .enable_mask = BIT(15),
1403 .hw.init = &(struct clk_init_data){
1404 .name = "gcc_blsp2_ahb_clk",
1405 .ops = &clk_branch2_ops,
1406 },
1407 },
1408 };
1409
1410 static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1411 .halt_reg = 0x0988,
1412 .clkr = {
1413 .enable_reg = 0x0988,
1414 .enable_mask = BIT(0),
1415 .hw.init = &(struct clk_init_data){
1416 .name = "gcc_blsp2_qup1_i2c_apps_clk",
1417 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_i2c_apps_clk_src.clkr.hw },
1418 .num_parents = 1,
1419 .flags = CLK_SET_RATE_PARENT,
1420 .ops = &clk_branch2_ops,
1421 },
1422 },
1423 };
1424
1425 static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1426 .halt_reg = 0x0984,
1427 .clkr = {
1428 .enable_reg = 0x0984,
1429 .enable_mask = BIT(0),
1430 .hw.init = &(struct clk_init_data){
1431 .name = "gcc_blsp2_qup1_spi_apps_clk",
1432 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup1_spi_apps_clk_src.clkr.hw },
1433 .num_parents = 1,
1434 .flags = CLK_SET_RATE_PARENT,
1435 .ops = &clk_branch2_ops,
1436 },
1437 },
1438 };
1439
1440 static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1441 .halt_reg = 0x0a08,
1442 .clkr = {
1443 .enable_reg = 0x0a08,
1444 .enable_mask = BIT(0),
1445 .hw.init = &(struct clk_init_data){
1446 .name = "gcc_blsp2_qup2_i2c_apps_clk",
1447 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_i2c_apps_clk_src.clkr.hw },
1448 .num_parents = 1,
1449 .flags = CLK_SET_RATE_PARENT,
1450 .ops = &clk_branch2_ops,
1451 },
1452 },
1453 };
1454
1455 static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1456 .halt_reg = 0x0a04,
1457 .clkr = {
1458 .enable_reg = 0x0a04,
1459 .enable_mask = BIT(0),
1460 .hw.init = &(struct clk_init_data){
1461 .name = "gcc_blsp2_qup2_spi_apps_clk",
1462 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup2_spi_apps_clk_src.clkr.hw },
1463 .num_parents = 1,
1464 .flags = CLK_SET_RATE_PARENT,
1465 .ops = &clk_branch2_ops,
1466 },
1467 },
1468 };
1469
1470 static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1471 .halt_reg = 0x0a88,
1472 .clkr = {
1473 .enable_reg = 0x0a88,
1474 .enable_mask = BIT(0),
1475 .hw.init = &(struct clk_init_data){
1476 .name = "gcc_blsp2_qup3_i2c_apps_clk",
1477 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_i2c_apps_clk_src.clkr.hw },
1478 .num_parents = 1,
1479 .flags = CLK_SET_RATE_PARENT,
1480 .ops = &clk_branch2_ops,
1481 },
1482 },
1483 };
1484
1485 static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1486 .halt_reg = 0x0a84,
1487 .clkr = {
1488 .enable_reg = 0x0a84,
1489 .enable_mask = BIT(0),
1490 .hw.init = &(struct clk_init_data){
1491 .name = "gcc_blsp2_qup3_spi_apps_clk",
1492 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup3_spi_apps_clk_src.clkr.hw },
1493 .num_parents = 1,
1494 .flags = CLK_SET_RATE_PARENT,
1495 .ops = &clk_branch2_ops,
1496 },
1497 },
1498 };
1499
1500 static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1501 .halt_reg = 0x0b08,
1502 .clkr = {
1503 .enable_reg = 0x0b08,
1504 .enable_mask = BIT(0),
1505 .hw.init = &(struct clk_init_data){
1506 .name = "gcc_blsp2_qup4_i2c_apps_clk",
1507 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_i2c_apps_clk_src.clkr.hw },
1508 .num_parents = 1,
1509 .flags = CLK_SET_RATE_PARENT,
1510 .ops = &clk_branch2_ops,
1511 },
1512 },
1513 };
1514
1515 static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1516 .halt_reg = 0x0b04,
1517 .clkr = {
1518 .enable_reg = 0x0b04,
1519 .enable_mask = BIT(0),
1520 .hw.init = &(struct clk_init_data){
1521 .name = "gcc_blsp2_qup4_spi_apps_clk",
1522 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup4_spi_apps_clk_src.clkr.hw },
1523 .num_parents = 1,
1524 .flags = CLK_SET_RATE_PARENT,
1525 .ops = &clk_branch2_ops,
1526 },
1527 },
1528 };
1529
1530 static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1531 .halt_reg = 0x0b88,
1532 .clkr = {
1533 .enable_reg = 0x0b88,
1534 .enable_mask = BIT(0),
1535 .hw.init = &(struct clk_init_data){
1536 .name = "gcc_blsp2_qup5_i2c_apps_clk",
1537 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_i2c_apps_clk_src.clkr.hw },
1538 .num_parents = 1,
1539 .flags = CLK_SET_RATE_PARENT,
1540 .ops = &clk_branch2_ops,
1541 },
1542 },
1543 };
1544
1545 static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1546 .halt_reg = 0x0b84,
1547 .clkr = {
1548 .enable_reg = 0x0b84,
1549 .enable_mask = BIT(0),
1550 .hw.init = &(struct clk_init_data){
1551 .name = "gcc_blsp2_qup5_spi_apps_clk",
1552 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup5_spi_apps_clk_src.clkr.hw },
1553 .num_parents = 1,
1554 .flags = CLK_SET_RATE_PARENT,
1555 .ops = &clk_branch2_ops,
1556 },
1557 },
1558 };
1559
1560 static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1561 .halt_reg = 0x0c08,
1562 .clkr = {
1563 .enable_reg = 0x0c08,
1564 .enable_mask = BIT(0),
1565 .hw.init = &(struct clk_init_data){
1566 .name = "gcc_blsp2_qup6_i2c_apps_clk",
1567 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_i2c_apps_clk_src.clkr.hw },
1568 .num_parents = 1,
1569 .flags = CLK_SET_RATE_PARENT,
1570 .ops = &clk_branch2_ops,
1571 },
1572 },
1573 };
1574
1575 static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1576 .halt_reg = 0x0c04,
1577 .clkr = {
1578 .enable_reg = 0x0c04,
1579 .enable_mask = BIT(0),
1580 .hw.init = &(struct clk_init_data){
1581 .name = "gcc_blsp2_qup6_spi_apps_clk",
1582 .parent_hws = (const struct clk_hw *[]){ &blsp2_qup6_spi_apps_clk_src.clkr.hw },
1583 .num_parents = 1,
1584 .flags = CLK_SET_RATE_PARENT,
1585 .ops = &clk_branch2_ops,
1586 },
1587 },
1588 };
1589
1590 static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1591 .halt_reg = 0x09c4,
1592 .clkr = {
1593 .enable_reg = 0x09c4,
1594 .enable_mask = BIT(0),
1595 .hw.init = &(struct clk_init_data){
1596 .name = "gcc_blsp2_uart1_apps_clk",
1597 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart1_apps_clk_src.clkr.hw },
1598 .num_parents = 1,
1599 .flags = CLK_SET_RATE_PARENT,
1600 .ops = &clk_branch2_ops,
1601 },
1602 },
1603 };
1604
1605 static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1606 .halt_reg = 0x0a44,
1607 .clkr = {
1608 .enable_reg = 0x0a44,
1609 .enable_mask = BIT(0),
1610 .hw.init = &(struct clk_init_data){
1611 .name = "gcc_blsp2_uart2_apps_clk",
1612 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart2_apps_clk_src.clkr.hw },
1613 .num_parents = 1,
1614 .flags = CLK_SET_RATE_PARENT,
1615 .ops = &clk_branch2_ops,
1616 },
1617 },
1618 };
1619
1620 static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1621 .halt_reg = 0x0ac4,
1622 .clkr = {
1623 .enable_reg = 0x0ac4,
1624 .enable_mask = BIT(0),
1625 .hw.init = &(struct clk_init_data){
1626 .name = "gcc_blsp2_uart3_apps_clk",
1627 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart3_apps_clk_src.clkr.hw },
1628 .num_parents = 1,
1629 .flags = CLK_SET_RATE_PARENT,
1630 .ops = &clk_branch2_ops,
1631 },
1632 },
1633 };
1634
1635 static struct clk_branch gcc_blsp2_uart4_apps_clk = {
1636 .halt_reg = 0x0b44,
1637 .clkr = {
1638 .enable_reg = 0x0b44,
1639 .enable_mask = BIT(0),
1640 .hw.init = &(struct clk_init_data){
1641 .name = "gcc_blsp2_uart4_apps_clk",
1642 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart4_apps_clk_src.clkr.hw },
1643 .num_parents = 1,
1644 .flags = CLK_SET_RATE_PARENT,
1645 .ops = &clk_branch2_ops,
1646 },
1647 },
1648 };
1649
1650 static struct clk_branch gcc_blsp2_uart5_apps_clk = {
1651 .halt_reg = 0x0bc4,
1652 .clkr = {
1653 .enable_reg = 0x0bc4,
1654 .enable_mask = BIT(0),
1655 .hw.init = &(struct clk_init_data){
1656 .name = "gcc_blsp2_uart5_apps_clk",
1657 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart5_apps_clk_src.clkr.hw },
1658 .num_parents = 1,
1659 .flags = CLK_SET_RATE_PARENT,
1660 .ops = &clk_branch2_ops,
1661 },
1662 },
1663 };
1664
1665 static struct clk_branch gcc_blsp2_uart6_apps_clk = {
1666 .halt_reg = 0x0c44,
1667 .clkr = {
1668 .enable_reg = 0x0c44,
1669 .enable_mask = BIT(0),
1670 .hw.init = &(struct clk_init_data){
1671 .name = "gcc_blsp2_uart6_apps_clk",
1672 .parent_hws = (const struct clk_hw *[]){ &blsp2_uart6_apps_clk_src.clkr.hw },
1673 .num_parents = 1,
1674 .flags = CLK_SET_RATE_PARENT,
1675 .ops = &clk_branch2_ops,
1676 },
1677 },
1678 };
1679
1680 static struct clk_branch gcc_gp1_clk = {
1681 .halt_reg = 0x1900,
1682 .clkr = {
1683 .enable_reg = 0x1900,
1684 .enable_mask = BIT(0),
1685 .hw.init = &(struct clk_init_data){
1686 .name = "gcc_gp1_clk",
1687 .parent_hws = (const struct clk_hw *[]){ &gp1_clk_src.clkr.hw },
1688 .num_parents = 1,
1689 .flags = CLK_SET_RATE_PARENT,
1690 .ops = &clk_branch2_ops,
1691 },
1692 },
1693 };
1694
1695 static struct clk_branch gcc_gp2_clk = {
1696 .halt_reg = 0x1940,
1697 .clkr = {
1698 .enable_reg = 0x1940,
1699 .enable_mask = BIT(0),
1700 .hw.init = &(struct clk_init_data){
1701 .name = "gcc_gp2_clk",
1702 .parent_hws = (const struct clk_hw *[]){ &gp2_clk_src.clkr.hw },
1703 .num_parents = 1,
1704 .flags = CLK_SET_RATE_PARENT,
1705 .ops = &clk_branch2_ops,
1706 },
1707 },
1708 };
1709
1710 static struct clk_branch gcc_gp3_clk = {
1711 .halt_reg = 0x1980,
1712 .clkr = {
1713 .enable_reg = 0x1980,
1714 .enable_mask = BIT(0),
1715 .hw.init = &(struct clk_init_data){
1716 .name = "gcc_gp3_clk",
1717 .parent_hws = (const struct clk_hw *[]){ &gp3_clk_src.clkr.hw },
1718 .num_parents = 1,
1719 .flags = CLK_SET_RATE_PARENT,
1720 .ops = &clk_branch2_ops,
1721 },
1722 },
1723 };
1724
1725 static struct clk_branch gcc_lpass_q6_axi_clk = {
1726 .halt_reg = 0x0280,
1727 .clkr = {
1728 .enable_reg = 0x0280,
1729 .enable_mask = BIT(0),
1730 .hw.init = &(struct clk_init_data){
1731 .name = "gcc_lpass_q6_axi_clk",
1732 .ops = &clk_branch2_ops,
1733 },
1734 },
1735 };
1736
1737 static struct clk_branch gcc_mss_q6_bimc_axi_clk = {
1738 .halt_reg = 0x0284,
1739 .clkr = {
1740 .enable_reg = 0x0284,
1741 .enable_mask = BIT(0),
1742 .hw.init = &(struct clk_init_data){
1743 .name = "gcc_mss_q6_bimc_axi_clk",
1744 .ops = &clk_branch2_ops,
1745 },
1746 },
1747 };
1748
1749 static struct clk_branch gcc_pcie_0_aux_clk = {
1750 .halt_reg = 0x1ad4,
1751 .clkr = {
1752 .enable_reg = 0x1ad4,
1753 .enable_mask = BIT(0),
1754 .hw.init = &(struct clk_init_data){
1755 .name = "gcc_pcie_0_aux_clk",
1756 .parent_hws = (const struct clk_hw *[]){ &pcie_0_aux_clk_src.clkr.hw },
1757 .num_parents = 1,
1758 .flags = CLK_SET_RATE_PARENT,
1759 .ops = &clk_branch2_ops,
1760 },
1761 },
1762 };
1763
1764 static struct clk_branch gcc_pcie_0_cfg_ahb_clk = {
1765 .halt_reg = 0x1ad0,
1766 .clkr = {
1767 .enable_reg = 0x1ad0,
1768 .enable_mask = BIT(0),
1769 .hw.init = &(struct clk_init_data){
1770 .name = "gcc_pcie_0_cfg_ahb_clk",
1771 .ops = &clk_branch2_ops,
1772 },
1773 },
1774 };
1775
1776 static struct clk_branch gcc_pcie_0_mstr_axi_clk = {
1777 .halt_reg = 0x1acc,
1778 .clkr = {
1779 .enable_reg = 0x1acc,
1780 .enable_mask = BIT(0),
1781 .hw.init = &(struct clk_init_data){
1782 .name = "gcc_pcie_0_mstr_axi_clk",
1783 .ops = &clk_branch2_ops,
1784 },
1785 },
1786 };
1787
1788 static struct clk_branch gcc_pcie_0_pipe_clk = {
1789 .halt_reg = 0x1ad8,
1790 .halt_check = BRANCH_HALT_DELAY,
1791 .clkr = {
1792 .enable_reg = 0x1ad8,
1793 .enable_mask = BIT(0),
1794 .hw.init = &(struct clk_init_data){
1795 .name = "gcc_pcie_0_pipe_clk",
1796 .parent_hws = (const struct clk_hw *[]){ &pcie_0_pipe_clk_src.clkr.hw },
1797 .num_parents = 1,
1798 .flags = CLK_SET_RATE_PARENT,
1799 .ops = &clk_branch2_ops,
1800 },
1801 },
1802 };
1803
1804 static struct clk_branch gcc_pcie_0_slv_axi_clk = {
1805 .halt_reg = 0x1ac8,
1806 .halt_check = BRANCH_HALT_DELAY,
1807 .clkr = {
1808 .enable_reg = 0x1ac8,
1809 .enable_mask = BIT(0),
1810 .hw.init = &(struct clk_init_data){
1811 .name = "gcc_pcie_0_slv_axi_clk",
1812 .ops = &clk_branch2_ops,
1813 },
1814 },
1815 };
1816
1817 static struct clk_branch gcc_pcie_1_aux_clk = {
1818 .halt_reg = 0x1b54,
1819 .clkr = {
1820 .enable_reg = 0x1b54,
1821 .enable_mask = BIT(0),
1822 .hw.init = &(struct clk_init_data){
1823 .name = "gcc_pcie_1_aux_clk",
1824 .parent_hws = (const struct clk_hw *[]){ &pcie_1_aux_clk_src.clkr.hw },
1825 .num_parents = 1,
1826 .flags = CLK_SET_RATE_PARENT,
1827 .ops = &clk_branch2_ops,
1828 },
1829 },
1830 };
1831
1832 static struct clk_branch gcc_pcie_1_cfg_ahb_clk = {
1833 .halt_reg = 0x1b54,
1834 .clkr = {
1835 .enable_reg = 0x1b54,
1836 .enable_mask = BIT(0),
1837 .hw.init = &(struct clk_init_data){
1838 .name = "gcc_pcie_1_cfg_ahb_clk",
1839 .ops = &clk_branch2_ops,
1840 },
1841 },
1842 };
1843
1844 static struct clk_branch gcc_pcie_1_mstr_axi_clk = {
1845 .halt_reg = 0x1b50,
1846 .clkr = {
1847 .enable_reg = 0x1b50,
1848 .enable_mask = BIT(0),
1849 .hw.init = &(struct clk_init_data){
1850 .name = "gcc_pcie_1_mstr_axi_clk",
1851 .ops = &clk_branch2_ops,
1852 },
1853 },
1854 };
1855
1856 static struct clk_branch gcc_pcie_1_pipe_clk = {
1857 .halt_reg = 0x1b58,
1858 .halt_check = BRANCH_HALT_DELAY,
1859 .clkr = {
1860 .enable_reg = 0x1b58,
1861 .enable_mask = BIT(0),
1862 .hw.init = &(struct clk_init_data){
1863 .name = "gcc_pcie_1_pipe_clk",
1864 .parent_hws = (const struct clk_hw *[]){ &pcie_1_pipe_clk_src.clkr.hw },
1865 .num_parents = 1,
1866 .flags = CLK_SET_RATE_PARENT,
1867 .ops = &clk_branch2_ops,
1868 },
1869 },
1870 };
1871
1872 static struct clk_branch gcc_pcie_1_slv_axi_clk = {
1873 .halt_reg = 0x1b48,
1874 .clkr = {
1875 .enable_reg = 0x1b48,
1876 .enable_mask = BIT(0),
1877 .hw.init = &(struct clk_init_data){
1878 .name = "gcc_pcie_1_slv_axi_clk",
1879 .ops = &clk_branch2_ops,
1880 },
1881 },
1882 };
1883
1884 static struct clk_branch gcc_pdm2_clk = {
1885 .halt_reg = 0x0ccc,
1886 .clkr = {
1887 .enable_reg = 0x0ccc,
1888 .enable_mask = BIT(0),
1889 .hw.init = &(struct clk_init_data){
1890 .name = "gcc_pdm2_clk",
1891 .parent_hws = (const struct clk_hw *[]){ &pdm2_clk_src.clkr.hw },
1892 .num_parents = 1,
1893 .flags = CLK_SET_RATE_PARENT,
1894 .ops = &clk_branch2_ops,
1895 },
1896 },
1897 };
1898
1899 static struct clk_branch gcc_pdm_ahb_clk = {
1900 .halt_reg = 0x0cc4,
1901 .clkr = {
1902 .enable_reg = 0x0cc4,
1903 .enable_mask = BIT(0),
1904 .hw.init = &(struct clk_init_data){
1905 .name = "gcc_pdm_ahb_clk",
1906 .ops = &clk_branch2_ops,
1907 },
1908 },
1909 };
1910
1911 static struct clk_branch gcc_sdcc1_apps_clk = {
1912 .halt_reg = 0x04c4,
1913 .clkr = {
1914 .enable_reg = 0x04c4,
1915 .enable_mask = BIT(0),
1916 .hw.init = &(struct clk_init_data){
1917 .name = "gcc_sdcc1_apps_clk",
1918 .parent_hws = (const struct clk_hw *[]){ &sdcc1_apps_clk_src.clkr.hw },
1919 .num_parents = 1,
1920 .flags = CLK_SET_RATE_PARENT,
1921 .ops = &clk_branch2_ops,
1922 },
1923 },
1924 };
1925
1926 static struct clk_branch gcc_sdcc1_ahb_clk = {
1927 .halt_reg = 0x04c8,
1928 .clkr = {
1929 .enable_reg = 0x04c8,
1930 .enable_mask = BIT(0),
1931 .hw.init = &(struct clk_init_data){
1932 .name = "gcc_sdcc1_ahb_clk",
1933 .ops = &clk_branch2_ops,
1934 },
1935 },
1936 };
1937
1938 static struct clk_branch gcc_sdcc2_ahb_clk = {
1939 .halt_reg = 0x0508,
1940 .clkr = {
1941 .enable_reg = 0x0508,
1942 .enable_mask = BIT(0),
1943 .hw.init = &(struct clk_init_data){
1944 .name = "gcc_sdcc2_ahb_clk",
1945 .ops = &clk_branch2_ops,
1946 },
1947 },
1948 };
1949
1950 static struct clk_branch gcc_sdcc2_apps_clk = {
1951 .halt_reg = 0x0504,
1952 .clkr = {
1953 .enable_reg = 0x0504,
1954 .enable_mask = BIT(0),
1955 .hw.init = &(struct clk_init_data){
1956 .name = "gcc_sdcc2_apps_clk",
1957 .parent_hws = (const struct clk_hw *[]){ &sdcc2_apps_clk_src.clkr.hw },
1958 .num_parents = 1,
1959 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops,
1961 },
1962 },
1963 };
1964
1965 static struct clk_branch gcc_sdcc3_ahb_clk = {
1966 .halt_reg = 0x0548,
1967 .clkr = {
1968 .enable_reg = 0x0548,
1969 .enable_mask = BIT(0),
1970 .hw.init = &(struct clk_init_data){
1971 .name = "gcc_sdcc3_ahb_clk",
1972 .ops = &clk_branch2_ops,
1973 },
1974 },
1975 };
1976
1977 static struct clk_branch gcc_sdcc3_apps_clk = {
1978 .halt_reg = 0x0544,
1979 .clkr = {
1980 .enable_reg = 0x0544,
1981 .enable_mask = BIT(0),
1982 .hw.init = &(struct clk_init_data){
1983 .name = "gcc_sdcc3_apps_clk",
1984 .parent_hws = (const struct clk_hw *[]){ &sdcc3_apps_clk_src.clkr.hw },
1985 .num_parents = 1,
1986 .flags = CLK_SET_RATE_PARENT,
1987 .ops = &clk_branch2_ops,
1988 },
1989 },
1990 };
1991
1992 static struct clk_branch gcc_sdcc4_ahb_clk = {
1993 .halt_reg = 0x0588,
1994 .clkr = {
1995 .enable_reg = 0x0588,
1996 .enable_mask = BIT(0),
1997 .hw.init = &(struct clk_init_data){
1998 .name = "gcc_sdcc4_ahb_clk",
1999 .ops = &clk_branch2_ops,
2000 },
2001 },
2002 };
2003
2004 static struct clk_branch gcc_sdcc4_apps_clk = {
2005 .halt_reg = 0x0584,
2006 .clkr = {
2007 .enable_reg = 0x0584,
2008 .enable_mask = BIT(0),
2009 .hw.init = &(struct clk_init_data){
2010 .name = "gcc_sdcc4_apps_clk",
2011 .parent_hws = (const struct clk_hw *[]){ &sdcc4_apps_clk_src.clkr.hw },
2012 .num_parents = 1,
2013 .flags = CLK_SET_RATE_PARENT,
2014 .ops = &clk_branch2_ops,
2015 },
2016 },
2017 };
2018
2019 static struct clk_branch gcc_sys_noc_ufs_axi_clk = {
2020 .halt_reg = 0x1d7c,
2021 .clkr = {
2022 .enable_reg = 0x1d7c,
2023 .enable_mask = BIT(0),
2024 .hw.init = &(struct clk_init_data){
2025 .name = "gcc_sys_noc_ufs_axi_clk",
2026 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2027 .num_parents = 1,
2028 .flags = CLK_SET_RATE_PARENT,
2029 .ops = &clk_branch2_ops,
2030 },
2031 },
2032 };
2033
2034 static struct clk_branch gcc_sys_noc_usb3_axi_clk = {
2035 .halt_reg = 0x03fc,
2036 .clkr = {
2037 .enable_reg = 0x03fc,
2038 .enable_mask = BIT(0),
2039 .hw.init = &(struct clk_init_data){
2040 .name = "gcc_sys_noc_usb3_axi_clk",
2041 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2042 .num_parents = 1,
2043 .flags = CLK_SET_RATE_PARENT,
2044 .ops = &clk_branch2_ops,
2045 },
2046 },
2047 };
2048
2049 static struct clk_branch gcc_tsif_ahb_clk = {
2050 .halt_reg = 0x0d84,
2051 .clkr = {
2052 .enable_reg = 0x0d84,
2053 .enable_mask = BIT(0),
2054 .hw.init = &(struct clk_init_data){
2055 .name = "gcc_tsif_ahb_clk",
2056 .ops = &clk_branch2_ops,
2057 },
2058 },
2059 };
2060
2061 static struct clk_branch gcc_tsif_ref_clk = {
2062 .halt_reg = 0x0d88,
2063 .clkr = {
2064 .enable_reg = 0x0d88,
2065 .enable_mask = BIT(0),
2066 .hw.init = &(struct clk_init_data){
2067 .name = "gcc_tsif_ref_clk",
2068 .parent_hws = (const struct clk_hw *[]){ &tsif_ref_clk_src.clkr.hw },
2069 .num_parents = 1,
2070 .flags = CLK_SET_RATE_PARENT,
2071 .ops = &clk_branch2_ops,
2072 },
2073 },
2074 };
2075
2076 static struct clk_branch gcc_ufs_ahb_clk = {
2077 .halt_reg = 0x1d4c,
2078 .clkr = {
2079 .enable_reg = 0x1d4c,
2080 .enable_mask = BIT(0),
2081 .hw.init = &(struct clk_init_data){
2082 .name = "gcc_ufs_ahb_clk",
2083 .ops = &clk_branch2_ops,
2084 },
2085 },
2086 };
2087
2088 static struct clk_branch gcc_ufs_axi_clk = {
2089 .halt_reg = 0x1d48,
2090 .clkr = {
2091 .enable_reg = 0x1d48,
2092 .enable_mask = BIT(0),
2093 .hw.init = &(struct clk_init_data){
2094 .name = "gcc_ufs_axi_clk",
2095 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2096 .num_parents = 1,
2097 .flags = CLK_SET_RATE_PARENT,
2098 .ops = &clk_branch2_ops,
2099 },
2100 },
2101 };
2102
2103 static struct clk_branch gcc_ufs_rx_cfg_clk = {
2104 .halt_reg = 0x1d54,
2105 .clkr = {
2106 .enable_reg = 0x1d54,
2107 .enable_mask = BIT(0),
2108 .hw.init = &(struct clk_init_data){
2109 .name = "gcc_ufs_rx_cfg_clk",
2110 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2111 .num_parents = 1,
2112 .flags = CLK_SET_RATE_PARENT,
2113 .ops = &clk_branch2_ops,
2114 },
2115 },
2116 };
2117
2118 static struct clk_branch gcc_ufs_rx_symbol_0_clk = {
2119 .halt_reg = 0x1d60,
2120 .halt_check = BRANCH_HALT_DELAY,
2121 .clkr = {
2122 .enable_reg = 0x1d60,
2123 .enable_mask = BIT(0),
2124 .hw.init = &(struct clk_init_data){
2125 .name = "gcc_ufs_rx_symbol_0_clk",
2126 .ops = &clk_branch2_ops,
2127 },
2128 },
2129 };
2130
2131 static struct clk_branch gcc_ufs_rx_symbol_1_clk = {
2132 .halt_reg = 0x1d64,
2133 .halt_check = BRANCH_HALT_DELAY,
2134 .clkr = {
2135 .enable_reg = 0x1d64,
2136 .enable_mask = BIT(0),
2137 .hw.init = &(struct clk_init_data){
2138 .name = "gcc_ufs_rx_symbol_1_clk",
2139 .ops = &clk_branch2_ops,
2140 },
2141 },
2142 };
2143
2144 static struct clk_branch gcc_ufs_tx_cfg_clk = {
2145 .halt_reg = 0x1d50,
2146 .clkr = {
2147 .enable_reg = 0x1d50,
2148 .enable_mask = BIT(0),
2149 .hw.init = &(struct clk_init_data){
2150 .name = "gcc_ufs_tx_cfg_clk",
2151 .parent_hws = (const struct clk_hw *[]){ &ufs_axi_clk_src.clkr.hw },
2152 .num_parents = 1,
2153 .flags = CLK_SET_RATE_PARENT,
2154 .ops = &clk_branch2_ops,
2155 },
2156 },
2157 };
2158
2159 static struct clk_branch gcc_ufs_tx_symbol_0_clk = {
2160 .halt_reg = 0x1d58,
2161 .halt_check = BRANCH_HALT_DELAY,
2162 .clkr = {
2163 .enable_reg = 0x1d58,
2164 .enable_mask = BIT(0),
2165 .hw.init = &(struct clk_init_data){
2166 .name = "gcc_ufs_tx_symbol_0_clk",
2167 .ops = &clk_branch2_ops,
2168 },
2169 },
2170 };
2171
2172 static struct clk_branch gcc_ufs_tx_symbol_1_clk = {
2173 .halt_reg = 0x1d5c,
2174 .halt_check = BRANCH_HALT_DELAY,
2175 .clkr = {
2176 .enable_reg = 0x1d5c,
2177 .enable_mask = BIT(0),
2178 .hw.init = &(struct clk_init_data){
2179 .name = "gcc_ufs_tx_symbol_1_clk",
2180 .ops = &clk_branch2_ops,
2181 },
2182 },
2183 };
2184
2185 static struct clk_branch gcc_usb2_hs_phy_sleep_clk = {
2186 .halt_reg = 0x04ac,
2187 .clkr = {
2188 .enable_reg = 0x04ac,
2189 .enable_mask = BIT(0),
2190 .hw.init = &(struct clk_init_data){
2191 .name = "gcc_usb2_hs_phy_sleep_clk",
2192 .parent_data = &(const struct clk_parent_data){
2193 .fw_name = "sleep",
2194 .name = "sleep"
2195 },
2196 .num_parents = 1,
2197 .ops = &clk_branch2_ops,
2198 },
2199 },
2200 };
2201
2202 static struct clk_branch gcc_usb30_master_clk = {
2203 .halt_reg = 0x03c8,
2204 .clkr = {
2205 .enable_reg = 0x03c8,
2206 .enable_mask = BIT(0),
2207 .hw.init = &(struct clk_init_data){
2208 .name = "gcc_usb30_master_clk",
2209 .parent_hws = (const struct clk_hw *[]){ &usb30_master_clk_src.clkr.hw },
2210 .num_parents = 1,
2211 .flags = CLK_SET_RATE_PARENT,
2212 .ops = &clk_branch2_ops,
2213 },
2214 },
2215 };
2216
2217 static struct clk_branch gcc_usb30_mock_utmi_clk = {
2218 .halt_reg = 0x03d0,
2219 .clkr = {
2220 .enable_reg = 0x03d0,
2221 .enable_mask = BIT(0),
2222 .hw.init = &(struct clk_init_data){
2223 .name = "gcc_usb30_mock_utmi_clk",
2224 .parent_hws = (const struct clk_hw *[]){ &usb30_mock_utmi_clk_src.clkr.hw },
2225 .num_parents = 1,
2226 .flags = CLK_SET_RATE_PARENT,
2227 .ops = &clk_branch2_ops,
2228 },
2229 },
2230 };
2231
2232 static struct clk_branch gcc_usb30_sleep_clk = {
2233 .halt_reg = 0x03cc,
2234 .clkr = {
2235 .enable_reg = 0x03cc,
2236 .enable_mask = BIT(0),
2237 .hw.init = &(struct clk_init_data){
2238 .name = "gcc_usb30_sleep_clk",
2239 .parent_data = &(const struct clk_parent_data){
2240 .fw_name = "sleep",
2241 .name = "sleep"
2242 },
2243 .num_parents = 1,
2244 .ops = &clk_branch2_ops,
2245 },
2246 },
2247 };
2248
2249 static struct clk_branch gcc_usb3_phy_aux_clk = {
2250 .halt_reg = 0x1408,
2251 .clkr = {
2252 .enable_reg = 0x1408,
2253 .enable_mask = BIT(0),
2254 .hw.init = &(struct clk_init_data){
2255 .name = "gcc_usb3_phy_aux_clk",
2256 .parent_hws = (const struct clk_hw *[]){ &usb3_phy_aux_clk_src.clkr.hw },
2257 .num_parents = 1,
2258 .flags = CLK_SET_RATE_PARENT,
2259 .ops = &clk_branch2_ops,
2260 },
2261 },
2262 };
2263
2264 static struct clk_branch gcc_usb3_phy_pipe_clk = {
2265 .halt_reg = 0x140c,
2266 .halt_check = BRANCH_HALT_SKIP,
2267 .clkr = {
2268 .enable_reg = 0x140c,
2269 .enable_mask = BIT(0),
2270 .hw.init = &(struct clk_init_data){
2271 .name = "gcc_usb3_phy_pipe_clk",
2272 .ops = &clk_branch2_ops,
2273 },
2274 },
2275 };
2276
2277 static struct clk_branch gcc_usb_hs_ahb_clk = {
2278 .halt_reg = 0x0488,
2279 .clkr = {
2280 .enable_reg = 0x0488,
2281 .enable_mask = BIT(0),
2282 .hw.init = &(struct clk_init_data){
2283 .name = "gcc_usb_hs_ahb_clk",
2284 .ops = &clk_branch2_ops,
2285 },
2286 },
2287 };
2288
2289 static struct clk_branch gcc_usb_hs_system_clk = {
2290 .halt_reg = 0x0484,
2291 .clkr = {
2292 .enable_reg = 0x0484,
2293 .enable_mask = BIT(0),
2294 .hw.init = &(struct clk_init_data){
2295 .name = "gcc_usb_hs_system_clk",
2296 .parent_hws = (const struct clk_hw *[]){ &usb_hs_system_clk_src.clkr.hw },
2297 .num_parents = 1,
2298 .flags = CLK_SET_RATE_PARENT,
2299 .ops = &clk_branch2_ops,
2300 },
2301 },
2302 };
2303
2304 static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = {
2305 .halt_reg = 0x1a84,
2306 .clkr = {
2307 .enable_reg = 0x1a84,
2308 .enable_mask = BIT(0),
2309 .hw.init = &(struct clk_init_data){
2310 .name = "gcc_usb_phy_cfg_ahb2phy_clk",
2311 .ops = &clk_branch2_ops,
2312 },
2313 },
2314 };
2315
2316 static struct clk_branch gpll0_out_mmsscc = {
2317 .halt_check = BRANCH_HALT_DELAY,
2318 .clkr = {
2319 .enable_reg = 0x1484,
2320 .enable_mask = BIT(26),
2321 .hw.init = &(struct clk_init_data){
2322 .name = "gpll0_out_mmsscc",
2323 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2324 .num_parents = 1,
2325 .ops = &clk_branch2_ops,
2326 },
2327 },
2328 };
2329
2330 static struct clk_branch gpll0_out_msscc = {
2331 .halt_check = BRANCH_HALT_DELAY,
2332 .clkr = {
2333 .enable_reg = 0x1484,
2334 .enable_mask = BIT(27),
2335 .hw.init = &(struct clk_init_data){
2336 .name = "gpll0_out_msscc",
2337 .parent_hws = (const struct clk_hw *[]){ &gpll0.clkr.hw },
2338 .num_parents = 1,
2339 .ops = &clk_branch2_ops,
2340 },
2341 },
2342 };
2343
2344 static struct clk_branch pcie_0_phy_ldo = {
2345 .halt_reg = 0x1e00,
2346 .halt_check = BRANCH_HALT_SKIP,
2347 .clkr = {
2348 .enable_reg = 0x1E00,
2349 .enable_mask = BIT(0),
2350 .hw.init = &(struct clk_init_data){
2351 .name = "pcie_0_phy_ldo",
2352 .ops = &clk_branch2_ops,
2353 },
2354 },
2355 };
2356
2357 static struct clk_branch pcie_1_phy_ldo = {
2358 .halt_reg = 0x1e04,
2359 .halt_check = BRANCH_HALT_SKIP,
2360 .clkr = {
2361 .enable_reg = 0x1E04,
2362 .enable_mask = BIT(0),
2363 .hw.init = &(struct clk_init_data){
2364 .name = "pcie_1_phy_ldo",
2365 .ops = &clk_branch2_ops,
2366 },
2367 },
2368 };
2369
2370 static struct clk_branch ufs_phy_ldo = {
2371 .halt_reg = 0x1e0c,
2372 .halt_check = BRANCH_HALT_SKIP,
2373 .clkr = {
2374 .enable_reg = 0x1E0C,
2375 .enable_mask = BIT(0),
2376 .hw.init = &(struct clk_init_data){
2377 .name = "ufs_phy_ldo",
2378 .ops = &clk_branch2_ops,
2379 },
2380 },
2381 };
2382
2383 static struct clk_branch usb_ss_phy_ldo = {
2384 .halt_reg = 0x1e08,
2385 .halt_check = BRANCH_HALT_SKIP,
2386 .clkr = {
2387 .enable_reg = 0x1E08,
2388 .enable_mask = BIT(0),
2389 .hw.init = &(struct clk_init_data){
2390 .name = "usb_ss_phy_ldo",
2391 .ops = &clk_branch2_ops,
2392 },
2393 },
2394 };
2395
2396 static struct clk_branch gcc_boot_rom_ahb_clk = {
2397 .halt_reg = 0x0e04,
2398 .halt_check = BRANCH_HALT_VOTED,
2399 .hwcg_reg = 0x0e04,
2400 .hwcg_bit = 1,
2401 .clkr = {
2402 .enable_reg = 0x1484,
2403 .enable_mask = BIT(10),
2404 .hw.init = &(struct clk_init_data){
2405 .name = "gcc_boot_rom_ahb_clk",
2406 .ops = &clk_branch2_ops,
2407 },
2408 },
2409 };
2410
2411 static struct clk_branch gcc_prng_ahb_clk = {
2412 .halt_reg = 0x0d04,
2413 .halt_check = BRANCH_HALT_VOTED,
2414 .clkr = {
2415 .enable_reg = 0x1484,
2416 .enable_mask = BIT(13),
2417 .hw.init = &(struct clk_init_data){
2418 .name = "gcc_prng_ahb_clk",
2419 .ops = &clk_branch2_ops,
2420 },
2421 },
2422 };
2423
2424 static struct gdsc pcie_0_gdsc = {
2425 .gdscr = 0x1ac4,
2426 .pd = {
2427 .name = "pcie_0",
2428 },
2429 .pwrsts = PWRSTS_OFF_ON,
2430 };
2431
2432 static struct gdsc pcie_1_gdsc = {
2433 .gdscr = 0x1b44,
2434 .pd = {
2435 .name = "pcie_1",
2436 },
2437 .pwrsts = PWRSTS_OFF_ON,
2438 };
2439
2440 static struct gdsc usb30_gdsc = {
2441 .gdscr = 0x3c4,
2442 .pd = {
2443 .name = "usb30",
2444 },
2445 .pwrsts = PWRSTS_OFF_ON,
2446 };
2447
2448 static struct gdsc ufs_gdsc = {
2449 .gdscr = 0x1d44,
2450 .pd = {
2451 .name = "ufs",
2452 },
2453 .pwrsts = PWRSTS_OFF_ON,
2454 };
2455
2456 static struct clk_regmap *gcc_msm8994_clocks[] = {
2457 [GPLL0_EARLY] = &gpll0_early.clkr,
2458 [GPLL0] = &gpll0.clkr,
2459 [GPLL4_EARLY] = &gpll4_early.clkr,
2460 [GPLL4] = &gpll4.clkr,
2461 [UFS_AXI_CLK_SRC] = &ufs_axi_clk_src.clkr,
2462 [USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,
2463 [BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,
2464 [BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,
2465 [BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,
2466 [BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,
2467 [BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,
2468 [BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,
2469 [BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,
2470 [BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,
2471 [BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,
2472 [BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,
2473 [BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,
2474 [BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,
2475 [BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,
2476 [BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,
2477 [BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,
2478 [BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,
2479 [BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,
2480 [BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,
2481 [BLSP2_QUP1_I2C_APPS_CLK_SRC] = &blsp2_qup1_i2c_apps_clk_src.clkr,
2482 [BLSP2_QUP1_SPI_APPS_CLK_SRC] = &blsp2_qup1_spi_apps_clk_src.clkr,
2483 [BLSP2_QUP2_I2C_APPS_CLK_SRC] = &blsp2_qup2_i2c_apps_clk_src.clkr,
2484 [BLSP2_QUP2_SPI_APPS_CLK_SRC] = &blsp2_qup2_spi_apps_clk_src.clkr,
2485 [BLSP2_QUP3_I2C_APPS_CLK_SRC] = &blsp2_qup3_i2c_apps_clk_src.clkr,
2486 [BLSP2_QUP3_SPI_APPS_CLK_SRC] = &blsp2_qup3_spi_apps_clk_src.clkr,
2487 [BLSP2_QUP4_I2C_APPS_CLK_SRC] = &blsp2_qup4_i2c_apps_clk_src.clkr,
2488 [BLSP2_QUP4_SPI_APPS_CLK_SRC] = &blsp2_qup4_spi_apps_clk_src.clkr,
2489 [BLSP2_QUP5_I2C_APPS_CLK_SRC] = &blsp2_qup5_i2c_apps_clk_src.clkr,
2490 [BLSP2_QUP5_SPI_APPS_CLK_SRC] = &blsp2_qup5_spi_apps_clk_src.clkr,
2491 [BLSP2_QUP6_I2C_APPS_CLK_SRC] = &blsp2_qup6_i2c_apps_clk_src.clkr,
2492 [BLSP2_QUP6_SPI_APPS_CLK_SRC] = &blsp2_qup6_spi_apps_clk_src.clkr,
2493 [BLSP2_UART1_APPS_CLK_SRC] = &blsp2_uart1_apps_clk_src.clkr,
2494 [BLSP2_UART2_APPS_CLK_SRC] = &blsp2_uart2_apps_clk_src.clkr,
2495 [BLSP2_UART3_APPS_CLK_SRC] = &blsp2_uart3_apps_clk_src.clkr,
2496 [BLSP2_UART4_APPS_CLK_SRC] = &blsp2_uart4_apps_clk_src.clkr,
2497 [BLSP2_UART5_APPS_CLK_SRC] = &blsp2_uart5_apps_clk_src.clkr,
2498 [BLSP2_UART6_APPS_CLK_SRC] = &blsp2_uart6_apps_clk_src.clkr,
2499 [GP1_CLK_SRC] = &gp1_clk_src.clkr,
2500 [GP2_CLK_SRC] = &gp2_clk_src.clkr,
2501 [GP3_CLK_SRC] = &gp3_clk_src.clkr,
2502 [PCIE_0_AUX_CLK_SRC] = &pcie_0_aux_clk_src.clkr,
2503 [PCIE_0_PIPE_CLK_SRC] = &pcie_0_pipe_clk_src.clkr,
2504 [PCIE_1_AUX_CLK_SRC] = &pcie_1_aux_clk_src.clkr,
2505 [PCIE_1_PIPE_CLK_SRC] = &pcie_1_pipe_clk_src.clkr,
2506 [PDM2_CLK_SRC] = &pdm2_clk_src.clkr,
2507 [SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,
2508 [SDCC2_APPS_CLK_SRC] = &sdcc2_apps_clk_src.clkr,
2509 [SDCC3_APPS_CLK_SRC] = &sdcc3_apps_clk_src.clkr,
2510 [SDCC4_APPS_CLK_SRC] = &sdcc4_apps_clk_src.clkr,
2511 [TSIF_REF_CLK_SRC] = &tsif_ref_clk_src.clkr,
2512 [USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,
2513 [USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,
2514 [USB_HS_SYSTEM_CLK_SRC] = &usb_hs_system_clk_src.clkr,
2515 [GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,
2516 [GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,
2517 [GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,
2518 [GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,
2519 [GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,
2520 [GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,
2521 [GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,
2522 [GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,
2523 [GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,
2524 [GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,
2525 [GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,
2526 [GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,
2527 [GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,
2528 [GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,
2529 [GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,
2530 [GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,
2531 [GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,
2532 [GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,
2533 [GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,
2534 [GCC_BLSP2_AHB_CLK] = &gcc_blsp2_ahb_clk.clkr,
2535 [GCC_BLSP2_QUP1_I2C_APPS_CLK] = &gcc_blsp2_qup1_i2c_apps_clk.clkr,
2536 [GCC_BLSP2_QUP1_SPI_APPS_CLK] = &gcc_blsp2_qup1_spi_apps_clk.clkr,
2537 [GCC_BLSP2_QUP2_I2C_APPS_CLK] = &gcc_blsp2_qup2_i2c_apps_clk.clkr,
2538 [GCC_BLSP2_QUP2_SPI_APPS_CLK] = &gcc_blsp2_qup2_spi_apps_clk.clkr,
2539 [GCC_BLSP2_QUP3_I2C_APPS_CLK] = &gcc_blsp2_qup3_i2c_apps_clk.clkr,
2540 [GCC_BLSP2_QUP3_SPI_APPS_CLK] = &gcc_blsp2_qup3_spi_apps_clk.clkr,
2541 [GCC_BLSP2_QUP4_I2C_APPS_CLK] = &gcc_blsp2_qup4_i2c_apps_clk.clkr,
2542 [GCC_BLSP2_QUP4_SPI_APPS_CLK] = &gcc_blsp2_qup4_spi_apps_clk.clkr,
2543 [GCC_BLSP2_QUP5_I2C_APPS_CLK] = &gcc_blsp2_qup5_i2c_apps_clk.clkr,
2544 [GCC_BLSP2_QUP5_SPI_APPS_CLK] = &gcc_blsp2_qup5_spi_apps_clk.clkr,
2545 [GCC_BLSP2_QUP6_I2C_APPS_CLK] = &gcc_blsp2_qup6_i2c_apps_clk.clkr,
2546 [GCC_BLSP2_QUP6_SPI_APPS_CLK] = &gcc_blsp2_qup6_spi_apps_clk.clkr,
2547 [GCC_BLSP2_UART1_APPS_CLK] = &gcc_blsp2_uart1_apps_clk.clkr,
2548 [GCC_BLSP2_UART2_APPS_CLK] = &gcc_blsp2_uart2_apps_clk.clkr,
2549 [GCC_BLSP2_UART3_APPS_CLK] = &gcc_blsp2_uart3_apps_clk.clkr,
2550 [GCC_BLSP2_UART4_APPS_CLK] = &gcc_blsp2_uart4_apps_clk.clkr,
2551 [GCC_BLSP2_UART5_APPS_CLK] = &gcc_blsp2_uart5_apps_clk.clkr,
2552 [GCC_BLSP2_UART6_APPS_CLK] = &gcc_blsp2_uart6_apps_clk.clkr,
2553 [GCC_GP1_CLK] = &gcc_gp1_clk.clkr,
2554 [GCC_GP2_CLK] = &gcc_gp2_clk.clkr,
2555 [GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
2556 [GCC_LPASS_Q6_AXI_CLK] = &gcc_lpass_q6_axi_clk.clkr,
2557 [GCC_MSS_Q6_BIMC_AXI_CLK] = &gcc_mss_q6_bimc_axi_clk.clkr,
2558 [GCC_PCIE_0_AUX_CLK] = &gcc_pcie_0_aux_clk.clkr,
2559 [GCC_PCIE_0_CFG_AHB_CLK] = &gcc_pcie_0_cfg_ahb_clk.clkr,
2560 [GCC_PCIE_0_MSTR_AXI_CLK] = &gcc_pcie_0_mstr_axi_clk.clkr,
2561 [GCC_PCIE_0_PIPE_CLK] = &gcc_pcie_0_pipe_clk.clkr,
2562 [GCC_PCIE_0_SLV_AXI_CLK] = &gcc_pcie_0_slv_axi_clk.clkr,
2563 [GCC_PCIE_1_AUX_CLK] = &gcc_pcie_1_aux_clk.clkr,
2564 [GCC_PCIE_1_CFG_AHB_CLK] = &gcc_pcie_1_cfg_ahb_clk.clkr,
2565 [GCC_PCIE_1_MSTR_AXI_CLK] = &gcc_pcie_1_mstr_axi_clk.clkr,
2566 [GCC_PCIE_1_PIPE_CLK] = &gcc_pcie_1_pipe_clk.clkr,
2567 [GCC_PCIE_1_SLV_AXI_CLK] = &gcc_pcie_1_slv_axi_clk.clkr,
2568 [GCC_PDM2_CLK] = &gcc_pdm2_clk.clkr,
2569 [GCC_PDM_AHB_CLK] = &gcc_pdm_ahb_clk.clkr,
2570 [GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,
2571 [GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,
2572 [GCC_SDCC2_AHB_CLK] = &gcc_sdcc2_ahb_clk.clkr,
2573 [GCC_SDCC2_APPS_CLK] = &gcc_sdcc2_apps_clk.clkr,
2574 [GCC_SDCC3_AHB_CLK] = &gcc_sdcc3_ahb_clk.clkr,
2575 [GCC_SDCC3_APPS_CLK] = &gcc_sdcc3_apps_clk.clkr,
2576 [GCC_SDCC4_AHB_CLK] = &gcc_sdcc4_ahb_clk.clkr,
2577 [GCC_SDCC4_APPS_CLK] = &gcc_sdcc4_apps_clk.clkr,
2578 [GCC_SYS_NOC_UFS_AXI_CLK] = &gcc_sys_noc_ufs_axi_clk.clkr,
2579 [GCC_SYS_NOC_USB3_AXI_CLK] = &gcc_sys_noc_usb3_axi_clk.clkr,
2580 [GCC_TSIF_AHB_CLK] = &gcc_tsif_ahb_clk.clkr,
2581 [GCC_TSIF_REF_CLK] = &gcc_tsif_ref_clk.clkr,
2582 [GCC_UFS_AHB_CLK] = &gcc_ufs_ahb_clk.clkr,
2583 [GCC_UFS_AXI_CLK] = &gcc_ufs_axi_clk.clkr,
2584 [GCC_UFS_RX_CFG_CLK] = &gcc_ufs_rx_cfg_clk.clkr,
2585 [GCC_UFS_RX_SYMBOL_0_CLK] = &gcc_ufs_rx_symbol_0_clk.clkr,
2586 [GCC_UFS_RX_SYMBOL_1_CLK] = &gcc_ufs_rx_symbol_1_clk.clkr,
2587 [GCC_UFS_TX_CFG_CLK] = &gcc_ufs_tx_cfg_clk.clkr,
2588 [GCC_UFS_TX_SYMBOL_0_CLK] = &gcc_ufs_tx_symbol_0_clk.clkr,
2589 [GCC_UFS_TX_SYMBOL_1_CLK] = &gcc_ufs_tx_symbol_1_clk.clkr,
2590 [GCC_USB2_HS_PHY_SLEEP_CLK] = &gcc_usb2_hs_phy_sleep_clk.clkr,
2591 [GCC_USB30_MASTER_CLK] = &gcc_usb30_master_clk.clkr,
2592 [GCC_USB30_MOCK_UTMI_CLK] = &gcc_usb30_mock_utmi_clk.clkr,
2593 [GCC_USB30_SLEEP_CLK] = &gcc_usb30_sleep_clk.clkr,
2594 [GCC_USB3_PHY_AUX_CLK] = &gcc_usb3_phy_aux_clk.clkr,
2595 [GCC_USB3_PHY_PIPE_CLK] = &gcc_usb3_phy_pipe_clk.clkr,
2596 [GCC_USB_HS_AHB_CLK] = &gcc_usb_hs_ahb_clk.clkr,
2597 [GCC_USB_HS_SYSTEM_CLK] = &gcc_usb_hs_system_clk.clkr,
2598 [GCC_USB_PHY_CFG_AHB2PHY_CLK] = &gcc_usb_phy_cfg_ahb2phy_clk.clkr,
2599 [GPLL0_OUT_MMSSCC] = &gpll0_out_mmsscc.clkr,
2600 [GPLL0_OUT_MSSCC] = &gpll0_out_msscc.clkr,
2601 [PCIE_0_PHY_LDO] = &pcie_0_phy_ldo.clkr,
2602 [PCIE_1_PHY_LDO] = &pcie_1_phy_ldo.clkr,
2603 [UFS_PHY_LDO] = &ufs_phy_ldo.clkr,
2604 [USB_SS_PHY_LDO] = &usb_ss_phy_ldo.clkr,
2605 [GCC_BOOT_ROM_AHB_CLK] = &gcc_boot_rom_ahb_clk.clkr,
2606 [GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,
2607
2608 /*
2609 * The following clocks should NOT be managed by this driver, but they once were
2610 * mistakengly added. Now they are only here to indicate that they are not defined
2611 * on purpose, even though the names will stay in the header file (for ABI sanity).
2612 */
2613 [CONFIG_NOC_CLK_SRC] = NULL,
2614 [PERIPH_NOC_CLK_SRC] = NULL,
2615 [SYSTEM_NOC_CLK_SRC] = NULL,
2616 };
2617
2618 static struct gdsc *gcc_msm8994_gdscs[] = {
2619 /* This GDSC does not exist, but ABI has to remain intact */
2620 [PCIE_GDSC] = NULL,
2621 [PCIE_0_GDSC] = &pcie_0_gdsc,
2622 [PCIE_1_GDSC] = &pcie_1_gdsc,
2623 [USB30_GDSC] = &usb30_gdsc,
2624 [UFS_GDSC] = &ufs_gdsc,
2625 };
2626
2627 static const struct qcom_reset_map gcc_msm8994_resets[] = {
2628 [USB3_PHY_RESET] = { 0x1400 },
2629 [USB3PHY_PHY_RESET] = { 0x1404 },
2630 [MSS_RESET] = { 0x1680 },
2631 [PCIE_PHY_0_RESET] = { 0x1b18 },
2632 [PCIE_PHY_1_RESET] = { 0x1b98 },
2633 [QUSB2_PHY_RESET] = { 0x04b8 },
2634 };
2635
2636 static const struct regmap_config gcc_msm8994_regmap_config = {
2637 .reg_bits = 32,
2638 .reg_stride = 4,
2639 .val_bits = 32,
2640 .max_register = 0x2000,
2641 .fast_io = true,
2642 };
2643
2644 static const struct qcom_cc_desc gcc_msm8994_desc = {
2645 .config = &gcc_msm8994_regmap_config,
2646 .clks = gcc_msm8994_clocks,
2647 .num_clks = ARRAY_SIZE(gcc_msm8994_clocks),
2648 .resets = gcc_msm8994_resets,
2649 .num_resets = ARRAY_SIZE(gcc_msm8994_resets),
2650 .gdscs = gcc_msm8994_gdscs,
2651 .num_gdscs = ARRAY_SIZE(gcc_msm8994_gdscs),
2652 };
2653
2654 static const struct of_device_id gcc_msm8994_match_table[] = {
2655 { .compatible = "qcom,gcc-msm8992" },
2656 { .compatible = "qcom,gcc-msm8994" }, /* V2 and V2.1 */
2657 {}
2658 };
2659 MODULE_DEVICE_TABLE(of, gcc_msm8994_match_table);
2660
gcc_msm8994_probe(struct platform_device * pdev)2661 static int gcc_msm8994_probe(struct platform_device *pdev)
2662 {
2663 if (of_device_is_compatible(pdev->dev.of_node, "qcom,gcc-msm8992")) {
2664 /* MSM8992 features less clocks and some have different freq tables */
2665 gcc_msm8994_desc.clks[UFS_AXI_CLK_SRC] = NULL;
2666 gcc_msm8994_desc.clks[GCC_LPASS_Q6_AXI_CLK] = NULL;
2667 gcc_msm8994_desc.clks[UFS_PHY_LDO] = NULL;
2668 gcc_msm8994_desc.clks[GCC_UFS_AHB_CLK] = NULL;
2669 gcc_msm8994_desc.clks[GCC_UFS_AXI_CLK] = NULL;
2670 gcc_msm8994_desc.clks[GCC_UFS_RX_CFG_CLK] = NULL;
2671 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_0_CLK] = NULL;
2672 gcc_msm8994_desc.clks[GCC_UFS_RX_SYMBOL_1_CLK] = NULL;
2673 gcc_msm8994_desc.clks[GCC_UFS_TX_CFG_CLK] = NULL;
2674 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_0_CLK] = NULL;
2675 gcc_msm8994_desc.clks[GCC_UFS_TX_SYMBOL_1_CLK] = NULL;
2676
2677 sdcc1_apps_clk_src.freq_tbl = ftbl_sdcc1_apps_clk_src_8992;
2678 blsp1_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2679 blsp1_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2680 blsp1_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2681 blsp1_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2682 blsp1_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2683 blsp1_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2684 blsp2_qup1_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2685 blsp2_qup2_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2686 blsp2_qup3_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2687 blsp2_qup4_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2688 blsp2_qup5_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2689 blsp2_qup6_i2c_apps_clk_src.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src_8992;
2690
2691 /*
2692 * Some 8992 boards might *possibly* use
2693 * PCIe1 clocks and controller, but it's not
2694 * standard and they should be disabled otherwise.
2695 */
2696 gcc_msm8994_desc.clks[PCIE_1_AUX_CLK_SRC] = NULL;
2697 gcc_msm8994_desc.clks[PCIE_1_PIPE_CLK_SRC] = NULL;
2698 gcc_msm8994_desc.clks[PCIE_1_PHY_LDO] = NULL;
2699 gcc_msm8994_desc.clks[GCC_PCIE_1_AUX_CLK] = NULL;
2700 gcc_msm8994_desc.clks[GCC_PCIE_1_CFG_AHB_CLK] = NULL;
2701 gcc_msm8994_desc.clks[GCC_PCIE_1_MSTR_AXI_CLK] = NULL;
2702 gcc_msm8994_desc.clks[GCC_PCIE_1_PIPE_CLK] = NULL;
2703 gcc_msm8994_desc.clks[GCC_PCIE_1_SLV_AXI_CLK] = NULL;
2704 gcc_msm8994_desc.clks[GCC_SYS_NOC_UFS_AXI_CLK] = NULL;
2705 }
2706
2707 return qcom_cc_probe(pdev, &gcc_msm8994_desc);
2708 }
2709
2710 static struct platform_driver gcc_msm8994_driver = {
2711 .probe = gcc_msm8994_probe,
2712 .driver = {
2713 .name = "gcc-msm8994",
2714 .of_match_table = gcc_msm8994_match_table,
2715 },
2716 };
2717
gcc_msm8994_init(void)2718 static int __init gcc_msm8994_init(void)
2719 {
2720 return platform_driver_register(&gcc_msm8994_driver);
2721 }
2722 core_initcall(gcc_msm8994_init);
2723
gcc_msm8994_exit(void)2724 static void __exit gcc_msm8994_exit(void)
2725 {
2726 platform_driver_unregister(&gcc_msm8994_driver);
2727 }
2728 module_exit(gcc_msm8994_exit);
2729
2730 MODULE_DESCRIPTION("Qualcomm GCC MSM8994 Driver");
2731 MODULE_LICENSE("GPL v2");
2732 MODULE_ALIAS("platform:gcc-msm8994");
2733
