1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 MediaTek Inc.
4 * Author: Wenzhen Yu <Wenzhen Yu@mediatek.com>
5 * Ryder Lee <ryder.lee@mediatek.com>
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/of.h>
10 #include <linux/of_address.h>
11 #include <linux/of_device.h>
12 #include <linux/platform_device.h>
13
14 #include "clk-mtk.h"
15 #include "clk-gate.h"
16
17 #include <dt-bindings/clock/mt7629-clk.h>
18
19 #define GATE_PCIE(_id, _name, _parent, _shift) { \
20 .id = _id, \
21 .name = _name, \
22 .parent_name = _parent, \
23 .regs = &pcie_cg_regs, \
24 .shift = _shift, \
25 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
26 }
27
28 #define GATE_SSUSB(_id, _name, _parent, _shift) { \
29 .id = _id, \
30 .name = _name, \
31 .parent_name = _parent, \
32 .regs = &ssusb_cg_regs, \
33 .shift = _shift, \
34 .ops = &mtk_clk_gate_ops_no_setclr_inv, \
35 }
36
37 static const struct mtk_gate_regs pcie_cg_regs = {
38 .set_ofs = 0x30,
39 .clr_ofs = 0x30,
40 .sta_ofs = 0x30,
41 };
42
43 static const struct mtk_gate_regs ssusb_cg_regs = {
44 .set_ofs = 0x30,
45 .clr_ofs = 0x30,
46 .sta_ofs = 0x30,
47 };
48
49 static const struct mtk_gate ssusb_clks[] = {
50 GATE_SSUSB(CLK_SSUSB_U2_PHY_1P_EN, "ssusb_u2_phy_1p",
51 "to_u2_phy_1p", 0),
52 GATE_SSUSB(CLK_SSUSB_U2_PHY_EN, "ssusb_u2_phy_en", "to_u2_phy", 1),
53 GATE_SSUSB(CLK_SSUSB_REF_EN, "ssusb_ref_en", "to_usb3_ref", 5),
54 GATE_SSUSB(CLK_SSUSB_SYS_EN, "ssusb_sys_en", "to_usb3_sys", 6),
55 GATE_SSUSB(CLK_SSUSB_MCU_EN, "ssusb_mcu_en", "to_usb3_mcu", 7),
56 GATE_SSUSB(CLK_SSUSB_DMA_EN, "ssusb_dma_en", "to_usb3_dma", 8),
57 };
58
59 static const struct mtk_gate pcie_clks[] = {
60 GATE_PCIE(CLK_PCIE_P1_AUX_EN, "pcie_p1_aux_en", "p1_1mhz", 12),
61 GATE_PCIE(CLK_PCIE_P1_OBFF_EN, "pcie_p1_obff_en", "free_run_4mhz", 13),
62 GATE_PCIE(CLK_PCIE_P1_AHB_EN, "pcie_p1_ahb_en", "from_top_ahb", 14),
63 GATE_PCIE(CLK_PCIE_P1_AXI_EN, "pcie_p1_axi_en", "from_top_axi", 15),
64 GATE_PCIE(CLK_PCIE_P1_MAC_EN, "pcie_p1_mac_en", "pcie1_mac_en", 16),
65 GATE_PCIE(CLK_PCIE_P1_PIPE_EN, "pcie_p1_pipe_en", "pcie1_pipe_en", 17),
66 GATE_PCIE(CLK_PCIE_P0_AUX_EN, "pcie_p0_aux_en", "p0_1mhz", 18),
67 GATE_PCIE(CLK_PCIE_P0_OBFF_EN, "pcie_p0_obff_en", "free_run_4mhz", 19),
68 GATE_PCIE(CLK_PCIE_P0_AHB_EN, "pcie_p0_ahb_en", "from_top_ahb", 20),
69 GATE_PCIE(CLK_PCIE_P0_AXI_EN, "pcie_p0_axi_en", "from_top_axi", 21),
70 GATE_PCIE(CLK_PCIE_P0_MAC_EN, "pcie_p0_mac_en", "pcie0_mac_en", 22),
71 GATE_PCIE(CLK_PCIE_P0_PIPE_EN, "pcie_p0_pipe_en", "pcie0_pipe_en", 23),
72 };
73
74 static u16 rst_ofs[] = { 0x34, };
75
76 static const struct mtk_clk_rst_desc clk_rst_desc = {
77 .version = MTK_RST_SIMPLE,
78 .rst_bank_ofs = rst_ofs,
79 .rst_bank_nr = ARRAY_SIZE(rst_ofs),
80 };
81
clk_mt7629_ssusbsys_init(struct platform_device * pdev)82 static int clk_mt7629_ssusbsys_init(struct platform_device *pdev)
83 {
84 struct clk_hw_onecell_data *clk_data;
85 struct device_node *node = pdev->dev.of_node;
86 int r;
87
88 clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
89
90 mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
91 clk_data);
92
93 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
94 if (r)
95 dev_err(&pdev->dev,
96 "could not register clock provider: %s: %d\n",
97 pdev->name, r);
98
99 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
100
101 return r;
102 }
103
clk_mt7629_pciesys_init(struct platform_device * pdev)104 static int clk_mt7629_pciesys_init(struct platform_device *pdev)
105 {
106 struct clk_hw_onecell_data *clk_data;
107 struct device_node *node = pdev->dev.of_node;
108 int r;
109
110 clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
111
112 mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
113 clk_data);
114
115 r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
116 if (r)
117 dev_err(&pdev->dev,
118 "could not register clock provider: %s: %d\n",
119 pdev->name, r);
120
121 mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
122
123 return r;
124 }
125
126 static const struct of_device_id of_match_clk_mt7629_hif[] = {
127 {
128 .compatible = "mediatek,mt7629-pciesys",
129 .data = clk_mt7629_pciesys_init,
130 }, {
131 .compatible = "mediatek,mt7629-ssusbsys",
132 .data = clk_mt7629_ssusbsys_init,
133 }, {
134 /* sentinel */
135 }
136 };
137
clk_mt7629_hif_probe(struct platform_device * pdev)138 static int clk_mt7629_hif_probe(struct platform_device *pdev)
139 {
140 int (*clk_init)(struct platform_device *);
141 int r;
142
143 clk_init = of_device_get_match_data(&pdev->dev);
144 if (!clk_init)
145 return -EINVAL;
146
147 r = clk_init(pdev);
148 if (r)
149 dev_err(&pdev->dev,
150 "could not register clock provider: %s: %d\n",
151 pdev->name, r);
152
153 return r;
154 }
155
156 static struct platform_driver clk_mt7629_hif_drv = {
157 .probe = clk_mt7629_hif_probe,
158 .driver = {
159 .name = "clk-mt7629-hif",
160 .of_match_table = of_match_clk_mt7629_hif,
161 },
162 };
163
164 builtin_platform_driver(clk_mt7629_hif_drv);
165
