1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * MPC85xx setup and early boot code plus other random bits.
4 *
5 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6 *
7 * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
8 */
9
10 #include <linux/stddef.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/errno.h>
14 #include <linux/reboot.h>
15 #include <linux/pci.h>
16 #include <linux/kdev_t.h>
17 #include <linux/major.h>
18 #include <linux/console.h>
19 #include <linux/delay.h>
20 #include <linux/seq_file.h>
21 #include <linux/initrd.h>
22 #include <linux/interrupt.h>
23 #include <linux/fsl_devices.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_platform.h>
27 #include <linux/pgtable.h>
28
29 #include <asm/page.h>
30 #include <linux/atomic.h>
31 #include <asm/time.h>
32 #include <asm/io.h>
33 #include <asm/machdep.h>
34 #include <asm/ipic.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/irq.h>
37 #include <mm/mmu_decl.h>
38 #include <asm/udbg.h>
39 #include <asm/mpic.h>
40 #include <asm/i8259.h>
41
42 #include <sysdev/fsl_soc.h>
43 #include <sysdev/fsl_pci.h>
44
45 #include "mpc85xx.h"
46
47 /*
48 * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
49 * various logic and performs system control functions.
50 * Here is the FPGA/CPLD register map.
51 */
52 struct cadmus_reg {
53 u8 cm_ver; /* Board version */
54 u8 cm_csr; /* General control/status */
55 u8 cm_rst; /* Reset control */
56 u8 cm_hsclk; /* High speed clock */
57 u8 cm_hsxclk; /* High speed clock extended */
58 u8 cm_led; /* LED data */
59 u8 cm_pci; /* PCI control/status */
60 u8 cm_dma; /* DMA control */
61 u8 res[248]; /* Total 256 bytes */
62 };
63
64 static struct cadmus_reg *cadmus;
65
66 #ifdef CONFIG_PCI
67
68 #define ARCADIA_HOST_BRIDGE_IDSEL 17
69 #define ARCADIA_2ND_BRIDGE_IDSEL 3
70
mpc85xx_exclude_device(struct pci_controller * hose,u_char bus,u_char devfn)71 static int mpc85xx_exclude_device(struct pci_controller *hose,
72 u_char bus, u_char devfn)
73 {
74 /* We explicitly do not go past the Tundra 320 Bridge */
75 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
76 return PCIBIOS_DEVICE_NOT_FOUND;
77 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
78 return PCIBIOS_DEVICE_NOT_FOUND;
79 else
80 return PCIBIOS_SUCCESSFUL;
81 }
82
mpc85xx_cds_restart(struct notifier_block * this,unsigned long mode,void * cmd)83 static int mpc85xx_cds_restart(struct notifier_block *this,
84 unsigned long mode, void *cmd)
85 {
86 struct pci_dev *dev;
87 u_char tmp;
88
89 if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
90 NULL))) {
91
92 /* Use the VIA Super Southbridge to force a PCI reset */
93 pci_read_config_byte(dev, 0x47, &tmp);
94 pci_write_config_byte(dev, 0x47, tmp | 1);
95
96 /* Flush the outbound PCI write queues */
97 pci_read_config_byte(dev, 0x47, &tmp);
98
99 /*
100 * At this point, the hardware reset should have triggered.
101 * However, if it doesn't work for some mysterious reason,
102 * just fall through to the default reset below.
103 */
104
105 pci_dev_put(dev);
106 }
107
108 /*
109 * If we can't find the VIA chip (maybe the P2P bridge is
110 * disabled) or the VIA chip reset didn't work, just return
111 * and let default reset sequence happen.
112 */
113 return NOTIFY_DONE;
114 }
115
mpc85xx_cds_restart_register(void)116 static int mpc85xx_cds_restart_register(void)
117 {
118 static struct notifier_block restart_handler;
119
120 restart_handler.notifier_call = mpc85xx_cds_restart;
121 restart_handler.priority = 192;
122
123 return register_restart_handler(&restart_handler);
124 }
125 machine_arch_initcall(mpc85xx_cds, mpc85xx_cds_restart_register);
126
127
mpc85xx_cds_pci_irq_fixup(struct pci_dev * dev)128 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
129 {
130 u_char c;
131 if (dev->vendor == PCI_VENDOR_ID_VIA) {
132 switch (dev->device) {
133 case PCI_DEVICE_ID_VIA_82C586_1:
134 /*
135 * U-Boot does not set the enable bits
136 * for the IDE device. Force them on here.
137 */
138 pci_read_config_byte(dev, 0x40, &c);
139 c |= 0x03; /* IDE: Chip Enable Bits */
140 pci_write_config_byte(dev, 0x40, c);
141
142 /*
143 * Since only primary interface works, force the
144 * IDE function to standard primary IDE interrupt
145 * w/ 8259 offset
146 */
147 dev->irq = 14;
148 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
149 break;
150 /*
151 * Force legacy USB interrupt routing
152 */
153 case PCI_DEVICE_ID_VIA_82C586_2:
154 /* There are two USB controllers.
155 * Identify them by function number
156 */
157 if (PCI_FUNC(dev->devfn) == 3)
158 dev->irq = 11;
159 else
160 dev->irq = 10;
161 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
162 break;
163 default:
164 break;
165 }
166 }
167 }
168
skip_fake_bridge(struct pci_dev * dev)169 static void skip_fake_bridge(struct pci_dev *dev)
170 {
171 /* Make it an error to skip the fake bridge
172 * in pci_setup_device() in probe.c */
173 dev->hdr_type = 0x7f;
174 }
175 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
176 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
177 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
178
179 #define PCI_DEVICE_ID_IDT_TSI310 0x01a7
180
181 /*
182 * Fix Tsi310 PCI-X bridge resource.
183 * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
184 * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
185 */
mpc85xx_cds_fixup_bus(struct pci_bus * bus)186 void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
187 {
188 struct pci_dev *dev = bus->self;
189 struct resource *res = bus->resource[0];
190
191 if (dev != NULL &&
192 dev->vendor == PCI_VENDOR_ID_IBM &&
193 dev->device == PCI_DEVICE_ID_IDT_TSI310) {
194 if (res) {
195 res->start = 0;
196 res->end = 0x1fff;
197 res->flags = IORESOURCE_IO;
198 pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
199 pr_info("mpc85xx_cds: %pR\n", res);
200 }
201 }
202
203 fsl_pcibios_fixup_bus(bus);
204 }
205
206 #ifdef CONFIG_PPC_I8259
mpc85xx_8259_cascade_handler(struct irq_desc * desc)207 static void mpc85xx_8259_cascade_handler(struct irq_desc *desc)
208 {
209 unsigned int cascade_irq = i8259_irq();
210
211 if (cascade_irq)
212 /* handle an interrupt from the 8259 */
213 generic_handle_irq(cascade_irq);
214
215 /* check for any interrupts from the shared IRQ line */
216 handle_fasteoi_irq(desc);
217 }
218
mpc85xx_8259_cascade_action(int irq,void * dev_id)219 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
220 {
221 return IRQ_HANDLED;
222 }
223 #endif /* PPC_I8259 */
224 #endif /* CONFIG_PCI */
225
mpc85xx_cds_pic_init(void)226 static void __init mpc85xx_cds_pic_init(void)
227 {
228 struct mpic *mpic;
229 mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
230 0, 256, " OpenPIC ");
231 BUG_ON(mpic == NULL);
232 mpic_init(mpic);
233 }
234
235 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
mpc85xx_cds_8259_attach(void)236 static int mpc85xx_cds_8259_attach(void)
237 {
238 int ret;
239 struct device_node *np = NULL;
240 struct device_node *cascade_node = NULL;
241 int cascade_irq;
242
243 /* Initialize the i8259 controller */
244 for_each_node_by_type(np, "interrupt-controller")
245 if (of_device_is_compatible(np, "chrp,iic")) {
246 cascade_node = np;
247 break;
248 }
249
250 if (cascade_node == NULL) {
251 printk(KERN_DEBUG "Could not find i8259 PIC\n");
252 return -ENODEV;
253 }
254
255 cascade_irq = irq_of_parse_and_map(cascade_node, 0);
256 if (!cascade_irq) {
257 printk(KERN_ERR "Failed to map cascade interrupt\n");
258 return -ENXIO;
259 }
260
261 i8259_init(cascade_node, 0);
262 of_node_put(cascade_node);
263
264 /*
265 * Hook the interrupt to make sure desc->action is never NULL.
266 * This is required to ensure that the interrupt does not get
267 * disabled when the last user of the shared IRQ line frees their
268 * interrupt.
269 */
270 ret = request_irq(cascade_irq, mpc85xx_8259_cascade_action,
271 IRQF_SHARED | IRQF_NO_THREAD, "8259 cascade",
272 cascade_node);
273 if (ret) {
274 printk(KERN_ERR "Failed to setup cascade interrupt\n");
275 return ret;
276 }
277
278 /* Success. Connect our low-level cascade handler. */
279 irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
280
281 return 0;
282 }
283 machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
284
285 #endif /* CONFIG_PPC_I8259 */
286
mpc85xx_cds_pci_assign_primary(void)287 static void __init mpc85xx_cds_pci_assign_primary(void)
288 {
289 #ifdef CONFIG_PCI
290 struct device_node *np;
291
292 if (fsl_pci_primary)
293 return;
294
295 /*
296 * MPC85xx_CDS has ISA bridge but unfortunately there is no
297 * isa node in device tree. We now looking for i8259 node as
298 * a workaround for such a broken device tree. This routine
299 * is for complying to all device trees.
300 */
301 np = of_find_node_by_name(NULL, "i8259");
302 while ((fsl_pci_primary = of_get_parent(np))) {
303 of_node_put(np);
304 np = fsl_pci_primary;
305
306 if ((of_device_is_compatible(np, "fsl,mpc8540-pci") ||
307 of_device_is_compatible(np, "fsl,mpc8548-pcie")) &&
308 of_device_is_available(np))
309 return;
310 }
311 #endif
312 }
313
314 /*
315 * Setup the architecture
316 */
mpc85xx_cds_setup_arch(void)317 static void __init mpc85xx_cds_setup_arch(void)
318 {
319 struct device_node *np;
320 int cds_pci_slot;
321
322 if (ppc_md.progress)
323 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
324
325 np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
326 if (!np) {
327 pr_err("Could not find FPGA node.\n");
328 return;
329 }
330
331 cadmus = of_iomap(np, 0);
332 of_node_put(np);
333 if (!cadmus) {
334 pr_err("Fail to map FPGA area.\n");
335 return;
336 }
337
338 if (ppc_md.progress) {
339 char buf[40];
340 cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
341 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
342 in_8(&cadmus->cm_ver), cds_pci_slot);
343 ppc_md.progress(buf, 0);
344 }
345
346 #ifdef CONFIG_PCI
347 ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
348 ppc_md.pci_exclude_device = mpc85xx_exclude_device;
349 #endif
350
351 mpc85xx_cds_pci_assign_primary();
352 fsl_pci_assign_primary();
353 }
354
mpc85xx_cds_show_cpuinfo(struct seq_file * m)355 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
356 {
357 uint pvid, svid, phid1;
358
359 pvid = mfspr(SPRN_PVR);
360 svid = mfspr(SPRN_SVR);
361
362 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
363 seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
364 in_8(&cadmus->cm_ver));
365 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
366 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
367
368 /* Display cpu Pll setting */
369 phid1 = mfspr(SPRN_HID1);
370 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
371 }
372
373
374 /*
375 * Called very early, device-tree isn't unflattened
376 */
mpc85xx_cds_probe(void)377 static int __init mpc85xx_cds_probe(void)
378 {
379 return of_machine_is_compatible("MPC85xxCDS");
380 }
381
382 machine_arch_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
383
define_machine(mpc85xx_cds)384 define_machine(mpc85xx_cds) {
385 .name = "MPC85xx CDS",
386 .probe = mpc85xx_cds_probe,
387 .setup_arch = mpc85xx_cds_setup_arch,
388 .init_IRQ = mpc85xx_cds_pic_init,
389 .show_cpuinfo = mpc85xx_cds_show_cpuinfo,
390 .get_irq = mpic_get_irq,
391 #ifdef CONFIG_PCI
392 .pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
393 .pcibios_fixup_phb = fsl_pcibios_fixup_phb,
394 #endif
395 .calibrate_decr = generic_calibrate_decr,
396 .progress = udbg_progress,
397 };
398
