1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 *
7 * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
8 * Copyright 1999 SuSE GmbH (Philipp Rumpf, prumpf@tux.org)
9 * Copyright 1999 Hewlett Packard Co.
10 *
11 */
12
13 #include <linux/mm.h>
14 #include <linux/ptrace.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/interrupt.h>
18 #include <linux/extable.h>
19 #include <linux/uaccess.h>
20 #include <linux/hugetlb.h>
21 #include <linux/perf_event.h>
22
23 #include <asm/traps.h>
24
25 #define DEBUG_NATLB 0
26
27 /* Various important other fields */
28 #define bit22set(x) (x & 0x00000200)
29 #define bits23_25set(x) (x & 0x000001c0)
30 #define isGraphicsFlushRead(x) ((x & 0xfc003fdf) == 0x04001a80)
31 /* extended opcode is 0x6a */
32
33 #define BITSSET 0x1c0 /* for identifying LDCW */
34
35
36 int show_unhandled_signals = 1;
37
38 /*
39 * parisc_acctyp(unsigned int inst) --
40 * Given a PA-RISC memory access instruction, determine if the
41 * instruction would perform a memory read or memory write
42 * operation.
43 *
44 * This function assumes that the given instruction is a memory access
45 * instruction (i.e. you should really only call it if you know that
46 * the instruction has generated some sort of a memory access fault).
47 *
48 * Returns:
49 * VM_READ if read operation
50 * VM_WRITE if write operation
51 * VM_EXEC if execute operation
52 */
53 unsigned long
parisc_acctyp(unsigned long code,unsigned int inst)54 parisc_acctyp(unsigned long code, unsigned int inst)
55 {
56 if (code == 6 || code == 16)
57 return VM_EXEC;
58
59 switch (inst & 0xf0000000) {
60 case 0x40000000: /* load */
61 case 0x50000000: /* new load */
62 return VM_READ;
63
64 case 0x60000000: /* store */
65 case 0x70000000: /* new store */
66 return VM_WRITE;
67
68 case 0x20000000: /* coproc */
69 case 0x30000000: /* coproc2 */
70 if (bit22set(inst))
71 return VM_WRITE;
72 fallthrough;
73
74 case 0x0: /* indexed/memory management */
75 if (bit22set(inst)) {
76 /*
77 * Check for the 'Graphics Flush Read' instruction.
78 * It resembles an FDC instruction, except for bits
79 * 20 and 21. Any combination other than zero will
80 * utilize the block mover functionality on some
81 * older PA-RISC platforms. The case where a block
82 * move is performed from VM to graphics IO space
83 * should be treated as a READ.
84 *
85 * The significance of bits 20,21 in the FDC
86 * instruction is:
87 *
88 * 00 Flush data cache (normal instruction behavior)
89 * 01 Graphics flush write (IO space -> VM)
90 * 10 Graphics flush read (VM -> IO space)
91 * 11 Graphics flush read/write (VM <-> IO space)
92 */
93 if (isGraphicsFlushRead(inst))
94 return VM_READ;
95 return VM_WRITE;
96 } else {
97 /*
98 * Check for LDCWX and LDCWS (semaphore instructions).
99 * If bits 23 through 25 are all 1's it is one of
100 * the above two instructions and is a write.
101 *
102 * Note: With the limited bits we are looking at,
103 * this will also catch PROBEW and PROBEWI. However,
104 * these should never get in here because they don't
105 * generate exceptions of the type:
106 * Data TLB miss fault/data page fault
107 * Data memory protection trap
108 */
109 if (bits23_25set(inst) == BITSSET)
110 return VM_WRITE;
111 }
112 return VM_READ; /* Default */
113 }
114 return VM_READ; /* Default */
115 }
116
117 #undef bit22set
118 #undef bits23_25set
119 #undef isGraphicsFlushRead
120 #undef BITSSET
121
122
123 #if 0
124 /* This is the treewalk to find a vma which is the highest that has
125 * a start < addr. We're using find_vma_prev instead right now, but
126 * we might want to use this at some point in the future. Probably
127 * not, but I want it committed to CVS so I don't lose it :-)
128 */
129 while (tree != vm_avl_empty) {
130 if (tree->vm_start > addr) {
131 tree = tree->vm_avl_left;
132 } else {
133 prev = tree;
134 if (prev->vm_next == NULL)
135 break;
136 if (prev->vm_next->vm_start > addr)
137 break;
138 tree = tree->vm_avl_right;
139 }
140 }
141 #endif
142
fixup_exception(struct pt_regs * regs)143 int fixup_exception(struct pt_regs *regs)
144 {
145 const struct exception_table_entry *fix;
146
147 fix = search_exception_tables(regs->iaoq[0]);
148 if (fix) {
149 /*
150 * Fix up get_user() and put_user().
151 * ASM_EXCEPTIONTABLE_ENTRY_EFAULT() sets the least-significant
152 * bit in the relative address of the fixup routine to indicate
153 * that gr[ASM_EXCEPTIONTABLE_REG] should be loaded with
154 * -EFAULT to report a userspace access error.
155 */
156 if (fix->fixup & 1) {
157 regs->gr[ASM_EXCEPTIONTABLE_REG] = -EFAULT;
158
159 /* zero target register for get_user() */
160 if (parisc_acctyp(0, regs->iir) == VM_READ) {
161 int treg = regs->iir & 0x1f;
162 BUG_ON(treg == 0);
163 regs->gr[treg] = 0;
164 }
165 }
166
167 regs->iaoq[0] = (unsigned long)&fix->fixup + fix->fixup;
168 regs->iaoq[0] &= ~3;
169 /*
170 * NOTE: In some cases the faulting instruction
171 * may be in the delay slot of a branch. We
172 * don't want to take the branch, so we don't
173 * increment iaoq[1], instead we set it to be
174 * iaoq[0]+4, and clear the B bit in the PSW
175 */
176 regs->iaoq[1] = regs->iaoq[0] + 4;
177 regs->gr[0] &= ~PSW_B; /* IPSW in gr[0] */
178
179 return 1;
180 }
181
182 return 0;
183 }
184
185 /*
186 * parisc hardware trap list
187 *
188 * Documented in section 3 "Addressing and Access Control" of the
189 * "PA-RISC 1.1 Architecture and Instruction Set Reference Manual"
190 * https://parisc.wiki.kernel.org/index.php/File:Pa11_acd.pdf
191 *
192 * For implementation see handle_interruption() in traps.c
193 */
194 static const char * const trap_description[] = {
195 [1] "High-priority machine check (HPMC)",
196 [2] "Power failure interrupt",
197 [3] "Recovery counter trap",
198 [5] "Low-priority machine check",
199 [6] "Instruction TLB miss fault",
200 [7] "Instruction access rights / protection trap",
201 [8] "Illegal instruction trap",
202 [9] "Break instruction trap",
203 [10] "Privileged operation trap",
204 [11] "Privileged register trap",
205 [12] "Overflow trap",
206 [13] "Conditional trap",
207 [14] "FP Assist Exception trap",
208 [15] "Data TLB miss fault",
209 [16] "Non-access ITLB miss fault",
210 [17] "Non-access DTLB miss fault",
211 [18] "Data memory protection/unaligned access trap",
212 [19] "Data memory break trap",
213 [20] "TLB dirty bit trap",
214 [21] "Page reference trap",
215 [22] "Assist emulation trap",
216 [25] "Taken branch trap",
217 [26] "Data memory access rights trap",
218 [27] "Data memory protection ID trap",
219 [28] "Unaligned data reference trap",
220 };
221
trap_name(unsigned long code)222 const char *trap_name(unsigned long code)
223 {
224 const char *t = NULL;
225
226 if (code < ARRAY_SIZE(trap_description))
227 t = trap_description[code];
228
229 return t ? t : "Unknown trap";
230 }
231
232 /*
233 * Print out info about fatal segfaults, if the show_unhandled_signals
234 * sysctl is set:
235 */
236 static inline void
show_signal_msg(struct pt_regs * regs,unsigned long code,unsigned long address,struct task_struct * tsk,struct vm_area_struct * vma)237 show_signal_msg(struct pt_regs *regs, unsigned long code,
238 unsigned long address, struct task_struct *tsk,
239 struct vm_area_struct *vma)
240 {
241 if (!unhandled_signal(tsk, SIGSEGV))
242 return;
243
244 if (!printk_ratelimit())
245 return;
246
247 pr_warn("\n");
248 pr_warn("do_page_fault() command='%s' type=%lu address=0x%08lx",
249 tsk->comm, code, address);
250 print_vma_addr(KERN_CONT " in ", regs->iaoq[0]);
251
252 pr_cont("\ntrap #%lu: %s%c", code, trap_name(code),
253 vma ? ',':'\n');
254
255 if (vma)
256 pr_cont(" vm_start = 0x%08lx, vm_end = 0x%08lx\n",
257 vma->vm_start, vma->vm_end);
258
259 show_regs(regs);
260 }
261
do_page_fault(struct pt_regs * regs,unsigned long code,unsigned long address)262 void do_page_fault(struct pt_regs *regs, unsigned long code,
263 unsigned long address)
264 {
265 struct vm_area_struct *vma, *prev_vma;
266 struct task_struct *tsk;
267 struct mm_struct *mm;
268 unsigned long acc_type;
269 vm_fault_t fault = 0;
270 unsigned int flags;
271 char *msg;
272
273 tsk = current;
274 mm = tsk->mm;
275 if (!mm) {
276 msg = "Page fault: no context";
277 goto no_context;
278 }
279
280 flags = FAULT_FLAG_DEFAULT;
281 if (user_mode(regs))
282 flags |= FAULT_FLAG_USER;
283
284 acc_type = parisc_acctyp(code, regs->iir);
285 if (acc_type & VM_WRITE)
286 flags |= FAULT_FLAG_WRITE;
287 perf_sw_event(PERF_COUNT_SW_PAGE_FAULTS, 1, regs, address);
288 retry:
289 mmap_read_lock(mm);
290 vma = find_vma_prev(mm, address, &prev_vma);
291 if (!vma || address < vma->vm_start)
292 goto check_expansion;
293 /*
294 * Ok, we have a good vm_area for this memory access. We still need to
295 * check the access permissions.
296 */
297
298 good_area:
299
300 if ((vma->vm_flags & acc_type) != acc_type)
301 goto bad_area;
302
303 /*
304 * If for any reason at all we couldn't handle the fault, make
305 * sure we exit gracefully rather than endlessly redo the
306 * fault.
307 */
308
309 fault = handle_mm_fault(vma, address, flags, regs);
310
311 if (fault_signal_pending(fault, regs))
312 return;
313
314 /* The fault is fully completed (including releasing mmap lock) */
315 if (fault & VM_FAULT_COMPLETED)
316 return;
317
318 if (unlikely(fault & VM_FAULT_ERROR)) {
319 /*
320 * We hit a shared mapping outside of the file, or some
321 * other thing happened to us that made us unable to
322 * handle the page fault gracefully.
323 */
324 if (fault & VM_FAULT_OOM)
325 goto out_of_memory;
326 else if (fault & VM_FAULT_SIGSEGV)
327 goto bad_area;
328 else if (fault & (VM_FAULT_SIGBUS|VM_FAULT_HWPOISON|
329 VM_FAULT_HWPOISON_LARGE))
330 goto bad_area;
331 BUG();
332 }
333 if (fault & VM_FAULT_RETRY) {
334 /*
335 * No need to mmap_read_unlock(mm) as we would
336 * have already released it in __lock_page_or_retry
337 * in mm/filemap.c.
338 */
339 flags |= FAULT_FLAG_TRIED;
340 goto retry;
341 }
342 mmap_read_unlock(mm);
343 return;
344
345 check_expansion:
346 vma = prev_vma;
347 if (vma && (expand_stack(vma, address) == 0))
348 goto good_area;
349
350 /*
351 * Something tried to access memory that isn't in our memory map..
352 */
353 bad_area:
354 mmap_read_unlock(mm);
355
356 if (user_mode(regs)) {
357 int signo, si_code;
358
359 switch (code) {
360 case 15: /* Data TLB miss fault/Data page fault */
361 /* send SIGSEGV when outside of vma */
362 if (!vma ||
363 address < vma->vm_start || address >= vma->vm_end) {
364 signo = SIGSEGV;
365 si_code = SEGV_MAPERR;
366 break;
367 }
368
369 /* send SIGSEGV for wrong permissions */
370 if ((vma->vm_flags & acc_type) != acc_type) {
371 signo = SIGSEGV;
372 si_code = SEGV_ACCERR;
373 break;
374 }
375
376 /* probably address is outside of mapped file */
377 fallthrough;
378 case 17: /* NA data TLB miss / page fault */
379 case 18: /* Unaligned access - PCXS only */
380 signo = SIGBUS;
381 si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
382 break;
383 case 16: /* Non-access instruction TLB miss fault */
384 case 26: /* PCXL: Data memory access rights trap */
385 default:
386 signo = SIGSEGV;
387 si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
388 break;
389 }
390 #ifdef CONFIG_MEMORY_FAILURE
391 if (fault & (VM_FAULT_HWPOISON|VM_FAULT_HWPOISON_LARGE)) {
392 unsigned int lsb = 0;
393 printk(KERN_ERR
394 "MCE: Killing %s:%d due to hardware memory corruption fault at %08lx\n",
395 tsk->comm, tsk->pid, address);
396 /*
397 * Either small page or large page may be poisoned.
398 * In other words, VM_FAULT_HWPOISON_LARGE and
399 * VM_FAULT_HWPOISON are mutually exclusive.
400 */
401 if (fault & VM_FAULT_HWPOISON_LARGE)
402 lsb = hstate_index_to_shift(VM_FAULT_GET_HINDEX(fault));
403 else if (fault & VM_FAULT_HWPOISON)
404 lsb = PAGE_SHIFT;
405
406 force_sig_mceerr(BUS_MCEERR_AR, (void __user *) address,
407 lsb);
408 return;
409 }
410 #endif
411 show_signal_msg(regs, code, address, tsk, vma);
412
413 force_sig_fault(signo, si_code, (void __user *) address);
414 return;
415 }
416 msg = "Page fault: bad address";
417
418 no_context:
419
420 if (!user_mode(regs) && fixup_exception(regs)) {
421 return;
422 }
423
424 parisc_terminate(msg, regs, code, address);
425
426 out_of_memory:
427 mmap_read_unlock(mm);
428 if (!user_mode(regs)) {
429 msg = "Page fault: out of memory";
430 goto no_context;
431 }
432 pagefault_out_of_memory();
433 }
434
435 /* Handle non-access data TLB miss faults.
436 *
437 * For probe instructions, accesses to userspace are considered allowed
438 * if they lie in a valid VMA and the access type matches. We are not
439 * allowed to handle MM faults here so there may be situations where an
440 * actual access would fail even though a probe was successful.
441 */
442 int
handle_nadtlb_fault(struct pt_regs * regs)443 handle_nadtlb_fault(struct pt_regs *regs)
444 {
445 unsigned long insn = regs->iir;
446 int breg, treg, xreg, val = 0;
447 struct vm_area_struct *vma, *prev_vma;
448 struct task_struct *tsk;
449 struct mm_struct *mm;
450 unsigned long address;
451 unsigned long acc_type;
452
453 switch (insn & 0x380) {
454 case 0x280:
455 /* FDC instruction */
456 fallthrough;
457 case 0x380:
458 /* PDC and FIC instructions */
459 if (DEBUG_NATLB && printk_ratelimit()) {
460 pr_warn("WARNING: nullifying cache flush/purge instruction\n");
461 show_regs(regs);
462 }
463 if (insn & 0x20) {
464 /* Base modification */
465 breg = (insn >> 21) & 0x1f;
466 xreg = (insn >> 16) & 0x1f;
467 if (breg && xreg)
468 regs->gr[breg] += regs->gr[xreg];
469 }
470 regs->gr[0] |= PSW_N;
471 return 1;
472
473 case 0x180:
474 /* PROBE instruction */
475 treg = insn & 0x1f;
476 if (regs->isr) {
477 tsk = current;
478 mm = tsk->mm;
479 if (mm) {
480 /* Search for VMA */
481 address = regs->ior;
482 mmap_read_lock(mm);
483 vma = find_vma_prev(mm, address, &prev_vma);
484 mmap_read_unlock(mm);
485
486 /*
487 * Check if access to the VMA is okay.
488 * We don't allow for stack expansion.
489 */
490 acc_type = (insn & 0x40) ? VM_WRITE : VM_READ;
491 if (vma
492 && address >= vma->vm_start
493 && (vma->vm_flags & acc_type) == acc_type)
494 val = 1;
495 }
496 }
497 if (treg)
498 regs->gr[treg] = val;
499 regs->gr[0] |= PSW_N;
500 return 1;
501
502 case 0x300:
503 /* LPA instruction */
504 if (insn & 0x20) {
505 /* Base modification */
506 breg = (insn >> 21) & 0x1f;
507 xreg = (insn >> 16) & 0x1f;
508 if (breg && xreg)
509 regs->gr[breg] += regs->gr[xreg];
510 }
511 treg = insn & 0x1f;
512 if (treg)
513 regs->gr[treg] = 0;
514 regs->gr[0] |= PSW_N;
515 return 1;
516
517 default:
518 break;
519 }
520
521 return 0;
522 }
523
