1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * linux/arch/parisc/kernel/time.c
4 *
5 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
6 * Modifications for ARM (C) 1994, 1995, 1996,1997 Russell King
7 * Copyright (C) 1999 SuSE GmbH, (Philipp Rumpf, prumpf@tux.org)
8 *
9 * 1994-07-02 Alan Modra
10 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
11 * 1998-12-20 Updated NTP code according to technical memorandum Jan '96
12 * "A Kernel Model for Precision Timekeeping" by Dave Mills
13 */
14 #include <linux/errno.h>
15 #include <linux/module.h>
16 #include <linux/rtc.h>
17 #include <linux/sched.h>
18 #include <linux/sched/clock.h>
19 #include <linux/sched_clock.h>
20 #include <linux/kernel.h>
21 #include <linux/param.h>
22 #include <linux/string.h>
23 #include <linux/mm.h>
24 #include <linux/interrupt.h>
25 #include <linux/time.h>
26 #include <linux/init.h>
27 #include <linux/smp.h>
28 #include <linux/profile.h>
29 #include <linux/clocksource.h>
30 #include <linux/platform_device.h>
31 #include <linux/ftrace.h>
32
33 #include <linux/uaccess.h>
34 #include <asm/io.h>
35 #include <asm/irq.h>
36 #include <asm/page.h>
37 #include <asm/param.h>
38 #include <asm/pdc.h>
39 #include <asm/led.h>
40
41 #include <linux/timex.h>
42
43 int time_keeper_id __read_mostly; /* CPU used for timekeeping. */
44
45 static unsigned long clocktick __ro_after_init; /* timer cycles per tick */
46
47 /*
48 * We keep time on PA-RISC Linux by using the Interval Timer which is
49 * a pair of registers; one is read-only and one is write-only; both
50 * accessed through CR16. The read-only register is 32 or 64 bits wide,
51 * and increments by 1 every CPU clock tick. The architecture only
52 * guarantees us a rate between 0.5 and 2, but all implementations use a
53 * rate of 1. The write-only register is 32-bits wide. When the lowest
54 * 32 bits of the read-only register compare equal to the write-only
55 * register, it raises a maskable external interrupt. Each processor has
56 * an Interval Timer of its own and they are not synchronised.
57 *
58 * We want to generate an interrupt every 1/HZ seconds. So we program
59 * CR16 to interrupt every @clocktick cycles. The it_value in cpu_data
60 * is programmed with the intended time of the next tick. We can be
61 * held off for an arbitrarily long period of time by interrupts being
62 * disabled, so we may miss one or more ticks.
63 */
timer_interrupt(int irq,void * dev_id)64 irqreturn_t __irq_entry timer_interrupt(int irq, void *dev_id)
65 {
66 unsigned long now;
67 unsigned long next_tick;
68 unsigned long ticks_elapsed = 0;
69 unsigned int cpu = smp_processor_id();
70 struct cpuinfo_parisc *cpuinfo = &per_cpu(cpu_data, cpu);
71
72 /* gcc can optimize for "read-only" case with a local clocktick */
73 unsigned long cpt = clocktick;
74
75 /* Initialize next_tick to the old expected tick time. */
76 next_tick = cpuinfo->it_value;
77
78 /* Calculate how many ticks have elapsed. */
79 now = mfctl(16);
80 do {
81 ++ticks_elapsed;
82 next_tick += cpt;
83 } while (next_tick - now > cpt);
84
85 /* Store (in CR16 cycles) up to when we are accounting right now. */
86 cpuinfo->it_value = next_tick;
87
88 /* Go do system house keeping. */
89 if (IS_ENABLED(CONFIG_SMP) && (cpu != time_keeper_id))
90 ticks_elapsed = 0;
91 legacy_timer_tick(ticks_elapsed);
92
93 /* Skip clockticks on purpose if we know we would miss those.
94 * The new CR16 must be "later" than current CR16 otherwise
95 * itimer would not fire until CR16 wrapped - e.g 4 seconds
96 * later on a 1Ghz processor. We'll account for the missed
97 * ticks on the next timer interrupt.
98 * We want IT to fire modulo clocktick even if we miss/skip some.
99 * But those interrupts don't in fact get delivered that regularly.
100 *
101 * "next_tick - now" will always give the difference regardless
102 * if one or the other wrapped. If "now" is "bigger" we'll end up
103 * with a very large unsigned number.
104 */
105 now = mfctl(16);
106 while (next_tick - now > cpt)
107 next_tick += cpt;
108
109 /* Program the IT when to deliver the next interrupt.
110 * Only bottom 32-bits of next_tick are writable in CR16!
111 * Timer interrupt will be delivered at least a few hundred cycles
112 * after the IT fires, so if we are too close (<= 8000 cycles) to the
113 * next cycle, simply skip it.
114 */
115 if (next_tick - now <= 8000)
116 next_tick += cpt;
117 mtctl(next_tick, 16);
118
119 return IRQ_HANDLED;
120 }
121
122
profile_pc(struct pt_regs * regs)123 unsigned long profile_pc(struct pt_regs *regs)
124 {
125 unsigned long pc = instruction_pointer(regs);
126
127 if (regs->gr[0] & PSW_N)
128 pc -= 4;
129
130 #ifdef CONFIG_SMP
131 if (in_lock_functions(pc))
132 pc = regs->gr[2];
133 #endif
134
135 return pc;
136 }
137 EXPORT_SYMBOL(profile_pc);
138
139
140 /* clock source code */
141
read_cr16(struct clocksource * cs)142 static u64 notrace read_cr16(struct clocksource *cs)
143 {
144 return get_cycles();
145 }
146
147 static struct clocksource clocksource_cr16 = {
148 .name = "cr16",
149 .rating = 300,
150 .read = read_cr16,
151 .mask = CLOCKSOURCE_MASK(BITS_PER_LONG),
152 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
153 };
154
start_cpu_itimer(void)155 void start_cpu_itimer(void)
156 {
157 unsigned int cpu = smp_processor_id();
158 unsigned long next_tick = mfctl(16) + clocktick;
159
160 mtctl(next_tick, 16); /* kick off Interval Timer (CR16) */
161
162 per_cpu(cpu_data, cpu).it_value = next_tick;
163 }
164
165 #if IS_ENABLED(CONFIG_RTC_DRV_GENERIC)
rtc_generic_get_time(struct device * dev,struct rtc_time * tm)166 static int rtc_generic_get_time(struct device *dev, struct rtc_time *tm)
167 {
168 struct pdc_tod tod_data;
169
170 memset(tm, 0, sizeof(*tm));
171 if (pdc_tod_read(&tod_data) < 0)
172 return -EOPNOTSUPP;
173
174 /* we treat tod_sec as unsigned, so this can work until year 2106 */
175 rtc_time64_to_tm(tod_data.tod_sec, tm);
176 return 0;
177 }
178
rtc_generic_set_time(struct device * dev,struct rtc_time * tm)179 static int rtc_generic_set_time(struct device *dev, struct rtc_time *tm)
180 {
181 time64_t secs = rtc_tm_to_time64(tm);
182 int ret;
183
184 /* hppa has Y2K38 problem: pdc_tod_set() takes an u32 value! */
185 ret = pdc_tod_set(secs, 0);
186 if (ret != 0) {
187 pr_warn("pdc_tod_set(%lld) returned error %d\n", secs, ret);
188 if (ret == PDC_INVALID_ARG)
189 return -EINVAL;
190 return -EOPNOTSUPP;
191 }
192
193 return 0;
194 }
195
196 static const struct rtc_class_ops rtc_generic_ops = {
197 .read_time = rtc_generic_get_time,
198 .set_time = rtc_generic_set_time,
199 };
200
rtc_init(void)201 static int __init rtc_init(void)
202 {
203 struct platform_device *pdev;
204
205 pdev = platform_device_register_data(NULL, "rtc-generic", -1,
206 &rtc_generic_ops,
207 sizeof(rtc_generic_ops));
208
209 return PTR_ERR_OR_ZERO(pdev);
210 }
211 device_initcall(rtc_init);
212 #endif
213
read_persistent_clock64(struct timespec64 * ts)214 void read_persistent_clock64(struct timespec64 *ts)
215 {
216 static struct pdc_tod tod_data;
217 if (pdc_tod_read(&tod_data) == 0) {
218 ts->tv_sec = tod_data.tod_sec;
219 ts->tv_nsec = tod_data.tod_usec * 1000;
220 } else {
221 printk(KERN_ERR "Error reading tod clock\n");
222 ts->tv_sec = 0;
223 ts->tv_nsec = 0;
224 }
225 }
226
227
read_cr16_sched_clock(void)228 static u64 notrace read_cr16_sched_clock(void)
229 {
230 return get_cycles();
231 }
232
233
234 /*
235 * timer interrupt and sched_clock() initialization
236 */
237
time_init(void)238 void __init time_init(void)
239 {
240 unsigned long cr16_hz;
241
242 clocktick = (100 * PAGE0->mem_10msec) / HZ;
243 start_cpu_itimer(); /* get CPU 0 started */
244
245 cr16_hz = 100 * PAGE0->mem_10msec; /* Hz */
246
247 /* register as sched_clock source */
248 sched_clock_register(read_cr16_sched_clock, BITS_PER_LONG, cr16_hz);
249 }
250
init_cr16_clocksource(void)251 static int __init init_cr16_clocksource(void)
252 {
253 /*
254 * The cr16 interval timers are not synchronized across CPUs.
255 */
256 if (num_online_cpus() > 1 && !running_on_qemu) {
257 clocksource_cr16.name = "cr16_unstable";
258 clocksource_cr16.flags = CLOCK_SOURCE_UNSTABLE;
259 clocksource_cr16.rating = 0;
260 }
261
262 /* register at clocksource framework */
263 clocksource_register_hz(&clocksource_cr16,
264 100 * PAGE0->mem_10msec);
265
266 return 0;
267 }
268
269 device_initcall(init_cr16_clocksource);
270
