1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Base Device Tree Source for the Renesas RZ/N1D (R9A06G032) 4 * 5 * Copyright (C) 2018 Renesas Electronics Europe Limited 6 * 7 */ 8 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/r9a06g032-sysctrl.h> 11 12/ { 13 compatible = "renesas,r9a06g032"; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 cpus { 18 #address-cells = <1>; 19 #size-cells = <0>; 20 21 cpu@0 { 22 device_type = "cpu"; 23 compatible = "arm,cortex-a7"; 24 reg = <0>; 25 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 26 }; 27 28 cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <1>; 32 clocks = <&sysctrl R9A06G032_CLK_A7MP>; 33 enable-method = "renesas,r9a06g032-smp"; 34 cpu-release-addr = <0 0x4000c204>; 35 }; 36 }; 37 38 ext_jtag_clk: extjtagclk { 39 #clock-cells = <0>; 40 compatible = "fixed-clock"; 41 clock-frequency = <0>; 42 }; 43 44 ext_mclk: extmclk { 45 #clock-cells = <0>; 46 compatible = "fixed-clock"; 47 clock-frequency = <40000000>; 48 }; 49 50 ext_rgmii_ref: extrgmiiref { 51 #clock-cells = <0>; 52 compatible = "fixed-clock"; 53 clock-frequency = <0>; 54 }; 55 56 ext_rtc_clk: extrtcclk { 57 #clock-cells = <0>; 58 compatible = "fixed-clock"; 59 clock-frequency = <0>; 60 }; 61 62 soc { 63 compatible = "simple-bus"; 64 #address-cells = <1>; 65 #size-cells = <1>; 66 interrupt-parent = <&gic>; 67 ranges; 68 69 rtc0: rtc@40006000 { 70 compatible = "renesas,r9a06g032-rtc", "renesas,rzn1-rtc"; 71 reg = <0x40006000 0x1000>; 72 interrupts = <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 73 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 74 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 75 interrupt-names = "alarm", "timer", "pps"; 76 clocks = <&sysctrl R9A06G032_HCLK_RTC>; 77 clock-names = "hclk"; 78 power-domains = <&sysctrl>; 79 status = "disabled"; 80 }; 81 82 wdt0: watchdog@40008000 { 83 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 84 reg = <0x40008000 0x1000>; 85 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 86 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 87 status = "disabled"; 88 }; 89 90 wdt1: watchdog@40009000 { 91 compatible = "renesas,r9a06g032-wdt", "renesas,rzn1-wdt"; 92 reg = <0x40009000 0x1000>; 93 interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>; 94 clocks = <&sysctrl R9A06G032_CLK_WATCHDOG>; 95 status = "disabled"; 96 }; 97 98 sysctrl: system-controller@4000c000 { 99 compatible = "renesas,r9a06g032-sysctrl"; 100 reg = <0x4000c000 0x1000>; 101 status = "okay"; 102 #clock-cells = <1>; 103 #power-domain-cells = <0>; 104 105 clocks = <&ext_mclk>, <&ext_rtc_clk>, 106 <&ext_jtag_clk>, <&ext_rgmii_ref>; 107 clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext"; 108 #address-cells = <1>; 109 #size-cells = <1>; 110 111 dmamux: dma-router@a0 { 112 compatible = "renesas,rzn1-dmamux"; 113 reg = <0xa0 4>; 114 #dma-cells = <6>; 115 dma-requests = <32>; 116 dma-masters = <&dma0 &dma1>; 117 }; 118 }; 119 120 pci_usb: pci@40030000 { 121 compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; 122 device_type = "pci"; 123 clocks = <&sysctrl R9A06G032_HCLK_USBH>, 124 <&sysctrl R9A06G032_HCLK_USBPM>, 125 <&sysctrl R9A06G032_CLK_PCI_USB>; 126 clock-names = "hclkh", "hclkpm", "pciclk"; 127 power-domains = <&sysctrl>; 128 reg = <0x40030000 0xc00>, 129 <0x40020000 0x1100>; 130 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 131 status = "disabled"; 132 133 bus-range = <0 0>; 134 #address-cells = <3>; 135 #size-cells = <2>; 136 #interrupt-cells = <1>; 137 ranges = <0x02000000 0 0x40020000 0x40020000 0 0x00010000>; 138 /* Should map all possible DDR as inbound ranges, but 139 * the IP only supports a 256MB, 512MB, or 1GB window. 140 * flags, PCI addr (64-bit), CPU addr, PCI size (64-bit) 141 */ 142 dma-ranges = <0x42000000 0 0x80000000 0x80000000 0 0x40000000>; 143 interrupt-map-mask = <0xf800 0 0 0x7>; 144 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 145 0x0800 0 0 1 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH 146 0x1000 0 0 2 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 147 148 usb@1,0 { 149 reg = <0x800 0 0 0 0>; 150 phys = <&usbphy>; 151 phy-names = "usb"; 152 }; 153 154 usb@2,0 { 155 reg = <0x1000 0 0 0 0>; 156 phys = <&usbphy>; 157 phy-names = "usb"; 158 }; 159 }; 160 161 uart0: serial@40060000 { 162 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 163 reg = <0x40060000 0x400>; 164 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 165 reg-shift = <2>; 166 reg-io-width = <4>; 167 clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>; 168 clock-names = "baudclk", "apb_pclk"; 169 status = "disabled"; 170 }; 171 172 uart1: serial@40061000 { 173 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 174 reg = <0x40061000 0x400>; 175 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 176 reg-shift = <2>; 177 reg-io-width = <4>; 178 clocks = <&sysctrl R9A06G032_CLK_UART1>, <&sysctrl R9A06G032_HCLK_UART1>; 179 clock-names = "baudclk", "apb_pclk"; 180 status = "disabled"; 181 }; 182 183 uart2: serial@40062000 { 184 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart", "snps,dw-apb-uart"; 185 reg = <0x40062000 0x400>; 186 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 187 reg-shift = <2>; 188 reg-io-width = <4>; 189 clocks = <&sysctrl R9A06G032_CLK_UART2>, <&sysctrl R9A06G032_HCLK_UART2>; 190 clock-names = "baudclk", "apb_pclk"; 191 status = "disabled"; 192 }; 193 194 uart3: serial@50000000 { 195 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 196 reg = <0x50000000 0x400>; 197 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 198 reg-shift = <2>; 199 reg-io-width = <4>; 200 clocks = <&sysctrl R9A06G032_CLK_UART3>, <&sysctrl R9A06G032_HCLK_UART3>; 201 clock-names = "baudclk", "apb_pclk"; 202 dmas = <&dmamux 0 0 0 0 0 1>, <&dmamux 1 0 0 0 1 1>; 203 dma-names = "rx", "tx"; 204 status = "disabled"; 205 }; 206 207 uart4: serial@50001000 { 208 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 209 reg = <0x50001000 0x400>; 210 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 211 reg-shift = <2>; 212 reg-io-width = <4>; 213 clocks = <&sysctrl R9A06G032_CLK_UART4>, <&sysctrl R9A06G032_HCLK_UART4>; 214 clock-names = "baudclk", "apb_pclk"; 215 dmas = <&dmamux 2 0 0 0 2 1>, <&dmamux 3 0 0 0 3 1>; 216 dma-names = "rx", "tx"; 217 status = "disabled"; 218 }; 219 220 uart5: serial@50002000 { 221 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 222 reg = <0x50002000 0x400>; 223 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 224 reg-shift = <2>; 225 reg-io-width = <4>; 226 clocks = <&sysctrl R9A06G032_CLK_UART5>, <&sysctrl R9A06G032_HCLK_UART5>; 227 clock-names = "baudclk", "apb_pclk"; 228 dmas = <&dmamux 4 0 0 0 4 1>, <&dmamux 5 0 0 0 5 1>; 229 dma-names = "rx", "tx"; 230 status = "disabled"; 231 }; 232 233 uart6: serial@50003000 { 234 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 235 reg = <0x50003000 0x400>; 236 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 237 reg-shift = <2>; 238 reg-io-width = <4>; 239 clocks = <&sysctrl R9A06G032_CLK_UART6>, <&sysctrl R9A06G032_HCLK_UART6>; 240 clock-names = "baudclk", "apb_pclk"; 241 dmas = <&dmamux 6 0 0 0 6 1>, <&dmamux 7 0 0 0 7 1>; 242 dma-names = "rx", "tx"; 243 status = "disabled"; 244 }; 245 246 uart7: serial@50004000 { 247 compatible = "renesas,r9a06g032-uart", "renesas,rzn1-uart"; 248 reg = <0x50004000 0x400>; 249 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 250 reg-shift = <2>; 251 reg-io-width = <4>; 252 clocks = <&sysctrl R9A06G032_CLK_UART7>, <&sysctrl R9A06G032_HCLK_UART7>; 253 clock-names = "baudclk", "apb_pclk"; 254 dmas = <&dmamux 4 0 0 0 20 1>, <&dmamux 5 0 0 0 21 1>; 255 dma-names = "rx", "tx"; 256 status = "disabled"; 257 }; 258 259 pinctrl: pinctrl@40067000 { 260 compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; 261 reg = <0x40067000 0x1000>, <0x51000000 0x480>; 262 clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; 263 clock-names = "bus"; 264 status = "okay"; 265 }; 266 267 nand_controller: nand-controller@40102000 { 268 compatible = "renesas,r9a06g032-nandc", "renesas,rzn1-nandc"; 269 reg = <0x40102000 0x2000>; 270 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 271 clocks = <&sysctrl R9A06G032_HCLK_NAND>, <&sysctrl R9A06G032_CLK_NAND>; 272 clock-names = "hclk", "eclk"; 273 power-domains = <&sysctrl>; 274 #address-cells = <1>; 275 #size-cells = <0>; 276 status = "disabled"; 277 }; 278 279 dma0: dma-controller@40104000 { 280 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 281 reg = <0x40104000 0x1000>; 282 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 283 clock-names = "hclk"; 284 clocks = <&sysctrl R9A06G032_HCLK_DMA0>; 285 dma-channels = <8>; 286 dma-requests = <16>; 287 dma-masters = <1>; 288 #dma-cells = <3>; 289 block_size = <0xfff>; 290 data-width = <8>; 291 }; 292 293 dma1: dma-controller@40105000 { 294 compatible = "renesas,r9a06g032-dma", "renesas,rzn1-dma"; 295 reg = <0x40105000 0x1000>; 296 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 297 clock-names = "hclk"; 298 clocks = <&sysctrl R9A06G032_HCLK_DMA1>; 299 dma-channels = <8>; 300 dma-requests = <16>; 301 dma-masters = <1>; 302 #dma-cells = <3>; 303 block_size = <0xfff>; 304 data-width = <8>; 305 }; 306 307 gmac2: ethernet@44002000 { 308 compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; 309 reg = <0x44002000 0x2000>; 310 interrupt-parent = <&gic>; 311 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; 315 clocks = <&sysctrl R9A06G032_HCLK_GMAC1>; 316 clock-names = "stmmaceth"; 317 power-domains = <&sysctrl>; 318 snps,multicast-filter-bins = <256>; 319 snps,perfect-filter-entries = <128>; 320 tx-fifo-depth = <2048>; 321 rx-fifo-depth = <4096>; 322 status = "disabled"; 323 }; 324 325 eth_miic: eth-miic@44030000 { 326 compatible = "renesas,r9a06g032-miic", "renesas,rzn1-miic"; 327 #address-cells = <1>; 328 #size-cells = <0>; 329 reg = <0x44030000 0x10000>; 330 clocks = <&sysctrl R9A06G032_CLK_MII_REF>, 331 <&sysctrl R9A06G032_CLK_RGMII_REF>, 332 <&sysctrl R9A06G032_CLK_RMII_REF>, 333 <&sysctrl R9A06G032_HCLK_SWITCH_RG>; 334 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 335 power-domains = <&sysctrl>; 336 status = "disabled"; 337 338 mii_conv1: mii-conv@1 { 339 reg = <1>; 340 status = "disabled"; 341 }; 342 343 mii_conv2: mii-conv@2 { 344 reg = <2>; 345 status = "disabled"; 346 }; 347 348 mii_conv3: mii-conv@3 { 349 reg = <3>; 350 status = "disabled"; 351 }; 352 353 mii_conv4: mii-conv@4 { 354 reg = <4>; 355 status = "disabled"; 356 }; 357 358 mii_conv5: mii-conv@5 { 359 reg = <5>; 360 status = "disabled"; 361 }; 362 }; 363 364 switch: switch@44050000 { 365 compatible = "renesas,r9a06g032-a5psw", "renesas,rzn1-a5psw"; 366 reg = <0x44050000 0x10000>; 367 clocks = <&sysctrl R9A06G032_HCLK_SWITCH>, 368 <&sysctrl R9A06G032_CLK_SWITCH>; 369 clock-names = "hclk", "clk"; 370 power-domains = <&sysctrl>; 371 status = "disabled"; 372 373 ethernet-ports { 374 #address-cells = <1>; 375 #size-cells = <0>; 376 377 switch_port0: port@0 { 378 reg = <0>; 379 pcs-handle = <&mii_conv5>; 380 status = "disabled"; 381 }; 382 383 switch_port1: port@1 { 384 reg = <1>; 385 pcs-handle = <&mii_conv4>; 386 status = "disabled"; 387 }; 388 389 switch_port2: port@2 { 390 reg = <2>; 391 pcs-handle = <&mii_conv3>; 392 status = "disabled"; 393 }; 394 395 switch_port3: port@3 { 396 reg = <3>; 397 pcs-handle = <&mii_conv2>; 398 status = "disabled"; 399 }; 400 401 switch_port4: port@4 { 402 reg = <4>; 403 ethernet = <&gmac2>; 404 label = "cpu"; 405 phy-mode = "internal"; 406 status = "disabled"; 407 fixed-link { 408 speed = <1000>; 409 full-duplex; 410 }; 411 }; 412 }; 413 }; 414 415 gic: interrupt-controller@44101000 { 416 compatible = "arm,gic-400", "arm,cortex-a7-gic"; 417 interrupt-controller; 418 #interrupt-cells = <3>; 419 reg = <0x44101000 0x1000>, /* Distributer */ 420 <0x44102000 0x2000>, /* CPU interface */ 421 <0x44104000 0x2000>, /* Virt interface control */ 422 <0x44106000 0x2000>; /* Virt CPU interface */ 423 interrupts = 424 <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 425 }; 426 427 can0: can@52104000 { 428 compatible = "renesas,r9a06g032-sja1000","renesas,rzn1-sja1000"; 429 reg = <0x52104000 0x800>; 430 reg-io-width = <4>; 431 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 432 clocks = <&sysctrl R9A06G032_HCLK_CAN0>; 433 power-domains = <&sysctrl>; 434 status = "disabled"; 435 }; 436 437 can1: can@52105000 { 438 compatible = "renesas,r9a06g032-sja1000", "renesas,rzn1-sja1000"; 439 reg = <0x52105000 0x800>; 440 reg-io-width = <4>; 441 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 442 clocks = <&sysctrl R9A06G032_HCLK_CAN1>; 443 power-domains = <&sysctrl>; 444 status = "disabled"; 445 }; 446 }; 447 448 timer { 449 compatible = "arm,armv7-timer"; 450 interrupt-parent = <&gic>; 451 arm,cpu-registers-not-fw-configured; 452 always-on; 453 interrupts = 454 <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 455 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 456 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 457 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 458 }; 459 460 usbphy: usb-phy { 461 #phy-cells = <0>; 462 compatible = "usb-nop-xceiv"; 463 status = "disabled"; 464 }; 465}; 466
