1// SPDX-License-Identifier: GPL-2.0 2/dts-v1/; 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/mfd/qcom-rpm.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/clock/qcom,gcc-ipq806x.h> 8#include <dt-bindings/clock/qcom,lcc-ipq806x.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/reset/qcom,gcc-ipq806x.h> 11#include <dt-bindings/soc/qcom,gsbi.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 model = "Qualcomm IPQ8064"; 18 compatible = "qcom,ipq8064"; 19 interrupt-parent = <&intc>; 20 21 cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "qcom,krait"; 27 enable-method = "qcom,kpss-acc-v1"; 28 device_type = "cpu"; 29 reg = <0>; 30 next-level-cache = <&L2>; 31 qcom,acc = <&acc0>; 32 qcom,saw = <&saw0>; 33 }; 34 35 cpu1: cpu@1 { 36 compatible = "qcom,krait"; 37 enable-method = "qcom,kpss-acc-v1"; 38 device_type = "cpu"; 39 reg = <1>; 40 next-level-cache = <&L2>; 41 qcom,acc = <&acc1>; 42 qcom,saw = <&saw1>; 43 }; 44 45 L2: l2-cache { 46 compatible = "cache"; 47 cache-level = <2>; 48 }; 49 }; 50 51 thermal-zones { 52 sensor0-thermal { 53 polling-delay-passive = <0>; 54 polling-delay = <0>; 55 thermal-sensors = <&tsens 0>; 56 57 trips { 58 cpu-critical { 59 temperature = <105000>; 60 hysteresis = <2000>; 61 type = "critical"; 62 }; 63 64 cpu-hot { 65 temperature = <95000>; 66 hysteresis = <2000>; 67 type = "hot"; 68 }; 69 }; 70 }; 71 72 sensor1-thermal { 73 polling-delay-passive = <0>; 74 polling-delay = <0>; 75 thermal-sensors = <&tsens 1>; 76 77 trips { 78 cpu-critical { 79 temperature = <105000>; 80 hysteresis = <2000>; 81 type = "critical"; 82 }; 83 84 cpu-hot { 85 temperature = <95000>; 86 hysteresis = <2000>; 87 type = "hot"; 88 }; 89 }; 90 }; 91 92 sensor2-thermal { 93 polling-delay-passive = <0>; 94 polling-delay = <0>; 95 thermal-sensors = <&tsens 2>; 96 97 trips { 98 cpu-critical { 99 temperature = <105000>; 100 hysteresis = <2000>; 101 type = "critical"; 102 }; 103 104 cpu-hot { 105 temperature = <95000>; 106 hysteresis = <2000>; 107 type = "hot"; 108 }; 109 }; 110 }; 111 112 sensor3-thermal { 113 polling-delay-passive = <0>; 114 polling-delay = <0>; 115 thermal-sensors = <&tsens 3>; 116 117 trips { 118 cpu-critical { 119 temperature = <105000>; 120 hysteresis = <2000>; 121 type = "critical"; 122 }; 123 124 cpu-hot { 125 temperature = <95000>; 126 hysteresis = <2000>; 127 type = "hot"; 128 }; 129 }; 130 }; 131 132 sensor4-thermal { 133 polling-delay-passive = <0>; 134 polling-delay = <0>; 135 thermal-sensors = <&tsens 4>; 136 137 trips { 138 cpu-critical { 139 temperature = <105000>; 140 hysteresis = <2000>; 141 type = "critical"; 142 }; 143 144 cpu-hot { 145 temperature = <95000>; 146 hysteresis = <2000>; 147 type = "hot"; 148 }; 149 }; 150 }; 151 152 sensor5-thermal { 153 polling-delay-passive = <0>; 154 polling-delay = <0>; 155 thermal-sensors = <&tsens 5>; 156 157 trips { 158 cpu-critical { 159 temperature = <105000>; 160 hysteresis = <2000>; 161 type = "critical"; 162 }; 163 164 cpu-hot { 165 temperature = <95000>; 166 hysteresis = <2000>; 167 type = "hot"; 168 }; 169 }; 170 }; 171 172 sensor6-thermal { 173 polling-delay-passive = <0>; 174 polling-delay = <0>; 175 thermal-sensors = <&tsens 6>; 176 177 trips { 178 cpu-critical { 179 temperature = <105000>; 180 hysteresis = <2000>; 181 type = "critical"; 182 }; 183 184 cpu-hot { 185 temperature = <95000>; 186 hysteresis = <2000>; 187 type = "hot"; 188 }; 189 }; 190 }; 191 192 sensor7-thermal { 193 polling-delay-passive = <0>; 194 polling-delay = <0>; 195 thermal-sensors = <&tsens 7>; 196 197 trips { 198 cpu-critical { 199 temperature = <105000>; 200 hysteresis = <2000>; 201 type = "critical"; 202 }; 203 204 cpu-hot { 205 temperature = <95000>; 206 hysteresis = <2000>; 207 type = "hot"; 208 }; 209 }; 210 }; 211 212 sensor8-thermal { 213 polling-delay-passive = <0>; 214 polling-delay = <0>; 215 thermal-sensors = <&tsens 8>; 216 217 trips { 218 cpu-critical { 219 temperature = <105000>; 220 hysteresis = <2000>; 221 type = "critical"; 222 }; 223 224 cpu-hot { 225 temperature = <95000>; 226 hysteresis = <2000>; 227 type = "hot"; 228 }; 229 }; 230 }; 231 232 sensor9-thermal { 233 polling-delay-passive = <0>; 234 polling-delay = <0>; 235 thermal-sensors = <&tsens 9>; 236 237 trips { 238 cpu-critical { 239 temperature = <105000>; 240 hysteresis = <2000>; 241 type = "critical"; 242 }; 243 244 cpu-hot { 245 temperature = <95000>; 246 hysteresis = <2000>; 247 type = "hot"; 248 }; 249 }; 250 }; 251 252 sensor10-thermal { 253 polling-delay-passive = <0>; 254 polling-delay = <0>; 255 thermal-sensors = <&tsens 10>; 256 257 trips { 258 cpu-critical { 259 temperature = <105000>; 260 hysteresis = <2000>; 261 type = "critical"; 262 }; 263 264 cpu-hot { 265 temperature = <95000>; 266 hysteresis = <2000>; 267 type = "hot"; 268 }; 269 }; 270 }; 271 }; 272 273 memory { 274 device_type = "memory"; 275 reg = <0x0 0x0>; 276 }; 277 278 cpu-pmu { 279 compatible = "qcom,krait-pmu"; 280 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 281 IRQ_TYPE_LEVEL_HIGH)>; 282 }; 283 284 reserved-memory { 285 #address-cells = <1>; 286 #size-cells = <1>; 287 ranges; 288 289 nss@40000000 { 290 reg = <0x40000000 0x1000000>; 291 no-map; 292 }; 293 294 smem: smem@41000000 { 295 compatible = "qcom,smem"; 296 reg = <0x41000000 0x200000>; 297 no-map; 298 299 hwlocks = <&sfpb_mutex 3>; 300 }; 301 }; 302 303 clocks { 304 cxo_board: cxo_board { 305 compatible = "fixed-clock"; 306 #clock-cells = <0>; 307 clock-frequency = <25000000>; 308 }; 309 310 pxo_board: pxo_board { 311 compatible = "fixed-clock"; 312 #clock-cells = <0>; 313 clock-frequency = <25000000>; 314 }; 315 316 sleep_clk: sleep_clk { 317 compatible = "fixed-clock"; 318 clock-frequency = <32768>; 319 #clock-cells = <0>; 320 }; 321 }; 322 323 firmware { 324 scm { 325 compatible = "qcom,scm-ipq806x", "qcom,scm"; 326 }; 327 }; 328 329 soc: soc { 330 #address-cells = <1>; 331 #size-cells = <1>; 332 ranges; 333 compatible = "simple-bus"; 334 335 stmmac_axi_setup: stmmac-axi-config { 336 snps,wr_osr_lmt = <7>; 337 snps,rd_osr_lmt = <7>; 338 snps,blen = <16 0 0 0 0 0 0>; 339 }; 340 341 vsdcc_fixed: vsdcc-regulator { 342 compatible = "regulator-fixed"; 343 regulator-name = "SDCC Power"; 344 regulator-min-microvolt = <3300000>; 345 regulator-max-microvolt = <3300000>; 346 regulator-always-on; 347 }; 348 349 rpm: rpm@108000 { 350 compatible = "qcom,rpm-ipq8064"; 351 reg = <0x00108000 0x1000>; 352 qcom,ipc = <&l2cc 0x8 2>; 353 354 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 355 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 356 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 357 interrupt-names = "ack", "err", "wakeup"; 358 359 clocks = <&gcc RPM_MSG_RAM_H_CLK>; 360 clock-names = "ram"; 361 362 rpmcc: clock-controller { 363 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc"; 364 #clock-cells = <1>; 365 }; 366 }; 367 368 qcom,ssbi@500000 { 369 compatible = "qcom,ssbi"; 370 reg = <0x00500000 0x1000>; 371 qcom,controller-type = "pmic-arbiter"; 372 }; 373 374 qfprom: qfprom@700000 { 375 compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; 376 reg = <0x00700000 0x1000>; 377 #address-cells = <1>; 378 #size-cells = <1>; 379 speedbin_efuse: speedbin@c0 { 380 reg = <0xc0 0x4>; 381 }; 382 tsens_calib: calib@400 { 383 reg = <0x400 0xb>; 384 }; 385 tsens_calib_backup: calib_backup@410 { 386 reg = <0x410 0xb>; 387 }; 388 }; 389 390 qcom_pinmux: pinmux@800000 { 391 compatible = "qcom,ipq8064-pinctrl"; 392 reg = <0x00800000 0x4000>; 393 394 gpio-controller; 395 gpio-ranges = <&qcom_pinmux 0 0 69>; 396 #gpio-cells = <2>; 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 400 401 pcie0_pins: pcie0_pinmux { 402 mux { 403 pins = "gpio3"; 404 function = "pcie1_rst"; 405 drive-strength = <12>; 406 bias-disable; 407 }; 408 }; 409 410 pcie1_pins: pcie1_pinmux { 411 mux { 412 pins = "gpio48"; 413 function = "pcie2_rst"; 414 drive-strength = <12>; 415 bias-disable; 416 }; 417 }; 418 419 pcie2_pins: pcie2_pinmux { 420 mux { 421 pins = "gpio63"; 422 function = "pcie3_rst"; 423 drive-strength = <12>; 424 bias-disable; 425 }; 426 }; 427 428 i2c4_pins: i2c4-default { 429 pins = "gpio12", "gpio13"; 430 function = "gsbi4"; 431 drive-strength = <12>; 432 bias-disable; 433 }; 434 435 spi_pins: spi_pins { 436 mux { 437 pins = "gpio18", "gpio19", "gpio21"; 438 function = "gsbi5"; 439 drive-strength = <10>; 440 bias-none; 441 }; 442 }; 443 444 leds_pins: leds_pins { 445 mux { 446 pins = "gpio7", "gpio8", "gpio9", 447 "gpio26", "gpio53"; 448 function = "gpio"; 449 drive-strength = <2>; 450 bias-pull-down; 451 output-low; 452 }; 453 }; 454 455 buttons_pins: buttons_pins { 456 mux { 457 pins = "gpio54"; 458 drive-strength = <2>; 459 bias-pull-up; 460 }; 461 }; 462 463 nand_pins: nand_pins { 464 mux { 465 pins = "gpio34", "gpio35", "gpio36", 466 "gpio37", "gpio38", "gpio39", 467 "gpio40", "gpio41", "gpio42", 468 "gpio43", "gpio44", "gpio45", 469 "gpio46", "gpio47"; 470 function = "nand"; 471 drive-strength = <10>; 472 bias-disable; 473 }; 474 475 pullups { 476 pins = "gpio39"; 477 function = "nand"; 478 drive-strength = <10>; 479 bias-pull-up; 480 }; 481 482 hold { 483 pins = "gpio40", "gpio41", "gpio42", 484 "gpio43", "gpio44", "gpio45", 485 "gpio46", "gpio47"; 486 function = "nand"; 487 drive-strength = <10>; 488 bias-bus-hold; 489 }; 490 }; 491 492 mdio0_pins: mdio0-pins { 493 mux { 494 pins = "gpio0", "gpio1"; 495 function = "mdio"; 496 drive-strength = <8>; 497 bias-disable; 498 }; 499 }; 500 501 rgmii2_pins: rgmii2-pins { 502 mux { 503 pins = "gpio27", "gpio28", "gpio29", 504 "gpio30", "gpio31", "gpio32", 505 "gpio51", "gpio52", "gpio59", 506 "gpio60", "gpio61", "gpio62"; 507 function = "rgmii2"; 508 drive-strength = <8>; 509 bias-disable; 510 }; 511 }; 512 }; 513 514 gcc: clock-controller@900000 { 515 compatible = "qcom,gcc-ipq8064", "syscon"; 516 clocks = <&pxo_board>, <&cxo_board>; 517 clock-names = "pxo", "cxo"; 518 reg = <0x00900000 0x4000>; 519 #clock-cells = <1>; 520 #reset-cells = <1>; 521 #power-domain-cells = <1>; 522 523 tsens: thermal-sensor@900000 { 524 compatible = "qcom,ipq8064-tsens"; 525 526 nvmem-cells = <&tsens_calib>, <&tsens_calib_backup>; 527 nvmem-cell-names = "calib", "calib_backup"; 528 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 529 interrupt-names = "uplow"; 530 531 #qcom,sensors = <11>; 532 #thermal-sensor-cells = <1>; 533 }; 534 }; 535 536 sfpb_mutex: hwlock@1200600 { 537 compatible = "qcom,sfpb-mutex"; 538 reg = <0x01200600 0x100>; 539 540 #hwlock-cells = <1>; 541 }; 542 543 intc: interrupt-controller@2000000 { 544 compatible = "qcom,msm-qgic2"; 545 interrupt-controller; 546 #interrupt-cells = <3>; 547 reg = <0x02000000 0x1000>, 548 <0x02002000 0x1000>; 549 }; 550 551 timer@200a000 { 552 compatible = "qcom,kpss-timer", 553 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; 554 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | 555 IRQ_TYPE_EDGE_RISING)>, 556 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | 557 IRQ_TYPE_EDGE_RISING)>, 558 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | 559 IRQ_TYPE_EDGE_RISING)>, 560 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | 561 IRQ_TYPE_EDGE_RISING)>, 562 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | 563 IRQ_TYPE_EDGE_RISING)>; 564 reg = <0x0200a000 0x100>; 565 clock-frequency = <25000000>, 566 <32768>; 567 clocks = <&sleep_clk>; 568 clock-names = "sleep"; 569 cpu-offset = <0x80000>; 570 }; 571 572 l2cc: clock-controller@2011000 { 573 compatible = "qcom,kpss-gcc", "syscon"; 574 reg = <0x02011000 0x1000>; 575 clocks = <&gcc PLL8_VOTE>, <&pxo_board>; 576 clock-names = "pll8_vote", "pxo"; 577 clock-output-names = "acpu_l2_aux"; 578 }; 579 580 acc0: clock-controller@2088000 { 581 compatible = "qcom,kpss-acc-v1"; 582 reg = <0x02088000 0x1000>, <0x02008000 0x1000>; 583 }; 584 585 saw0: regulator@2089000 { 586 compatible = "qcom,saw2"; 587 reg = <0x02089000 0x1000>, <0x02009000 0x1000>; 588 regulator; 589 }; 590 591 acc1: clock-controller@2098000 { 592 compatible = "qcom,kpss-acc-v1"; 593 reg = <0x02098000 0x1000>, <0x02008000 0x1000>; 594 }; 595 596 saw1: regulator@2099000 { 597 compatible = "qcom,saw2"; 598 reg = <0x02099000 0x1000>, <0x02009000 0x1000>; 599 regulator; 600 }; 601 602 nss_common: syscon@03000000 { 603 compatible = "syscon"; 604 reg = <0x03000000 0x0000FFFF>; 605 }; 606 607 usb3_0: usb3@100f8800 { 608 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 609 #address-cells = <1>; 610 #size-cells = <1>; 611 reg = <0x100f8800 0x8000>; 612 clocks = <&gcc USB30_0_MASTER_CLK>; 613 clock-names = "core"; 614 615 ranges; 616 617 resets = <&gcc USB30_0_MASTER_RESET>; 618 reset-names = "master"; 619 620 status = "disabled"; 621 622 dwc3_0: dwc3@10000000 { 623 compatible = "snps,dwc3"; 624 reg = <0x10000000 0xcd00>; 625 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 626 phys = <&hs_phy_0>, <&ss_phy_0>; 627 phy-names = "usb2-phy", "usb3-phy"; 628 dr_mode = "host"; 629 snps,dis_u3_susphy_quirk; 630 }; 631 }; 632 633 hs_phy_0: phy@100f8800 { 634 compatible = "qcom,ipq806x-usb-phy-hs"; 635 reg = <0x100f8800 0x30>; 636 clocks = <&gcc USB30_0_UTMI_CLK>; 637 clock-names = "ref"; 638 #phy-cells = <0>; 639 640 status = "disabled"; 641 }; 642 643 ss_phy_0: phy@100f8830 { 644 compatible = "qcom,ipq806x-usb-phy-ss"; 645 reg = <0x100f8830 0x30>; 646 clocks = <&gcc USB30_0_MASTER_CLK>; 647 clock-names = "ref"; 648 #phy-cells = <0>; 649 650 status = "disabled"; 651 }; 652 653 usb3_1: usb3@110f8800 { 654 compatible = "qcom,ipq8064-dwc3", "qcom,dwc3"; 655 #address-cells = <1>; 656 #size-cells = <1>; 657 reg = <0x110f8800 0x8000>; 658 clocks = <&gcc USB30_1_MASTER_CLK>; 659 clock-names = "core"; 660 661 ranges; 662 663 resets = <&gcc USB30_1_MASTER_RESET>; 664 reset-names = "master"; 665 666 status = "disabled"; 667 668 dwc3_1: dwc3@11000000 { 669 compatible = "snps,dwc3"; 670 reg = <0x11000000 0xcd00>; 671 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 672 phys = <&hs_phy_1>, <&ss_phy_1>; 673 phy-names = "usb2-phy", "usb3-phy"; 674 dr_mode = "host"; 675 snps,dis_u3_susphy_quirk; 676 }; 677 }; 678 679 hs_phy_1: phy@110f8800 { 680 compatible = "qcom,ipq806x-usb-phy-hs"; 681 reg = <0x110f8800 0x30>; 682 clocks = <&gcc USB30_1_UTMI_CLK>; 683 clock-names = "ref"; 684 #phy-cells = <0>; 685 686 status = "disabled"; 687 }; 688 689 ss_phy_1: phy@110f8830 { 690 compatible = "qcom,ipq806x-usb-phy-ss"; 691 reg = <0x110f8830 0x30>; 692 clocks = <&gcc USB30_1_MASTER_CLK>; 693 clock-names = "ref"; 694 #phy-cells = <0>; 695 696 status = "disabled"; 697 }; 698 699 sdcc3bam: dma-controller@12182000 { 700 compatible = "qcom,bam-v1.3.0"; 701 reg = <0x12182000 0x8000>; 702 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&gcc SDC3_H_CLK>; 704 clock-names = "bam_clk"; 705 #dma-cells = <1>; 706 qcom,ee = <0>; 707 }; 708 709 sdcc1bam: dma-controller@12402000 { 710 compatible = "qcom,bam-v1.3.0"; 711 reg = <0x12402000 0x8000>; 712 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 713 clocks = <&gcc SDC1_H_CLK>; 714 clock-names = "bam_clk"; 715 #dma-cells = <1>; 716 qcom,ee = <0>; 717 }; 718 719 amba: amba { 720 compatible = "simple-bus"; 721 #address-cells = <1>; 722 #size-cells = <1>; 723 ranges; 724 725 sdcc3: mmc@12180000 { 726 compatible = "arm,pl18x", "arm,primecell"; 727 arm,primecell-periphid = <0x00051180>; 728 status = "disabled"; 729 reg = <0x12180000 0x2000>; 730 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 731 interrupt-names = "cmd_irq"; 732 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; 733 clock-names = "mclk", "apb_pclk"; 734 bus-width = <8>; 735 cap-sd-highspeed; 736 cap-mmc-highspeed; 737 max-frequency = <192000000>; 738 sd-uhs-sdr104; 739 sd-uhs-ddr50; 740 vqmmc-supply = <&vsdcc_fixed>; 741 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; 742 dma-names = "tx", "rx"; 743 }; 744 745 sdcc1: mmc@12400000 { 746 status = "disabled"; 747 compatible = "arm,pl18x", "arm,primecell"; 748 arm,primecell-periphid = <0x00051180>; 749 reg = <0x12400000 0x2000>; 750 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 751 interrupt-names = "cmd_irq"; 752 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; 753 clock-names = "mclk", "apb_pclk"; 754 bus-width = <8>; 755 max-frequency = <96000000>; 756 non-removable; 757 cap-sd-highspeed; 758 cap-mmc-highspeed; 759 mmc-ddr-1_8v; 760 vmmc-supply = <&vsdcc_fixed>; 761 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; 762 dma-names = "tx", "rx"; 763 }; 764 }; 765 766 gsbi1: gsbi@12440000 { 767 compatible = "qcom,gsbi-v1.0.0"; 768 reg = <0x12440000 0x100>; 769 cell-index = <1>; 770 clocks = <&gcc GSBI1_H_CLK>; 771 clock-names = "iface"; 772 #address-cells = <1>; 773 #size-cells = <1>; 774 ranges; 775 776 syscon-tcsr = <&tcsr>; 777 778 status = "disabled"; 779 780 gsbi1_serial: serial@12450000 { 781 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 782 reg = <0x12450000 0x100>, 783 <0x12400000 0x03>; 784 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 785 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 786 clock-names = "core", "iface"; 787 788 status = "disabled"; 789 }; 790 791 gsbi1_i2c: i2c@12460000 { 792 compatible = "qcom,i2c-qup-v1.1.1"; 793 reg = <0x12460000 0x1000>; 794 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 795 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 796 clock-names = "core", "iface"; 797 #address-cells = <1>; 798 #size-cells = <0>; 799 800 status = "disabled"; 801 }; 802 }; 803 804 gsbi2: gsbi@12480000 { 805 compatible = "qcom,gsbi-v1.0.0"; 806 cell-index = <2>; 807 reg = <0x12480000 0x100>; 808 clocks = <&gcc GSBI2_H_CLK>; 809 clock-names = "iface"; 810 #address-cells = <1>; 811 #size-cells = <1>; 812 ranges; 813 status = "disabled"; 814 815 syscon-tcsr = <&tcsr>; 816 817 gsbi2_serial: serial@12490000 { 818 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 819 reg = <0x12490000 0x1000>, 820 <0x12480000 0x1000>; 821 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>; 823 clock-names = "core", "iface"; 824 status = "disabled"; 825 }; 826 827 gsbi2_i2c: i2c@124a0000 { 828 compatible = "qcom,i2c-qup-v1.1.1"; 829 reg = <0x124a0000 0x1000>; 830 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 831 832 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; 833 clock-names = "core", "iface"; 834 status = "disabled"; 835 836 #address-cells = <1>; 837 #size-cells = <0>; 838 }; 839 }; 840 841 gsbi4: gsbi@16300000 { 842 compatible = "qcom,gsbi-v1.0.0"; 843 cell-index = <4>; 844 reg = <0x16300000 0x100>; 845 clocks = <&gcc GSBI4_H_CLK>; 846 clock-names = "iface"; 847 #address-cells = <1>; 848 #size-cells = <1>; 849 ranges; 850 status = "disabled"; 851 852 syscon-tcsr = <&tcsr>; 853 854 gsbi4_serial: serial@16340000 { 855 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 856 reg = <0x16340000 0x1000>, 857 <0x16300000 0x1000>; 858 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>; 860 clock-names = "core", "iface"; 861 status = "disabled"; 862 }; 863 864 i2c@16380000 { 865 compatible = "qcom,i2c-qup-v1.1.1"; 866 reg = <0x16380000 0x1000>; 867 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 868 869 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>; 870 clock-names = "core", "iface"; 871 status = "disabled"; 872 873 #address-cells = <1>; 874 #size-cells = <0>; 875 }; 876 }; 877 878 gsbi6: gsbi@16500000 { 879 compatible = "qcom,gsbi-v1.0.0"; 880 reg = <0x16500000 0x100>; 881 cell-index = <6>; 882 clocks = <&gcc GSBI6_H_CLK>; 883 clock-names = "iface"; 884 #address-cells = <1>; 885 #size-cells = <1>; 886 ranges; 887 888 syscon-tcsr = <&tcsr>; 889 890 status = "disabled"; 891 892 gsbi6_i2c: i2c@16580000 { 893 compatible = "qcom,i2c-qup-v1.1.1"; 894 reg = <0x16580000 0x1000>; 895 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 896 897 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 898 clock-names = "core", "iface"; 899 900 #address-cells = <1>; 901 #size-cells = <0>; 902 903 status = "disabled"; 904 }; 905 906 gsbi6_spi: spi@16580000 { 907 compatible = "qcom,spi-qup-v1.1.1"; 908 reg = <0x16580000 0x1000>; 909 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 910 911 clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>; 912 clock-names = "core", "iface"; 913 914 #address-cells = <1>; 915 #size-cells = <0>; 916 917 status = "disabled"; 918 }; 919 }; 920 921 gsbi7: gsbi@16600000 { 922 status = "disabled"; 923 compatible = "qcom,gsbi-v1.0.0"; 924 cell-index = <7>; 925 reg = <0x16600000 0x100>; 926 clocks = <&gcc GSBI7_H_CLK>; 927 clock-names = "iface"; 928 #address-cells = <1>; 929 #size-cells = <1>; 930 ranges; 931 syscon-tcsr = <&tcsr>; 932 933 gsbi7_serial: serial@16640000 { 934 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 935 reg = <0x16640000 0x1000>, 936 <0x16600000 0x1000>; 937 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 938 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; 939 clock-names = "core", "iface"; 940 status = "disabled"; 941 }; 942 943 gsbi7_i2c: i2c@16680000 { 944 compatible = "qcom,i2c-qup-v1.1.1"; 945 reg = <0x16680000 0x1000>; 946 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 947 948 clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>; 949 clock-names = "core", "iface"; 950 951 #address-cells = <1>; 952 #size-cells = <0>; 953 954 status = "disabled"; 955 }; 956 }; 957 958 adm_dma: dma-controller@18300000 { 959 compatible = "qcom,adm"; 960 reg = <0x18300000 0x100000>; 961 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 962 #dma-cells = <1>; 963 964 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>; 965 clock-names = "core", "iface"; 966 967 resets = <&gcc ADM0_RESET>, 968 <&gcc ADM0_PBUS_RESET>, 969 <&gcc ADM0_C0_RESET>, 970 <&gcc ADM0_C1_RESET>, 971 <&gcc ADM0_C2_RESET>; 972 reset-names = "clk", "pbus", "c0", "c1", "c2"; 973 qcom,ee = <0>; 974 975 status = "disabled"; 976 }; 977 978 gsbi5: gsbi@1a200000 { 979 compatible = "qcom,gsbi-v1.0.0"; 980 cell-index = <5>; 981 reg = <0x1a200000 0x100>; 982 clocks = <&gcc GSBI5_H_CLK>; 983 clock-names = "iface"; 984 #address-cells = <1>; 985 986 #size-cells = <1>; 987 ranges; 988 status = "disabled"; 989 990 syscon-tcsr = <&tcsr>; 991 992 gsbi5_serial: serial@1a240000 { 993 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 994 reg = <0x1a240000 0x1000>, 995 <0x1a200000 0x1000>; 996 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 997 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; 998 clock-names = "core", "iface"; 999 status = "disabled"; 1000 }; 1001 1002 i2c@1a280000 { 1003 compatible = "qcom,i2c-qup-v1.1.1"; 1004 reg = <0x1a280000 0x1000>; 1005 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1006 1007 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1008 clock-names = "core", "iface"; 1009 status = "disabled"; 1010 1011 #address-cells = <1>; 1012 #size-cells = <0>; 1013 }; 1014 1015 spi@1a280000 { 1016 compatible = "qcom,spi-qup-v1.1.1"; 1017 reg = <0x1a280000 0x1000>; 1018 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 1019 1020 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>; 1021 clock-names = "core", "iface"; 1022 status = "disabled"; 1023 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 }; 1027 }; 1028 1029 tcsr: syscon@1a400000 { 1030 compatible = "qcom,tcsr-ipq8064", "syscon"; 1031 reg = <0x1a400000 0x100>; 1032 }; 1033 1034 rng@1a500000 { 1035 compatible = "qcom,prng"; 1036 reg = <0x1a500000 0x200>; 1037 clocks = <&gcc PRNG_CLK>; 1038 clock-names = "core"; 1039 }; 1040 1041 nand: nand-controller@1ac00000 { 1042 compatible = "qcom,ipq806x-nand"; 1043 reg = <0x1ac00000 0x800>; 1044 1045 pinctrl-0 = <&nand_pins>; 1046 pinctrl-names = "default"; 1047 1048 clocks = <&gcc EBI2_CLK>, 1049 <&gcc EBI2_AON_CLK>; 1050 clock-names = "core", "aon"; 1051 1052 dmas = <&adm_dma 3>; 1053 dma-names = "rxtx"; 1054 qcom,cmd-crci = <15>; 1055 qcom,data-crci = <3>; 1056 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 1060 status = "disabled"; 1061 }; 1062 1063 sata_phy: sata-phy@1b400000 { 1064 compatible = "qcom,ipq806x-sata-phy"; 1065 reg = <0x1b400000 0x200>; 1066 1067 clocks = <&gcc SATA_PHY_CFG_CLK>; 1068 clock-names = "cfg"; 1069 1070 #phy-cells = <0>; 1071 status = "disabled"; 1072 }; 1073 1074 pcie0: pci@1b500000 { 1075 compatible = "qcom,pcie-ipq8064"; 1076 reg = <0x1b500000 0x1000 1077 0x1b502000 0x80 1078 0x1b600000 0x100 1079 0x0ff00000 0x100000>; 1080 reg-names = "dbi", "elbi", "parf", "config"; 1081 device_type = "pci"; 1082 linux,pci-domain = <0>; 1083 bus-range = <0x00 0xff>; 1084 num-lanes = <1>; 1085 #address-cells = <3>; 1086 #size-cells = <2>; 1087 1088 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */ 1089 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */ 1090 1091 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1092 interrupt-names = "msi"; 1093 #interrupt-cells = <1>; 1094 interrupt-map-mask = <0 0 0 0x7>; 1095 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1096 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1097 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1098 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1099 1100 clocks = <&gcc PCIE_A_CLK>, 1101 <&gcc PCIE_H_CLK>, 1102 <&gcc PCIE_PHY_CLK>, 1103 <&gcc PCIE_AUX_CLK>, 1104 <&gcc PCIE_ALT_REF_CLK>; 1105 clock-names = "core", "iface", "phy", "aux", "ref"; 1106 1107 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>; 1108 assigned-clock-rates = <100000000>; 1109 1110 resets = <&gcc PCIE_ACLK_RESET>, 1111 <&gcc PCIE_HCLK_RESET>, 1112 <&gcc PCIE_POR_RESET>, 1113 <&gcc PCIE_PCI_RESET>, 1114 <&gcc PCIE_PHY_RESET>, 1115 <&gcc PCIE_EXT_RESET>; 1116 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1117 1118 pinctrl-0 = <&pcie0_pins>; 1119 pinctrl-names = "default"; 1120 1121 status = "disabled"; 1122 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>; 1123 }; 1124 1125 pcie1: pci@1b700000 { 1126 compatible = "qcom,pcie-ipq8064"; 1127 reg = <0x1b700000 0x1000 1128 0x1b702000 0x80 1129 0x1b800000 0x100 1130 0x31f00000 0x100000>; 1131 reg-names = "dbi", "elbi", "parf", "config"; 1132 device_type = "pci"; 1133 linux,pci-domain = <1>; 1134 bus-range = <0x00 0xff>; 1135 num-lanes = <1>; 1136 #address-cells = <3>; 1137 #size-cells = <2>; 1138 1139 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */ 1140 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */ 1141 1142 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1143 interrupt-names = "msi"; 1144 #interrupt-cells = <1>; 1145 interrupt-map-mask = <0 0 0 0x7>; 1146 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1147 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1148 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1149 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1150 1151 clocks = <&gcc PCIE_1_A_CLK>, 1152 <&gcc PCIE_1_H_CLK>, 1153 <&gcc PCIE_1_PHY_CLK>, 1154 <&gcc PCIE_1_AUX_CLK>, 1155 <&gcc PCIE_1_ALT_REF_CLK>; 1156 clock-names = "core", "iface", "phy", "aux", "ref"; 1157 1158 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>; 1159 assigned-clock-rates = <100000000>; 1160 1161 resets = <&gcc PCIE_1_ACLK_RESET>, 1162 <&gcc PCIE_1_HCLK_RESET>, 1163 <&gcc PCIE_1_POR_RESET>, 1164 <&gcc PCIE_1_PCI_RESET>, 1165 <&gcc PCIE_1_PHY_RESET>, 1166 <&gcc PCIE_1_EXT_RESET>; 1167 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1168 1169 pinctrl-0 = <&pcie1_pins>; 1170 pinctrl-names = "default"; 1171 1172 status = "disabled"; 1173 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>; 1174 }; 1175 1176 pcie2: pci@1b900000 { 1177 compatible = "qcom,pcie-ipq8064"; 1178 reg = <0x1b900000 0x1000 1179 0x1b902000 0x80 1180 0x1ba00000 0x100 1181 0x35f00000 0x100000>; 1182 reg-names = "dbi", "elbi", "parf", "config"; 1183 device_type = "pci"; 1184 linux,pci-domain = <2>; 1185 bus-range = <0x00 0xff>; 1186 num-lanes = <1>; 1187 #address-cells = <3>; 1188 #size-cells = <2>; 1189 1190 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */ 1191 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */ 1192 1193 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 1194 interrupt-names = "msi"; 1195 #interrupt-cells = <1>; 1196 interrupt-map-mask = <0 0 0 0x7>; 1197 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1198 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1199 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1200 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1201 1202 clocks = <&gcc PCIE_2_A_CLK>, 1203 <&gcc PCIE_2_H_CLK>, 1204 <&gcc PCIE_2_PHY_CLK>, 1205 <&gcc PCIE_2_AUX_CLK>, 1206 <&gcc PCIE_2_ALT_REF_CLK>; 1207 clock-names = "core", "iface", "phy", "aux", "ref"; 1208 1209 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>; 1210 assigned-clock-rates = <100000000>; 1211 1212 resets = <&gcc PCIE_2_ACLK_RESET>, 1213 <&gcc PCIE_2_HCLK_RESET>, 1214 <&gcc PCIE_2_POR_RESET>, 1215 <&gcc PCIE_2_PCI_RESET>, 1216 <&gcc PCIE_2_PHY_RESET>, 1217 <&gcc PCIE_2_EXT_RESET>; 1218 reset-names = "axi", "ahb", "por", "pci", "phy", "ext"; 1219 1220 pinctrl-0 = <&pcie2_pins>; 1221 pinctrl-names = "default"; 1222 1223 status = "disabled"; 1224 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>; 1225 }; 1226 1227 qsgmii_csr: syscon@1bb00000 { 1228 compatible = "syscon"; 1229 reg = <0x1bb00000 0x000001FF>; 1230 }; 1231 1232 lcc: clock-controller@28000000 { 1233 compatible = "qcom,lcc-ipq8064"; 1234 reg = <0x28000000 0x1000>; 1235 #clock-cells = <1>; 1236 #reset-cells = <1>; 1237 }; 1238 1239 lpass@28100000 { 1240 compatible = "qcom,lpass-cpu"; 1241 status = "disabled"; 1242 clocks = <&lcc AHBIX_CLK>, 1243 <&lcc MI2S_OSR_CLK>, 1244 <&lcc MI2S_BIT_CLK>; 1245 clock-names = "ahbix-clk", 1246 "mi2s-osr-clk", 1247 "mi2s-bit-clk"; 1248 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1249 interrupt-names = "lpass-irq-lpaif"; 1250 reg = <0x28100000 0x10000>; 1251 reg-names = "lpass-lpaif"; 1252 }; 1253 1254 sata: sata@29000000 { 1255 compatible = "qcom,ipq806x-ahci", "generic-ahci"; 1256 reg = <0x29000000 0x180>; 1257 1258 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1259 1260 clocks = <&gcc SFAB_SATA_S_H_CLK>, 1261 <&gcc SATA_H_CLK>, 1262 <&gcc SATA_A_CLK>, 1263 <&gcc SATA_RXOOB_CLK>, 1264 <&gcc SATA_PMALIVE_CLK>; 1265 clock-names = "slave_face", "iface", "core", 1266 "rxoob", "pmalive"; 1267 1268 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; 1269 assigned-clock-rates = <100000000>, <100000000>; 1270 1271 phys = <&sata_phy>; 1272 phy-names = "sata-phy"; 1273 status = "disabled"; 1274 }; 1275 1276 gmac0: ethernet@37000000 { 1277 device_type = "network"; 1278 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1279 reg = <0x37000000 0x200000>; 1280 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1281 interrupt-names = "macirq"; 1282 1283 snps,axi-config = <&stmmac_axi_setup>; 1284 snps,pbl = <32>; 1285 snps,aal; 1286 1287 qcom,nss-common = <&nss_common>; 1288 qcom,qsgmii-csr = <&qsgmii_csr>; 1289 1290 clocks = <&gcc GMAC_CORE1_CLK>; 1291 clock-names = "stmmaceth"; 1292 1293 resets = <&gcc GMAC_CORE1_RESET>, 1294 <&gcc GMAC_AHB_RESET>; 1295 reset-names = "stmmaceth", "ahb"; 1296 1297 status = "disabled"; 1298 }; 1299 1300 gmac1: ethernet@37200000 { 1301 device_type = "network"; 1302 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1303 reg = <0x37200000 0x200000>; 1304 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 1305 interrupt-names = "macirq"; 1306 1307 snps,axi-config = <&stmmac_axi_setup>; 1308 snps,pbl = <32>; 1309 snps,aal; 1310 1311 qcom,nss-common = <&nss_common>; 1312 qcom,qsgmii-csr = <&qsgmii_csr>; 1313 1314 clocks = <&gcc GMAC_CORE2_CLK>; 1315 clock-names = "stmmaceth"; 1316 1317 resets = <&gcc GMAC_CORE2_RESET>, 1318 <&gcc GMAC_AHB_RESET>; 1319 reset-names = "stmmaceth", "ahb"; 1320 1321 status = "disabled"; 1322 }; 1323 1324 gmac2: ethernet@37400000 { 1325 device_type = "network"; 1326 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1327 reg = <0x37400000 0x200000>; 1328 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1329 interrupt-names = "macirq"; 1330 1331 snps,axi-config = <&stmmac_axi_setup>; 1332 snps,pbl = <32>; 1333 snps,aal; 1334 1335 qcom,nss-common = <&nss_common>; 1336 qcom,qsgmii-csr = <&qsgmii_csr>; 1337 1338 clocks = <&gcc GMAC_CORE3_CLK>; 1339 clock-names = "stmmaceth"; 1340 1341 resets = <&gcc GMAC_CORE3_RESET>, 1342 <&gcc GMAC_AHB_RESET>; 1343 reset-names = "stmmaceth", "ahb"; 1344 1345 status = "disabled"; 1346 }; 1347 1348 gmac3: ethernet@37600000 { 1349 device_type = "network"; 1350 compatible = "qcom,ipq806x-gmac", "snps,dwmac"; 1351 reg = <0x37600000 0x200000>; 1352 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1353 interrupt-names = "macirq"; 1354 1355 snps,axi-config = <&stmmac_axi_setup>; 1356 snps,pbl = <32>; 1357 snps,aal; 1358 1359 qcom,nss-common = <&nss_common>; 1360 qcom,qsgmii-csr = <&qsgmii_csr>; 1361 1362 clocks = <&gcc GMAC_CORE4_CLK>; 1363 clock-names = "stmmaceth"; 1364 1365 resets = <&gcc GMAC_CORE4_RESET>, 1366 <&gcc GMAC_AHB_RESET>; 1367 reset-names = "stmmaceth", "ahb"; 1368 1369 status = "disabled"; 1370 }; 1371 }; 1372}; 1373
