1[
2  {
3    "EventName": "ls_locks.bus_lock",
4    "EventCode": "0x25",
5    "BriefDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.",
6    "PublicDescription": "Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type.",
7    "UMask": "0x1"
8  },
9  {
10    "EventName": "ls_dispatch.ld_st_dispatch",
11    "EventCode": "0x29",
12    "BriefDescription": "Load-op-Stores.",
13    "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed. Load-op-Stores.",
14    "UMask": "0x4"
15  },
16  {
17    "EventName": "ls_dispatch.store_dispatch",
18    "EventCode": "0x29",
19    "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
20    "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
21    "UMask": "0x2"
22  },
23  {
24    "EventName": "ls_dispatch.ld_dispatch",
25    "EventCode": "0x29",
26    "BriefDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
27    "PublicDescription": "Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
28    "UMask": "0x1"
29  },
30  {
31    "EventName": "ls_stlf",
32    "EventCode": "0x35",
33    "BriefDescription": "Number of STLF hits."
34  },
35  {
36    "EventName": "ls_dc_accesses",
37    "EventCode": "0x40",
38    "BriefDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
39  },
40  {
41    "EventName": "ls_l1_d_tlb_miss.all",
42    "EventCode": "0x45",
43    "BriefDescription": "L1 DTLB Miss or Reload off all sizes.",
44    "PublicDescription": "L1 DTLB Miss or Reload off all sizes.",
45    "UMask": "0xff"
46  },
47  {
48    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
49    "EventCode": "0x45",
50    "BriefDescription": "L1 DTLB Miss of a page of 1G size.",
51    "PublicDescription": "L1 DTLB Miss of a page of 1G size.",
52    "UMask": "0x80"
53  },
54  {
55    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
56    "EventCode": "0x45",
57    "BriefDescription": "L1 DTLB Miss of a page of 2M size.",
58    "PublicDescription": "L1 DTLB Miss of a page of 2M size.",
59    "UMask": "0x40"
60  },
61  {
62    "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_miss",
63    "EventCode": "0x45",
64    "BriefDescription": "L1 DTLB Miss of a page of 32K size.",
65    "PublicDescription": "L1 DTLB Miss of a page of 32K size.",
66    "UMask": "0x20"
67  },
68  {
69    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
70    "EventCode": "0x45",
71    "BriefDescription": "L1 DTLB Miss of a page of 4K size.",
72    "PublicDescription": "L1 DTLB Miss of a page of 4K size.",
73    "UMask": "0x10"
74  },
75  {
76    "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
77    "EventCode": "0x45",
78    "BriefDescription": "L1 DTLB Reload of a page of 1G size.",
79    "PublicDescription": "L1 DTLB Reload of a page of 1G size.",
80    "UMask": "0x8"
81  },
82  {
83    "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
84    "EventCode": "0x45",
85    "BriefDescription": "L1 DTLB Reload of a page of 2M size.",
86    "PublicDescription": "L1 DTLB Reload of a page of 2M size.",
87    "UMask": "0x4"
88  },
89  {
90    "EventName": "ls_l1_d_tlb_miss.tlb_reload_32k_l2_hit",
91    "EventCode": "0x45",
92    "BriefDescription": "L1 DTLB Reload of a page of 32K size.",
93    "PublicDescription": "L1 DTLB Reload of a page of 32K size.",
94    "UMask": "0x2"
95  },
96  {
97    "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
98    "EventCode": "0x45",
99    "BriefDescription": "L1 DTLB Reload of a page of 4K size.",
100    "PublicDescription": "L1 DTLB Reload of a page of 4K size.",
101    "UMask": "0x1"
102  },
103  {
104    "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_iside",
105    "EventCode": "0x46",
106    "BriefDescription": "Tablewalker allocation.",
107    "PublicDescription": "Tablewalker allocation.",
108    "UMask": "0xc"
109  },
110  {
111    "EventName": "ls_tablewalker.perf_mon_tablewalk_alloc_dside",
112    "EventCode": "0x46",
113    "BriefDescription": "Tablewalker allocation.",
114    "PublicDescription": "Tablewalker allocation.",
115    "UMask": "0x3"
116  },
117  {
118    "EventName": "ls_misal_accesses",
119    "EventCode": "0x47",
120    "BriefDescription": "Misaligned loads."
121  },
122  {
123    "EventName": "ls_pref_instr_disp.prefetch_nta",
124    "EventCode": "0x4b",
125    "BriefDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.",
126    "PublicDescription": "Software Prefetch Instructions (PREFETCHNTA instruction) Dispatched.",
127    "UMask": "0x4"
128  },
129  {
130    "EventName": "ls_pref_instr_disp.store_prefetch_w",
131    "EventCode": "0x4b",
132    "BriefDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.",
133    "PublicDescription": "Software Prefetch Instructions (3DNow PREFETCHW instruction) Dispatched.",
134    "UMask": "0x2"
135  },
136  {
137    "EventName": "ls_pref_instr_disp.load_prefetch_w",
138    "EventCode": "0x4b",
139    "BriefDescription": "Prefetch, Prefetch_T0_T1_T2.",
140    "PublicDescription": "Software Prefetch Instructions Dispatched. Prefetch, Prefetch_T0_T1_T2.",
141    "UMask": "0x1"
142  },
143  {
144    "EventName": "ls_inef_sw_pref.mab_mch_cnt",
145    "EventCode": "0x52",
146    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
147    "PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
148    "UMask": "0x2"
149  },
150  {
151    "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
152    "EventCode": "0x52",
153    "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
154    "PublicDescription": "The number of software prefetches that did not fetch data outside of the processor core.",
155    "UMask": "0x1"
156  },
157  {
158    "EventName": "ls_not_halted_cyc",
159    "EventCode": "0x76",
160    "BriefDescription": "Cycles not in Halt."
161  }
162]
163