1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // imx-ssi.c -- ALSA Soc Audio Layer
4 //
5 // Copyright 2009 Sascha Hauer <s.hauer@pengutronix.de>
6 //
7 // This code is based on code copyrighted by Freescale,
8 // Liam Girdwood, Javier Martin and probably others.
9 //
10 // The i.MX SSI core has some nasty limitations in AC97 mode. While most
11 // sane processor vendors have a FIFO per AC97 slot, the i.MX has only
12 // one FIFO which combines all valid receive slots. We cannot even select
13 // which slots we want to receive. The WM9712 with which this driver
14 // was developed with always sends GPIO status data in slot 12 which
15 // we receive in our (PCM-) data stream. The only chance we have is to
16 // manually skip this data in the FIQ handler. With sampling rates different
17 // from 48000Hz not every frame has valid receive data, so the ratio
18 // between pcm data and GPIO status data changes. Our FIQ handler is not
19 // able to handle this, hence this driver only works with 48000Hz sampling
20 // rate.
21 // Reading and writing AC97 registers is another challenge. The core
22 // provides us status bits when the read register is updated with *another*
23 // value. When we read the same register two times (and the register still
24 // contains the same value) these status bits are not set. We work
25 // around this by not polling these bits but only wait a fixed delay.
26
27 #include <linux/clk.h>
28 #include <linux/delay.h>
29 #include <linux/device.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/init.h>
32 #include <linux/interrupt.h>
33 #include <linux/module.h>
34 #include <linux/platform_device.h>
35 #include <linux/slab.h>
36
37 #include <sound/core.h>
38 #include <sound/initval.h>
39 #include <sound/pcm.h>
40 #include <sound/pcm_params.h>
41 #include <sound/soc.h>
42
43 #include <linux/platform_data/asoc-imx-ssi.h>
44
45 #include "imx-ssi.h"
46 #include "fsl_utils.h"
47
48 #define SSI_SACNT_DEFAULT (SSI_SACNT_AC97EN | SSI_SACNT_FV)
49
50 /*
51 * SSI Network Mode or TDM slots configuration.
52 * Should only be called when port is inactive (i.e. SSIEN = 0).
53 */
imx_ssi_set_dai_tdm_slot(struct snd_soc_dai * cpu_dai,unsigned int tx_mask,unsigned int rx_mask,int slots,int slot_width)54 static int imx_ssi_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai,
55 unsigned int tx_mask, unsigned int rx_mask, int slots, int slot_width)
56 {
57 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
58 u32 sccr;
59
60 sccr = readl(ssi->base + SSI_STCCR);
61 sccr &= ~SSI_STCCR_DC_MASK;
62 sccr |= SSI_STCCR_DC(slots - 1);
63 writel(sccr, ssi->base + SSI_STCCR);
64
65 sccr = readl(ssi->base + SSI_SRCCR);
66 sccr &= ~SSI_STCCR_DC_MASK;
67 sccr |= SSI_STCCR_DC(slots - 1);
68 writel(sccr, ssi->base + SSI_SRCCR);
69
70 writel(~tx_mask, ssi->base + SSI_STMSK);
71 writel(~rx_mask, ssi->base + SSI_SRMSK);
72
73 return 0;
74 }
75
76 /*
77 * SSI DAI format configuration.
78 * Should only be called when port is inactive (i.e. SSIEN = 0).
79 */
imx_ssi_set_dai_fmt(struct snd_soc_dai * cpu_dai,unsigned int fmt)80 static int imx_ssi_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
81 {
82 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
83 u32 strcr = 0, scr;
84
85 scr = readl(ssi->base + SSI_SCR) & ~(SSI_SCR_SYN | SSI_SCR_NET);
86
87 /* DAI mode */
88 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
89 case SND_SOC_DAIFMT_I2S:
90 /* data on rising edge of bclk, frame low 1clk before data */
91 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSI |
92 SSI_STCR_TEFS;
93 scr |= SSI_SCR_NET;
94 if (ssi->flags & IMX_SSI_USE_I2S_SLAVE) {
95 scr &= ~SSI_I2S_MODE_MASK;
96 scr |= SSI_SCR_I2S_MODE_SLAVE;
97 }
98 break;
99 case SND_SOC_DAIFMT_LEFT_J:
100 /* data on rising edge of bclk, frame high with data */
101 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP;
102 break;
103 case SND_SOC_DAIFMT_DSP_B:
104 /* data on rising edge of bclk, frame high with data */
105 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSL;
106 break;
107 case SND_SOC_DAIFMT_DSP_A:
108 /* data on rising edge of bclk, frame high 1clk before data */
109 strcr |= SSI_STCR_TXBIT0 | SSI_STCR_TSCKP | SSI_STCR_TFSL |
110 SSI_STCR_TEFS;
111 break;
112 }
113
114 /* DAI clock inversion */
115 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
116 case SND_SOC_DAIFMT_IB_IF:
117 strcr ^= SSI_STCR_TSCKP | SSI_STCR_TFSI;
118 break;
119 case SND_SOC_DAIFMT_IB_NF:
120 strcr ^= SSI_STCR_TSCKP;
121 break;
122 case SND_SOC_DAIFMT_NB_IF:
123 strcr ^= SSI_STCR_TFSI;
124 break;
125 case SND_SOC_DAIFMT_NB_NF:
126 break;
127 }
128
129 /* DAI clock master masks */
130 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
131 case SND_SOC_DAIFMT_CBM_CFM:
132 break;
133 default:
134 /* Master mode not implemented, needs handling of clocks. */
135 return -EINVAL;
136 }
137
138 strcr |= SSI_STCR_TFEN0;
139
140 if (ssi->flags & IMX_SSI_NET)
141 scr |= SSI_SCR_NET;
142 if (ssi->flags & IMX_SSI_SYN)
143 scr |= SSI_SCR_SYN;
144
145 writel(strcr, ssi->base + SSI_STCR);
146 writel(strcr, ssi->base + SSI_SRCR);
147 writel(scr, ssi->base + SSI_SCR);
148
149 return 0;
150 }
151
152 /*
153 * SSI system clock configuration.
154 * Should only be called when port is inactive (i.e. SSIEN = 0).
155 */
imx_ssi_set_dai_sysclk(struct snd_soc_dai * cpu_dai,int clk_id,unsigned int freq,int dir)156 static int imx_ssi_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
157 int clk_id, unsigned int freq, int dir)
158 {
159 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
160 u32 scr;
161
162 scr = readl(ssi->base + SSI_SCR);
163
164 switch (clk_id) {
165 case IMX_SSP_SYS_CLK:
166 if (dir == SND_SOC_CLOCK_OUT)
167 scr |= SSI_SCR_SYS_CLK_EN;
168 else
169 scr &= ~SSI_SCR_SYS_CLK_EN;
170 break;
171 default:
172 return -EINVAL;
173 }
174
175 writel(scr, ssi->base + SSI_SCR);
176
177 return 0;
178 }
179
180 /*
181 * SSI Clock dividers
182 * Should only be called when port is inactive (i.e. SSIEN = 0).
183 */
imx_ssi_set_dai_clkdiv(struct snd_soc_dai * cpu_dai,int div_id,int div)184 static int imx_ssi_set_dai_clkdiv(struct snd_soc_dai *cpu_dai,
185 int div_id, int div)
186 {
187 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
188 u32 stccr, srccr;
189
190 stccr = readl(ssi->base + SSI_STCCR);
191 srccr = readl(ssi->base + SSI_SRCCR);
192
193 switch (div_id) {
194 case IMX_SSI_TX_DIV_2:
195 stccr &= ~SSI_STCCR_DIV2;
196 stccr |= div;
197 break;
198 case IMX_SSI_TX_DIV_PSR:
199 stccr &= ~SSI_STCCR_PSR;
200 stccr |= div;
201 break;
202 case IMX_SSI_TX_DIV_PM:
203 stccr &= ~0xff;
204 stccr |= SSI_STCCR_PM(div);
205 break;
206 case IMX_SSI_RX_DIV_2:
207 stccr &= ~SSI_STCCR_DIV2;
208 stccr |= div;
209 break;
210 case IMX_SSI_RX_DIV_PSR:
211 stccr &= ~SSI_STCCR_PSR;
212 stccr |= div;
213 break;
214 case IMX_SSI_RX_DIV_PM:
215 stccr &= ~0xff;
216 stccr |= SSI_STCCR_PM(div);
217 break;
218 default:
219 return -EINVAL;
220 }
221
222 writel(stccr, ssi->base + SSI_STCCR);
223 writel(srccr, ssi->base + SSI_SRCCR);
224
225 return 0;
226 }
227
228 /*
229 * Should only be called when port is inactive (i.e. SSIEN = 0),
230 * although can be called multiple times by upper layers.
231 */
imx_ssi_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * cpu_dai)232 static int imx_ssi_hw_params(struct snd_pcm_substream *substream,
233 struct snd_pcm_hw_params *params,
234 struct snd_soc_dai *cpu_dai)
235 {
236 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
237 u32 reg, sccr;
238
239 /* Tx/Rx config */
240 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
241 reg = SSI_STCCR;
242 else
243 reg = SSI_SRCCR;
244
245 if (ssi->flags & IMX_SSI_SYN)
246 reg = SSI_STCCR;
247
248 sccr = readl(ssi->base + reg) & ~SSI_STCCR_WL_MASK;
249
250 /* DAI data (word) size */
251 switch (params_format(params)) {
252 case SNDRV_PCM_FORMAT_S16_LE:
253 sccr |= SSI_SRCCR_WL(16);
254 break;
255 case SNDRV_PCM_FORMAT_S20_3LE:
256 sccr |= SSI_SRCCR_WL(20);
257 break;
258 case SNDRV_PCM_FORMAT_S24_LE:
259 sccr |= SSI_SRCCR_WL(24);
260 break;
261 }
262
263 writel(sccr, ssi->base + reg);
264
265 return 0;
266 }
267
imx_ssi_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)268 static int imx_ssi_trigger(struct snd_pcm_substream *substream, int cmd,
269 struct snd_soc_dai *dai)
270 {
271 struct imx_ssi *ssi = snd_soc_dai_get_drvdata(dai);
272 unsigned int sier_bits, sier;
273 unsigned int scr;
274
275 scr = readl(ssi->base + SSI_SCR);
276 sier = readl(ssi->base + SSI_SIER);
277
278 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
279 if (ssi->flags & IMX_SSI_DMA)
280 sier_bits = SSI_SIER_TDMAE;
281 else
282 sier_bits = SSI_SIER_TIE | SSI_SIER_TFE0_EN;
283 } else {
284 if (ssi->flags & IMX_SSI_DMA)
285 sier_bits = SSI_SIER_RDMAE;
286 else
287 sier_bits = SSI_SIER_RIE | SSI_SIER_RFF0_EN;
288 }
289
290 switch (cmd) {
291 case SNDRV_PCM_TRIGGER_START:
292 case SNDRV_PCM_TRIGGER_RESUME:
293 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
294 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
295 scr |= SSI_SCR_TE;
296 else
297 scr |= SSI_SCR_RE;
298 sier |= sier_bits;
299
300 scr |= SSI_SCR_SSIEN;
301
302 break;
303
304 case SNDRV_PCM_TRIGGER_STOP:
305 case SNDRV_PCM_TRIGGER_SUSPEND:
306 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
307 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
308 scr &= ~SSI_SCR_TE;
309 else
310 scr &= ~SSI_SCR_RE;
311 sier &= ~sier_bits;
312
313 if (!(scr & (SSI_SCR_TE | SSI_SCR_RE)))
314 scr &= ~SSI_SCR_SSIEN;
315
316 break;
317 default:
318 return -EINVAL;
319 }
320
321 if (!(ssi->flags & IMX_SSI_USE_AC97))
322 /* rx/tx are always enabled to access ac97 registers */
323 writel(scr, ssi->base + SSI_SCR);
324
325 writel(sier, ssi->base + SSI_SIER);
326
327 return 0;
328 }
329
330 static const struct snd_soc_dai_ops imx_ssi_pcm_dai_ops = {
331 .hw_params = imx_ssi_hw_params,
332 .set_fmt = imx_ssi_set_dai_fmt,
333 .set_clkdiv = imx_ssi_set_dai_clkdiv,
334 .set_sysclk = imx_ssi_set_dai_sysclk,
335 .set_tdm_slot = imx_ssi_set_dai_tdm_slot,
336 .trigger = imx_ssi_trigger,
337 };
338
imx_ssi_dai_probe(struct snd_soc_dai * dai)339 static int imx_ssi_dai_probe(struct snd_soc_dai *dai)
340 {
341 struct imx_ssi *ssi = dev_get_drvdata(dai->dev);
342 uint32_t val;
343
344 snd_soc_dai_set_drvdata(dai, ssi);
345
346 val = SSI_SFCSR_TFWM0(ssi->dma_params_tx.maxburst) |
347 SSI_SFCSR_RFWM0(ssi->dma_params_rx.maxburst);
348 writel(val, ssi->base + SSI_SFCSR);
349
350 /* Tx/Rx config */
351 dai->playback_dma_data = &ssi->dma_params_tx;
352 dai->capture_dma_data = &ssi->dma_params_rx;
353
354 return 0;
355 }
356
357 static struct snd_soc_dai_driver imx_ssi_dai = {
358 .probe = imx_ssi_dai_probe,
359 .playback = {
360 .channels_min = 1,
361 .channels_max = 2,
362 .rates = SNDRV_PCM_RATE_8000_96000,
363 .formats = SNDRV_PCM_FMTBIT_S16_LE,
364 },
365 .capture = {
366 .channels_min = 1,
367 .channels_max = 2,
368 .rates = SNDRV_PCM_RATE_8000_96000,
369 .formats = SNDRV_PCM_FMTBIT_S16_LE,
370 },
371 .ops = &imx_ssi_pcm_dai_ops,
372 };
373
374 static struct snd_soc_dai_driver imx_ac97_dai = {
375 .probe = imx_ssi_dai_probe,
376 .bus_control = true,
377 .playback = {
378 .stream_name = "AC97 Playback",
379 .channels_min = 2,
380 .channels_max = 2,
381 .rates = SNDRV_PCM_RATE_8000_48000,
382 .formats = SNDRV_PCM_FMTBIT_S16_LE,
383 },
384 .capture = {
385 .stream_name = "AC97 Capture",
386 .channels_min = 2,
387 .channels_max = 2,
388 .rates = SNDRV_PCM_RATE_48000,
389 .formats = SNDRV_PCM_FMTBIT_S16_LE,
390 },
391 .ops = &imx_ssi_pcm_dai_ops,
392 };
393
394 static const struct snd_soc_component_driver imx_component = {
395 .name = DRV_NAME,
396 };
397
setup_channel_to_ac97(struct imx_ssi * imx_ssi)398 static void setup_channel_to_ac97(struct imx_ssi *imx_ssi)
399 {
400 void __iomem *base = imx_ssi->base;
401
402 writel(0x0, base + SSI_SCR);
403 writel(0x0, base + SSI_STCR);
404 writel(0x0, base + SSI_SRCR);
405
406 writel(SSI_SCR_SYN | SSI_SCR_NET, base + SSI_SCR);
407
408 writel(SSI_SFCSR_RFWM0(8) |
409 SSI_SFCSR_TFWM0(8) |
410 SSI_SFCSR_RFWM1(8) |
411 SSI_SFCSR_TFWM1(8), base + SSI_SFCSR);
412
413 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_STCCR);
414 writel(SSI_STCCR_WL(16) | SSI_STCCR_DC(12), base + SSI_SRCCR);
415
416 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN, base + SSI_SCR);
417 writel(SSI_SOR_WAIT(3), base + SSI_SOR);
418
419 writel(SSI_SCR_SYN | SSI_SCR_NET | SSI_SCR_SSIEN |
420 SSI_SCR_TE | SSI_SCR_RE,
421 base + SSI_SCR);
422
423 writel(SSI_SACNT_DEFAULT, base + SSI_SACNT);
424 writel(0xff, base + SSI_SACCDIS);
425 writel(0x300, base + SSI_SACCEN);
426 }
427
428 static struct imx_ssi *ac97_ssi;
429
imx_ssi_ac97_write(struct snd_ac97 * ac97,unsigned short reg,unsigned short val)430 static void imx_ssi_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
431 unsigned short val)
432 {
433 struct imx_ssi *imx_ssi = ac97_ssi;
434 void __iomem *base = imx_ssi->base;
435 unsigned int lreg;
436 unsigned int lval;
437
438 if (reg > 0x7f)
439 return;
440
441 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
442
443 lreg = reg << 12;
444 writel(lreg, base + SSI_SACADD);
445
446 lval = val << 4;
447 writel(lval , base + SSI_SACDAT);
448
449 writel(SSI_SACNT_DEFAULT | SSI_SACNT_WR, base + SSI_SACNT);
450 udelay(100);
451 }
452
imx_ssi_ac97_read(struct snd_ac97 * ac97,unsigned short reg)453 static unsigned short imx_ssi_ac97_read(struct snd_ac97 *ac97,
454 unsigned short reg)
455 {
456 struct imx_ssi *imx_ssi = ac97_ssi;
457 void __iomem *base = imx_ssi->base;
458
459 unsigned short val = -1;
460 unsigned int lreg;
461
462 lreg = (reg & 0x7f) << 12 ;
463 writel(lreg, base + SSI_SACADD);
464 writel(SSI_SACNT_DEFAULT | SSI_SACNT_RD, base + SSI_SACNT);
465
466 udelay(100);
467
468 val = (readl(base + SSI_SACDAT) >> 4) & 0xffff;
469
470 pr_debug("%s: 0x%02x 0x%04x\n", __func__, reg, val);
471
472 return val;
473 }
474
imx_ssi_ac97_reset(struct snd_ac97 * ac97)475 static void imx_ssi_ac97_reset(struct snd_ac97 *ac97)
476 {
477 struct imx_ssi *imx_ssi = ac97_ssi;
478
479 if (imx_ssi->ac97_reset)
480 imx_ssi->ac97_reset(ac97);
481 /* First read sometimes fails, do a dummy read */
482 imx_ssi_ac97_read(ac97, 0);
483 }
484
imx_ssi_ac97_warm_reset(struct snd_ac97 * ac97)485 static void imx_ssi_ac97_warm_reset(struct snd_ac97 *ac97)
486 {
487 struct imx_ssi *imx_ssi = ac97_ssi;
488
489 if (imx_ssi->ac97_warm_reset)
490 imx_ssi->ac97_warm_reset(ac97);
491
492 /* First read sometimes fails, do a dummy read */
493 imx_ssi_ac97_read(ac97, 0);
494 }
495
496 static struct snd_ac97_bus_ops imx_ssi_ac97_ops = {
497 .read = imx_ssi_ac97_read,
498 .write = imx_ssi_ac97_write,
499 .reset = imx_ssi_ac97_reset,
500 .warm_reset = imx_ssi_ac97_warm_reset
501 };
502
imx_ssi_probe(struct platform_device * pdev)503 static int imx_ssi_probe(struct platform_device *pdev)
504 {
505 struct resource *res;
506 struct imx_ssi *ssi;
507 struct imx_ssi_platform_data *pdata = pdev->dev.platform_data;
508 int ret = 0;
509 struct snd_soc_dai_driver *dai;
510
511 ssi = devm_kzalloc(&pdev->dev, sizeof(*ssi), GFP_KERNEL);
512 if (!ssi)
513 return -ENOMEM;
514 dev_set_drvdata(&pdev->dev, ssi);
515
516 if (pdata) {
517 ssi->ac97_reset = pdata->ac97_reset;
518 ssi->ac97_warm_reset = pdata->ac97_warm_reset;
519 ssi->flags = pdata->flags;
520 }
521
522 ssi->irq = platform_get_irq(pdev, 0);
523 if (ssi->irq < 0)
524 return ssi->irq;
525
526 ssi->clk = devm_clk_get(&pdev->dev, NULL);
527 if (IS_ERR(ssi->clk)) {
528 ret = PTR_ERR(ssi->clk);
529 dev_err(&pdev->dev, "Cannot get the clock: %d\n",
530 ret);
531 goto failed_clk;
532 }
533 ret = clk_prepare_enable(ssi->clk);
534 if (ret)
535 goto failed_clk;
536
537 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
538 ssi->base = devm_ioremap_resource(&pdev->dev, res);
539 if (IS_ERR(ssi->base)) {
540 ret = PTR_ERR(ssi->base);
541 goto failed_register;
542 }
543
544 if (ssi->flags & IMX_SSI_USE_AC97) {
545 if (ac97_ssi) {
546 dev_err(&pdev->dev, "AC'97 SSI already registered\n");
547 ret = -EBUSY;
548 goto failed_register;
549 }
550 ac97_ssi = ssi;
551 setup_channel_to_ac97(ssi);
552 dai = &imx_ac97_dai;
553 } else
554 dai = &imx_ssi_dai;
555
556 writel(0x0, ssi->base + SSI_SIER);
557
558 ssi->dma_params_rx.addr = res->start + SSI_SRX0;
559 ssi->dma_params_tx.addr = res->start + SSI_STX0;
560
561 ssi->dma_params_tx.maxburst = 6;
562 ssi->dma_params_rx.maxburst = 4;
563
564 ssi->dma_params_tx.filter_data = &ssi->filter_data_tx;
565 ssi->dma_params_rx.filter_data = &ssi->filter_data_rx;
566
567 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx0");
568 if (res) {
569 imx_pcm_dma_params_init_data(&ssi->filter_data_tx, res->start,
570 IMX_DMATYPE_SSI);
571 }
572
573 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx0");
574 if (res) {
575 imx_pcm_dma_params_init_data(&ssi->filter_data_rx, res->start,
576 IMX_DMATYPE_SSI);
577 }
578
579 platform_set_drvdata(pdev, ssi);
580
581 ret = snd_soc_set_ac97_ops(&imx_ssi_ac97_ops);
582 if (ret != 0) {
583 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
584 goto failed_register;
585 }
586
587 ret = snd_soc_register_component(&pdev->dev, &imx_component,
588 dai, 1);
589 if (ret) {
590 dev_err(&pdev->dev, "register DAI failed\n");
591 goto failed_register;
592 }
593
594 ssi->fiq_params.irq = ssi->irq;
595 ssi->fiq_params.base = ssi->base;
596 ssi->fiq_params.dma_params_rx = &ssi->dma_params_rx;
597 ssi->fiq_params.dma_params_tx = &ssi->dma_params_tx;
598
599 ssi->fiq_init = imx_pcm_fiq_init(pdev, &ssi->fiq_params);
600 ssi->dma_init = imx_pcm_dma_init(pdev, IMX_SSI_DMABUF_SIZE);
601
602 if (ssi->fiq_init && ssi->dma_init) {
603 ret = ssi->fiq_init;
604 goto failed_pcm;
605 }
606
607 return 0;
608
609 failed_pcm:
610 snd_soc_unregister_component(&pdev->dev);
611 failed_register:
612 clk_disable_unprepare(ssi->clk);
613 failed_clk:
614 snd_soc_set_ac97_ops(NULL);
615
616 return ret;
617 }
618
imx_ssi_remove(struct platform_device * pdev)619 static int imx_ssi_remove(struct platform_device *pdev)
620 {
621 struct imx_ssi *ssi = platform_get_drvdata(pdev);
622
623 if (!ssi->fiq_init)
624 imx_pcm_fiq_exit(pdev);
625
626 snd_soc_unregister_component(&pdev->dev);
627
628 if (ssi->flags & IMX_SSI_USE_AC97)
629 ac97_ssi = NULL;
630
631 clk_disable_unprepare(ssi->clk);
632 snd_soc_set_ac97_ops(NULL);
633
634 return 0;
635 }
636
637 static struct platform_driver imx_ssi_driver = {
638 .probe = imx_ssi_probe,
639 .remove = imx_ssi_remove,
640
641 .driver = {
642 .name = "imx-ssi",
643 },
644 };
645
646 module_platform_driver(imx_ssi_driver);
647
648 /* Module information */
649 MODULE_AUTHOR("Sascha Hauer, <s.hauer@pengutronix.de>");
650 MODULE_DESCRIPTION("i.MX I2S/ac97 SoC Interface");
651 MODULE_LICENSE("GPL");
652 MODULE_ALIAS("platform:imx-ssi");
653
