1/*
2 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
3 *
4 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
5 * Freescale Semiconductor, Inc.
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 *  a) This file is free software; you can redistribute it and/or
13 *     modify it under the terms of the GNU General Public License
14 *     version 2 as published by the Free Software Foundation.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include "vf610.dtsi"
46
47/ {
48	chosen {
49		stdout-path = "serial0:115200n8";
50	};
51
52	memory@80000000 {
53		device_type = "memory";
54		reg = <0x80000000 0x20000000>;
55	};
56
57	gpio-leds {
58		compatible = "gpio-leds";
59		pinctrl-0 = <&pinctrl_leds_debug>;
60		pinctrl-names = "default";
61
62		debug {
63			label = "zii:green:debug1";
64			gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
65			linux,default-trigger = "heartbeat";
66		};
67	};
68
69	reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
70		compatible = "regulator-fixed";
71		regulator-name = "vcc_3v3_mcu";
72		regulator-min-microvolt = <3300000>;
73		regulator-max-microvolt = <3300000>;
74	};
75
76	usb0_vbus: regulator-usb0-vbus {
77		compatible = "regulator-fixed";
78		pinctrl-0 = <&pinctrl_usb_vbus>;
79		regulator-name = "usb_vbus";
80		regulator-min-microvolt = <5000000>;
81		regulator-max-microvolt = <5000000>;
82		enable-active-high;
83		regulator-always-on;
84		regulator-boot-on;
85		gpio = <&gpio0 6 0>;
86	};
87};
88
89&adc0 {
90	pinctrl-names = "default";
91	pinctrl-0 = <&pinctrl_adc0_ad5>;
92	vref-supply = <&reg_vcc_3v3_mcu>;
93	status = "okay";
94};
95
96&edma0 {
97	status = "okay";
98};
99
100&edma1 {
101	status = "okay";
102};
103
104&esdhc1 {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_esdhc1>;
107	bus-width = <4>;
108	status = "okay";
109};
110
111&fec0 {
112	phy-mode = "rmii";
113	pinctrl-names = "default";
114	pinctrl-0 = <&pinctrl_fec0>;
115	status = "okay";
116};
117
118&fec1 {
119	phy-mode = "rmii";
120	pinctrl-names = "default";
121	pinctrl-0 = <&pinctrl_fec1>;
122	status = "okay";
123
124	fixed-link {
125		   speed = <100>;
126		   full-duplex;
127	};
128
129	mdio1: mdio {
130		#address-cells = <1>;
131		#size-cells = <0>;
132		status = "okay";
133	};
134};
135
136&i2c0 {
137	clock-frequency = <100000>;
138	pinctrl-names = "default", "gpio";
139	pinctrl-0 = <&pinctrl_i2c0>;
140	pinctrl-1 = <&pinctrl_i2c0_gpio>;
141	scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
142	sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
143	status = "okay";
144
145	lm75@48 {
146		compatible = "national,lm75";
147		reg = <0x48>;
148	};
149
150	eeprom@50 {
151		compatible = "atmel,24c04";
152		reg = <0x50>;
153	};
154
155	eeprom@52 {
156		compatible = "atmel,24c04";
157		reg = <0x52>;
158	};
159
160	ds1682@6b {
161		compatible = "dallas,ds1682";
162		reg = <0x6b>;
163	};
164};
165
166&i2c1 {
167	clock-frequency = <100000>;
168	pinctrl-names = "default";
169	pinctrl-0 = <&pinctrl_i2c1>;
170	status = "okay";
171};
172
173&i2c2 {
174	clock-frequency = <100000>;
175	pinctrl-names = "default";
176	pinctrl-0 = <&pinctrl_i2c2>;
177	status = "okay";
178};
179
180&qspi0 {
181	pinctrl-names = "default";
182	pinctrl-0 = <&pinctrl_qspi0>;
183	status = "okay";
184
185	/*
186	 * Attached MT25QL02 can go up to 90Mhz in DTR and 166 in STR
187	 * modes, so, spi-max-frequency is limited to 90MHz
188	 */
189	flash@0 {
190		compatible = "jedec,spi-nor";
191		#address-cells = <1>;
192		#size-cells = <1>;
193		spi-max-frequency = <90000000>;
194		spi-rx-bus-width = <4>;
195		reg = <0>;
196		m25p,fast-read;
197	};
198
199	flash@2 {
200		compatible = "jedec,spi-nor";
201		#address-cells = <1>;
202		#size-cells = <1>;
203		spi-max-frequency = <90000000>;
204		spi-rx-bus-width = <4>;
205		reg = <2>;
206		m25p,fast-read;
207	};
208};
209
210&uart0 {
211	pinctrl-names = "default";
212	pinctrl-0 = <&pinctrl_uart0>;
213	status = "okay";
214};
215
216&uart1 {
217	pinctrl-names = "default";
218	pinctrl-0 = <&pinctrl_uart1>;
219	status = "okay";
220};
221
222&uart2 {
223	pinctrl-names = "default";
224	pinctrl-0 = <&pinctrl_uart2>;
225	status = "okay";
226};
227
228&usbdev0 {
229	disable-over-current;
230	vbus-supply = <&usb0_vbus>;
231	dr_mode = "host";
232	status = "okay";
233};
234
235&usbh1 {
236	disable-over-current;
237	status = "okay";
238};
239
240&usbmisc0 {
241	status = "okay";
242};
243
244&usbmisc1 {
245	status = "okay";
246};
247
248&usbphy0 {
249	status = "okay";
250};
251
252&usbphy1 {
253	status = "okay";
254};
255
256&tempsensor {
257	io-channels = <&adc0 16>;
258};
259
260&iomuxc {
261	pinctrl_adc0_ad5: adc0ad5grp {
262		fsl,pins = <
263			VF610_PAD_PTC30__ADC0_SE5	0x00a1
264		>;
265	};
266
267	pinctrl_dspi0: dspi0grp {
268		fsl,pins = <
269			VF610_PAD_PTB18__DSPI0_CS1	0x1182
270			VF610_PAD_PTB19__DSPI0_CS0	0x1182
271			VF610_PAD_PTB20__DSPI0_SIN	0x1181
272			VF610_PAD_PTB21__DSPI0_SOUT	0x1182
273			VF610_PAD_PTB22__DSPI0_SCK	0x1182
274		>;
275	};
276
277	pinctrl_dspi2: dspi2grp {
278		fsl,pins = <
279			VF610_PAD_PTD31__DSPI2_CS1	0x1182
280			VF610_PAD_PTD30__DSPI2_CS0	0x1182
281			VF610_PAD_PTD29__DSPI2_SIN	0x1181
282			VF610_PAD_PTD28__DSPI2_SOUT	0x1182
283			VF610_PAD_PTD27__DSPI2_SCK	0x1182
284		>;
285	};
286
287	pinctrl_esdhc1: esdhc1grp {
288		fsl,pins = <
289			VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
290			VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
291			VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
292			VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
293			VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
294			VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
295			VF610_PAD_PTA7__GPIO_134	0x219d
296		>;
297	};
298
299	pinctrl_fec0: fec0grp {
300		fsl,pins = <
301			VF610_PAD_PTC0__ENET_RMII0_MDC	0x30d2
302			VF610_PAD_PTC1__ENET_RMII0_MDIO	0x30d3
303			VF610_PAD_PTC2__ENET_RMII0_CRS	0x30d1
304			VF610_PAD_PTC3__ENET_RMII0_RXD1	0x30d1
305			VF610_PAD_PTC4__ENET_RMII0_RXD0	0x30d1
306			VF610_PAD_PTC5__ENET_RMII0_RXER	0x30d1
307			VF610_PAD_PTC6__ENET_RMII0_TXD1	0x30d2
308			VF610_PAD_PTC7__ENET_RMII0_TXD0	0x30d2
309			VF610_PAD_PTC8__ENET_RMII0_TXEN	0x30d2
310		>;
311	};
312
313	pinctrl_fec1: fec1grp {
314		fsl,pins = <
315			VF610_PAD_PTA6__RMII_CLKIN		0x30d1
316			VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
317			VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
318			VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
319			VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
320			VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
321			VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
322			VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
323			VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
324			VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
325		>;
326	};
327
328	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
329		fsl,pins = <
330			VF610_PAD_PTB22__GPIO_44	0x33e2
331			VF610_PAD_PTB21__GPIO_43	0x33e2
332			VF610_PAD_PTB20__GPIO_42	0x33e1
333			VF610_PAD_PTB19__GPIO_41	0x33e2
334			VF610_PAD_PTB18__GPIO_40	0x33e2
335		>;
336	};
337
338	pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
339		fsl,pins = <
340			VF610_PAD_PTB5__GPIO_27		0x219d
341		>;
342	};
343
344	pinctrl_gpio_switch1: pinctrl-gpio-switch1 {
345		fsl,pins = <
346			VF610_PAD_PTB4__GPIO_26		0x219d
347		>;
348	};
349
350	pinctrl_i2c_mux_reset: pinctrl-i2c-mux-reset {
351		fsl,pins = <
352			 VF610_PAD_PTE14__GPIO_119	0x31c2
353			 >;
354	};
355
356	pinctrl_i2c0: i2c0grp {
357		fsl,pins = <
358			VF610_PAD_PTB14__I2C0_SCL	0x37ff
359			VF610_PAD_PTB15__I2C0_SDA	0x37ff
360		>;
361	};
362
363	pinctrl_i2c0_gpio: i2c0grp-gpio {
364		fsl,pins = <
365			VF610_PAD_PTB14__GPIO_36	0x31c2
366			VF610_PAD_PTB15__GPIO_37	0x31c2
367		>;
368	};
369
370
371	pinctrl_i2c1: i2c1grp {
372		fsl,pins = <
373			VF610_PAD_PTB16__I2C1_SCL	0x37ff
374			VF610_PAD_PTB17__I2C1_SDA	0x37ff
375		>;
376	};
377
378	pinctrl_i2c2: i2c2grp {
379		fsl,pins = <
380			VF610_PAD_PTA22__I2C2_SCL	0x37ff
381			VF610_PAD_PTA23__I2C2_SDA	0x37ff
382		>;
383	};
384
385	pinctrl_leds_debug: pinctrl-leds-debug {
386		fsl,pins = <
387			 VF610_PAD_PTD20__GPIO_74	0x31c2
388			 >;
389	};
390
391	pinctrl_qspi0: qspi0grp {
392		fsl,pins = <
393			VF610_PAD_PTD0__QSPI0_A_QSCK	0x38c2
394			VF610_PAD_PTD1__QSPI0_A_CS0	0x38c2
395			VF610_PAD_PTD2__QSPI0_A_DATA3	0x38c3
396			VF610_PAD_PTD3__QSPI0_A_DATA2	0x38c3
397			VF610_PAD_PTD4__QSPI0_A_DATA1	0x38c3
398			VF610_PAD_PTD5__QSPI0_A_DATA0	0x38c3
399			VF610_PAD_PTD7__QSPI0_B_QSCK	0x38c2
400			VF610_PAD_PTD8__QSPI0_B_CS0	0x38c2
401			VF610_PAD_PTD9__QSPI0_B_DATA3	0x38c3
402			VF610_PAD_PTD10__QSPI0_B_DATA2	0x38c3
403			VF610_PAD_PTD11__QSPI0_B_DATA1	0x38c3
404			VF610_PAD_PTD12__QSPI0_B_DATA0	0x38c3
405		>;
406	};
407
408	pinctrl_uart0: uart0grp {
409		fsl,pins = <
410			VF610_PAD_PTB10__UART0_TX	0x21a2
411			VF610_PAD_PTB11__UART0_RX	0x21a1
412		>;
413	};
414
415	pinctrl_uart1: uart1grp {
416		fsl,pins = <
417			VF610_PAD_PTB23__UART1_TX	0x21a2
418			VF610_PAD_PTB24__UART1_RX	0x21a1
419		>;
420	};
421
422	pinctrl_uart2: uart2grp {
423		fsl,pins = <
424			VF610_PAD_PTD23__UART2_TX	0x21a2
425			VF610_PAD_PTD22__UART2_RX	0x21a1
426		>;
427	};
428
429	pinctrl_usb_vbus: pinctrl-usb-vbus {
430		fsl,pins = <
431			VF610_PAD_PTA16__GPIO_6	0x31c2
432		>;
433	};
434
435	pinctrl_usb0_host: usb0-host-grp {
436		fsl,pins = <
437			VF610_PAD_PTD6__GPIO_85		0x0062
438		>;
439	};
440};
441