1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
4 */
5
6/dts-v1/;
7#include "vf610-zii-dev.dtsi"
8
9/ {
10	model = "ZII VF610 Development Board, Rev B";
11	compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
12
13	mdio-mux {
14		compatible = "mdio-mux-gpio";
15		pinctrl-0 = <&pinctrl_mdio_mux>;
16		pinctrl-names = "default";
17		gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
18			 &gpio0 9  GPIO_ACTIVE_HIGH
19			 &gpio0 24 GPIO_ACTIVE_HIGH
20			 &gpio0 25 GPIO_ACTIVE_HIGH>;
21		mdio-parent-bus = <&mdio1>;
22		#address-cells = <1>;
23		#size-cells = <0>;
24
25		mdio_mux_1: mdio@1 {
26			reg = <1>;
27			#address-cells = <1>;
28			#size-cells = <0>;
29
30			switch0: switch@0 {
31				compatible = "marvell,mv88e6085";
32				pinctrl-0 = <&pinctrl_gpio_switch0>;
33				pinctrl-names = "default";
34				reg = <0>;
35				dsa,member = <0 0>;
36				interrupt-parent = <&gpio0>;
37				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
38				interrupt-controller;
39				#interrupt-cells = <2>;
40				eeprom-length = <512>;
41
42				ports {
43					#address-cells = <1>;
44					#size-cells = <0>;
45
46					port@0 {
47						reg = <0>;
48						label = "lan0";
49						phy-handle = <&switch0phy0>;
50					};
51
52					port@1 {
53						reg = <1>;
54						label = "lan1";
55						phy-handle = <&switch0phy1>;
56					};
57
58					port@2 {
59						reg = <2>;
60						label = "lan2";
61						phy-handle = <&switch0phy2>;
62					};
63
64					switch0port5: port@5 {
65						reg = <5>;
66						label = "dsa";
67						phy-mode = "rgmii-txid";
68						link = <&switch1port6
69							&switch2port9>;
70						fixed-link {
71							speed = <1000>;
72							full-duplex;
73						};
74					};
75
76					port@6 {
77						reg = <6>;
78						label = "cpu";
79						ethernet = <&fec1>;
80
81						fixed-link {
82							speed = <100>;
83							full-duplex;
84						};
85					};
86				};
87				mdio {
88					#address-cells = <1>;
89					#size-cells = <0>;
90					switch0phy0: switch0phy0@0 {
91						reg = <0>;
92						interrupt-parent = <&switch0>;
93						interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
94					};
95					switch0phy1: switch1phy0@1 {
96						reg = <1>;
97						interrupt-parent = <&switch0>;
98						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
99					};
100					switch0phy2: switch1phy0@2 {
101						reg = <2>;
102						interrupt-parent = <&switch0>;
103						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
104					};
105				};
106			};
107		};
108
109		mdio_mux_2: mdio@2 {
110			reg = <2>;
111			#address-cells = <1>;
112			#size-cells = <0>;
113
114			switch1: switch@0 {
115				compatible = "marvell,mv88e6085";
116				pinctrl-0 = <&pinctrl_gpio_switch1>;
117				pinctrl-names = "default";
118				reg = <0>;
119				dsa,member = <0 1>;
120				interrupt-parent = <&gpio0>;
121				interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
122				interrupt-controller;
123				#interrupt-cells = <2>;
124				eeprom-length = <512>;
125
126				ports {
127					#address-cells = <1>;
128					#size-cells = <0>;
129
130					port@0 {
131						reg = <0>;
132						label = "lan3";
133						phy-handle = <&switch1phy0>;
134					};
135
136					port@1 {
137						reg = <1>;
138						label = "lan4";
139						phy-handle = <&switch1phy1>;
140					};
141
142					port@2 {
143						reg = <2>;
144						label = "lan5";
145						phy-handle = <&switch1phy2>;
146					};
147
148					switch1port5: port@5 {
149						reg = <5>;
150						label = "dsa";
151						link = <&switch2port9>;
152						phy-mode = "rgmii-txid";
153
154						fixed-link {
155							speed = <1000>;
156							full-duplex;
157						};
158					};
159
160					switch1port6: port@6 {
161						reg = <6>;
162						label = "dsa";
163						phy-mode = "rgmii-txid";
164						link = <&switch0port5>;
165						fixed-link {
166							speed = <1000>;
167							full-duplex;
168						};
169					};
170				};
171				mdio {
172					#address-cells = <1>;
173					#size-cells = <0>;
174
175					switch1phy0: switch1phy0@0 {
176						reg = <0>;
177						interrupt-parent = <&switch1>;
178						interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
179					};
180
181					switch1phy1: switch1phy0@1 {
182						reg = <1>;
183						interrupt-parent = <&switch1>;
184						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
185					};
186
187					switch1phy2: switch1phy0@2 {
188						reg = <2>;
189						interrupt-parent = <&switch1>;
190						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
191					};
192				};
193			};
194		};
195
196		mdio_mux_4: mdio@4 {
197			#address-cells = <1>;
198			#size-cells = <0>;
199			reg = <4>;
200
201			switch2: switch@0 {
202				compatible = "marvell,mv88e6085";
203				reg = <0>;
204				dsa,member = <0 2>;
205
206				ports {
207					#address-cells = <1>;
208					#size-cells = <0>;
209
210					port@0 {
211						reg = <0>;
212						label = "lan6";
213						phy-handle = <&switch2phy0>;
214					};
215
216					port@1 {
217						reg = <1>;
218						label = "lan7";
219						phy-handle = <&switch2phy1>;
220					};
221
222					port@2 {
223						reg = <2>;
224						label = "lan8";
225						phy-handle = <&switch2phy2>;
226					};
227
228					port@3 {
229						reg = <3>;
230						label = "optical3";
231
232						fixed-link {
233							speed = <1000>;
234							full-duplex;
235							link-gpios = <&gpio6 2
236							      GPIO_ACTIVE_HIGH>;
237						};
238					};
239
240					port@4 {
241						reg = <4>;
242						label = "optical4";
243
244						fixed-link {
245							speed = <1000>;
246							full-duplex;
247							link-gpios = <&gpio6 3
248							      GPIO_ACTIVE_HIGH>;
249						};
250					};
251
252					switch2port9: port@9 {
253						reg = <9>;
254						label = "dsa";
255						phy-mode = "rgmii-txid";
256						link = <&switch1port5
257							&switch0port5>;
258
259						fixed-link {
260							speed = <1000>;
261							full-duplex;
262						};
263					};
264				};
265				mdio {
266					#address-cells = <1>;
267					#size-cells = <0>;
268
269					switch2phy0: phy@0 {
270						reg = <0>;
271					};
272					switch2phy1: phy@1 {
273						reg = <1>;
274					};
275					switch2phy2: phy@2 {
276						reg = <2>;
277					};
278				};
279			};
280		};
281
282		mdio_mux_8: mdio@8 {
283			reg = <8>;
284			#address-cells = <1>;
285			#size-cells = <0>;
286		};
287	};
288
289	spi0 {
290		compatible = "spi-gpio";
291		pinctrl-0 = <&pinctrl_gpio_spi0>;
292		pinctrl-names = "default";
293		#address-cells = <1>;
294		#size-cells = <0>;
295		gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
296		gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
297		gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
298		cs-gpios  = <&gpio1  9 GPIO_ACTIVE_LOW
299			     &gpio1  8 GPIO_ACTIVE_HIGH>;
300		num-chipselects = <2>;
301
302		flash@0 {
303			compatible = "m25p128", "jedec,spi-nor";
304			#address-cells = <1>;
305			#size-cells = <1>;
306			reg = <0>;
307			spi-max-frequency = <1000000>;
308		};
309
310		at93c46d@1 {
311			compatible = "atmel,at93c46d";
312			pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
313			pinctrl-names = "default";
314			#address-cells = <0>;
315			#size-cells = <0>;
316			reg = <1>;
317			spi-max-frequency = <500000>;
318			spi-cs-high;
319			data-size = <16>;
320			select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
321		};
322	};
323};
324
325&i2c0 {
326	clock-frequency = <100000>;
327	pinctrl-names = "default";
328	pinctrl-0 = <&pinctrl_i2c0>;
329	status = "okay";
330
331	gpio5: io-expander@20 {
332		compatible = "nxp,pca9554";
333		reg = <0x20>;
334		gpio-controller;
335		#gpio-cells = <2>;
336
337	};
338
339	gpio6: io-expander@22 {
340		compatible = "nxp,pca9554";
341		pinctrl-names = "default";
342		pinctrl-0 = <&pinctrl_pca9554_22>;
343		reg = <0x22>;
344		gpio-controller;
345		#gpio-cells = <2>;
346		interrupt-controller;
347		interrupt-parent = <&gpio3>;
348		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
349	};
350};
351
352&i2c2 {
353	clock-frequency = <100000>;
354	pinctrl-names = "default";
355	pinctrl-0 = <&pinctrl_i2c2>;
356	status = "okay";
357
358	tca9548@70 {
359		compatible = "nxp,pca9548";
360		pinctrl-0 = <&pinctrl_i2c_mux_reset>;
361		pinctrl-names = "default";
362		#address-cells = <1>;
363		#size-cells = <0>;
364		reg = <0x70>;
365		reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
366
367		i2c@0 {
368			#address-cells = <1>;
369			#size-cells = <0>;
370			reg = <0>;
371
372			sfp1: eeprom@50 {
373				compatible = "atmel,24c02";
374				reg = <0x50>;
375			};
376		};
377
378		i2c@1 {
379			#address-cells = <1>;
380			#size-cells = <0>;
381			reg = <1>;
382
383			sfp2: eeprom@50 {
384				compatible = "atmel,24c02";
385				reg = <0x50>;
386			};
387		};
388
389		i2c@2 {
390			#address-cells = <1>;
391			#size-cells = <0>;
392			reg = <2>;
393
394			sfp3: eeprom@50 {
395				compatible = "atmel,24c02";
396				reg = <0x50>;
397			};
398		};
399
400		i2c@3 {
401			#address-cells = <1>;
402			#size-cells = <0>;
403			reg = <3>;
404
405			sfp4: eeprom@50 {
406				compatible = "atmel,24c02";
407				reg = <0x50>;
408			};
409		};
410
411		i2c@4 {
412			#address-cells = <1>;
413			#size-cells = <0>;
414			reg = <4>;
415		};
416	};
417};
418
419
420&iomuxc {
421	pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
422		fsl,pins = <
423			VF610_PAD_PTE27__GPIO_132	0x33e2
424		>;
425	};
426
427	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
428		fsl,pins = <
429			VF610_PAD_PTB22__GPIO_44	0x33e2
430			VF610_PAD_PTB21__GPIO_43	0x33e2
431			VF610_PAD_PTB20__GPIO_42	0x33e1
432			VF610_PAD_PTB19__GPIO_41	0x33e2
433			VF610_PAD_PTB18__GPIO_40	0x33e2
434		>;
435	};
436
437	pinctrl_mdio_mux: pinctrl-mdio-mux {
438		fsl,pins = <
439			VF610_PAD_PTA18__GPIO_8		0x31c2
440			VF610_PAD_PTA19__GPIO_9		0x31c2
441			VF610_PAD_PTB2__GPIO_24		0x31c2
442			VF610_PAD_PTB3__GPIO_25		0x31c2
443		>;
444	};
445
446	pinctrl_pca9554_22: pinctrl-pca95540-22 {
447		fsl,pins = <
448			VF610_PAD_PTB28__GPIO_98	0x219d
449		>;
450	};
451};
452