1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/input.h>
5#include "tegra20.dtsi"
6
7/ {
8	model = "NVIDIA Tegra20 Ventana evaluation board";
9	compatible = "nvidia,ventana", "nvidia,tegra20";
10
11	aliases {
12		rtc0 = "/i2c@7000d000/tps6586x@34";
13		rtc1 = "/rtc@7000e000";
14		serial0 = &uartd;
15	};
16
17	chosen {
18		stdout-path = "serial0:115200n8";
19	};
20
21	memory@0 {
22		reg = <0x00000000 0x40000000>;
23	};
24
25	host1x@50000000 {
26		dc@54200000 {
27			rgb {
28				status = "okay";
29
30				nvidia,panel = <&panel>;
31			};
32		};
33
34		hdmi@54280000 {
35			status = "okay";
36
37			vdd-supply = <&hdmi_vdd_reg>;
38			pll-supply = <&hdmi_pll_reg>;
39
40			nvidia,ddc-i2c-bus = <&hdmi_ddc>;
41			nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
42				GPIO_ACTIVE_HIGH>;
43		};
44	};
45
46	pinmux@70000014 {
47		pinctrl-names = "default";
48		pinctrl-0 = <&state_default>;
49
50		state_default: pinmux {
51			ata {
52				nvidia,pins = "ata";
53				nvidia,function = "ide";
54			};
55			atb {
56				nvidia,pins = "atb", "gma", "gme";
57				nvidia,function = "sdio4";
58			};
59			atc {
60				nvidia,pins = "atc";
61				nvidia,function = "nand";
62			};
63			atd {
64				nvidia,pins = "atd", "ate", "gmb", "spia",
65					"spib", "spic";
66				nvidia,function = "gmi";
67			};
68			cdev1 {
69				nvidia,pins = "cdev1";
70				nvidia,function = "plla_out";
71			};
72			cdev2 {
73				nvidia,pins = "cdev2";
74				nvidia,function = "pllp_out4";
75			};
76			crtp {
77				nvidia,pins = "crtp", "lm1";
78				nvidia,function = "crt";
79			};
80			csus {
81				nvidia,pins = "csus";
82				nvidia,function = "vi_sensor_clk";
83			};
84			dap1 {
85				nvidia,pins = "dap1";
86				nvidia,function = "dap1";
87			};
88			dap2 {
89				nvidia,pins = "dap2";
90				nvidia,function = "dap2";
91			};
92			dap3 {
93				nvidia,pins = "dap3";
94				nvidia,function = "dap3";
95			};
96			dap4 {
97				nvidia,pins = "dap4";
98				nvidia,function = "dap4";
99			};
100			dta {
101				nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
102				nvidia,function = "vi";
103			};
104			dtf {
105				nvidia,pins = "dtf";
106				nvidia,function = "i2c3";
107			};
108			gmc {
109				nvidia,pins = "gmc";
110				nvidia,function = "uartd";
111			};
112			gmd {
113				nvidia,pins = "gmd";
114				nvidia,function = "sflash";
115			};
116			gpu {
117				nvidia,pins = "gpu";
118				nvidia,function = "pwm";
119			};
120			gpu7 {
121				nvidia,pins = "gpu7";
122				nvidia,function = "rtck";
123			};
124			gpv {
125				nvidia,pins = "gpv", "slxa", "slxk";
126				nvidia,function = "pcie";
127			};
128			hdint {
129				nvidia,pins = "hdint";
130				nvidia,function = "hdmi";
131			};
132			i2cp {
133				nvidia,pins = "i2cp";
134				nvidia,function = "i2cp";
135			};
136			irrx {
137				nvidia,pins = "irrx", "irtx";
138				nvidia,function = "uartb";
139			};
140			kbca {
141				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
142					"kbce", "kbcf";
143				nvidia,function = "kbc";
144			};
145			lcsn {
146				nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
147					"lsdi", "lvp0";
148				nvidia,function = "rsvd4";
149			};
150			ld0 {
151				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
152					"ld5", "ld6", "ld7", "ld8", "ld9",
153					"ld10", "ld11", "ld12", "ld13", "ld14",
154					"ld15", "ld16", "ld17", "ldi", "lhp0",
155					"lhp1", "lhp2", "lhs", "lpp", "lpw0",
156					"lpw2", "lsc0", "lsc1", "lsck", "lsda",
157					"lspi", "lvp1", "lvs";
158				nvidia,function = "displaya";
159			};
160			owc {
161				nvidia,pins = "owc", "spdi", "spdo", "uac";
162				nvidia,function = "rsvd2";
163			};
164			pmc {
165				nvidia,pins = "pmc";
166				nvidia,function = "pwr_on";
167			};
168			rm {
169				nvidia,pins = "rm";
170				nvidia,function = "i2c1";
171			};
172			sdb {
173				nvidia,pins = "sdb", "sdc", "sdd", "slxc";
174				nvidia,function = "sdio3";
175			};
176			sdio1 {
177				nvidia,pins = "sdio1";
178				nvidia,function = "sdio1";
179			};
180			slxd {
181				nvidia,pins = "slxd";
182				nvidia,function = "spdif";
183			};
184			spid {
185				nvidia,pins = "spid", "spie", "spif";
186				nvidia,function = "spi1";
187			};
188			spig {
189				nvidia,pins = "spig", "spih";
190				nvidia,function = "spi2_alt";
191			};
192			uaa {
193				nvidia,pins = "uaa", "uab", "uda";
194				nvidia,function = "ulpi";
195			};
196			uad {
197				nvidia,pins = "uad";
198				nvidia,function = "irda";
199			};
200			uca {
201				nvidia,pins = "uca", "ucb";
202				nvidia,function = "uartc";
203			};
204			conf_ata {
205				nvidia,pins = "ata", "atb", "atc", "atd",
206					"cdev1", "cdev2", "dap1", "dap2",
207					"dap4", "ddc", "dtf", "gma", "gmc",
208					"gme", "gpu", "gpu7", "i2cp", "irrx",
209					"irtx", "pta", "rm", "sdc", "sdd",
210					"slxc", "slxd", "slxk", "spdi", "spdo",
211					"uac", "uad", "uca", "ucb", "uda";
212				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
213				nvidia,tristate = <TEGRA_PIN_DISABLE>;
214			};
215			conf_ate {
216				nvidia,pins = "ate", "csus", "dap3", "gmd",
217					"gpv", "owc", "spia", "spib", "spic",
218					"spid", "spie", "spig";
219				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
220				nvidia,tristate = <TEGRA_PIN_ENABLE>;
221			};
222			conf_ck32 {
223				nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
224					"pmcc", "pmcd", "pmce", "xm2c", "xm2d";
225				nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226			};
227			conf_crtp {
228				nvidia,pins = "crtp", "gmb", "slxa", "spih";
229				nvidia,pull = <TEGRA_PIN_PULL_UP>;
230				nvidia,tristate = <TEGRA_PIN_ENABLE>;
231			};
232			conf_dta {
233				nvidia,pins = "dta", "dtb", "dtc", "dtd";
234				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
235				nvidia,tristate = <TEGRA_PIN_DISABLE>;
236			};
237			conf_dte {
238				nvidia,pins = "dte", "spif";
239				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
240				nvidia,tristate = <TEGRA_PIN_ENABLE>;
241			};
242			conf_hdint {
243				nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
244					"lpw1", "lsck", "lsda", "lsdi", "lvp0";
245				nvidia,tristate = <TEGRA_PIN_ENABLE>;
246			};
247			conf_kbca {
248				nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
249					"kbce", "kbcf", "sdio1", "uaa", "uab";
250				nvidia,pull = <TEGRA_PIN_PULL_UP>;
251				nvidia,tristate = <TEGRA_PIN_DISABLE>;
252			};
253			conf_lc {
254				nvidia,pins = "lc", "ls";
255				nvidia,pull = <TEGRA_PIN_PULL_UP>;
256			};
257			conf_ld0 {
258				nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
259					"ld5", "ld6", "ld7", "ld8", "ld9",
260					"ld10", "ld11", "ld12", "ld13", "ld14",
261					"ld15", "ld16", "ld17", "ldi", "lhp0",
262					"lhp1", "lhp2", "lhs", "lm0", "lpp",
263					"lpw0", "lpw2", "lsc0", "lsc1", "lspi",
264					"lvp1", "lvs", "pmc", "sdb";
265				nvidia,tristate = <TEGRA_PIN_DISABLE>;
266			};
267			conf_ld17_0 {
268				nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
269					"ld23_22";
270				nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
271			};
272			drive_sdio1 {
273				nvidia,pins = "drive_sdio1";
274				nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
275				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
276				nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
277				nvidia,pull-down-strength = <31>;
278				nvidia,pull-up-strength = <31>;
279				nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
280				nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
281			};
282		};
283
284		state_i2cmux_ddc: pinmux_i2cmux_ddc {
285			ddc {
286				nvidia,pins = "ddc";
287				nvidia,function = "i2c2";
288			};
289			pta {
290				nvidia,pins = "pta";
291				nvidia,function = "rsvd4";
292			};
293		};
294
295		state_i2cmux_pta: pinmux_i2cmux_pta {
296			ddc {
297				nvidia,pins = "ddc";
298				nvidia,function = "rsvd4";
299			};
300			pta {
301				nvidia,pins = "pta";
302				nvidia,function = "i2c2";
303			};
304		};
305
306		state_i2cmux_idle: pinmux_i2cmux_idle {
307			ddc {
308				nvidia,pins = "ddc";
309				nvidia,function = "rsvd4";
310			};
311			pta {
312				nvidia,pins = "pta";
313				nvidia,function = "rsvd4";
314			};
315		};
316	};
317
318	i2s@70002800 {
319		status = "okay";
320	};
321
322	serial@70006300 {
323		status = "okay";
324	};
325
326	pwm: pwm@7000a000 {
327		status = "okay";
328	};
329
330	i2c@7000c000 {
331		status = "okay";
332		clock-frequency = <400000>;
333
334		wm8903: wm8903@1a {
335			compatible = "wlf,wm8903";
336			reg = <0x1a>;
337			interrupt-parent = <&gpio>;
338			interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
339
340			gpio-controller;
341			#gpio-cells = <2>;
342
343			micdet-cfg = <0>;
344			micdet-delay = <100>;
345			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
346		};
347
348		/* ALS and proximity sensor */
349		isl29018@44 {
350			compatible = "isil,isl29018";
351			reg = <0x44>;
352			interrupt-parent = <&gpio>;
353			interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>;
354		};
355	};
356
357	i2c@7000c400 {
358		status = "okay";
359		clock-frequency = <100000>;
360	};
361
362	i2cmux {
363		compatible = "i2c-mux-pinctrl";
364		#address-cells = <1>;
365		#size-cells = <0>;
366
367		i2c-parent = <&{/i2c@7000c400}>;
368
369		pinctrl-names = "ddc", "pta", "idle";
370		pinctrl-0 = <&state_i2cmux_ddc>;
371		pinctrl-1 = <&state_i2cmux_pta>;
372		pinctrl-2 = <&state_i2cmux_idle>;
373
374		hdmi_ddc: i2c@0 {
375			reg = <0>;
376			#address-cells = <1>;
377			#size-cells = <0>;
378		};
379
380		lvds_ddc: i2c@1 {
381			reg = <1>;
382			#address-cells = <1>;
383			#size-cells = <0>;
384		};
385	};
386
387	i2c@7000c500 {
388		status = "okay";
389		clock-frequency = <400000>;
390	};
391
392	i2c@7000d000 {
393		status = "okay";
394		clock-frequency = <400000>;
395
396		pmic: tps6586x@34 {
397			compatible = "ti,tps6586x";
398			reg = <0x34>;
399			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
400
401			ti,system-power-controller;
402
403			#gpio-cells = <2>;
404			gpio-controller;
405
406			sys-supply = <&vdd_5v0_reg>;
407			vin-sm0-supply = <&sys_reg>;
408			vin-sm1-supply = <&sys_reg>;
409			vin-sm2-supply = <&sys_reg>;
410			vinldo01-supply = <&sm2_reg>;
411			vinldo23-supply = <&sm2_reg>;
412			vinldo4-supply = <&sm2_reg>;
413			vinldo678-supply = <&sm2_reg>;
414			vinldo9-supply = <&sm2_reg>;
415
416			regulators {
417				sys_reg: sys {
418					regulator-name = "vdd_sys";
419					regulator-always-on;
420				};
421
422				sm0 {
423					regulator-name = "vdd_sm0,vdd_core";
424					regulator-min-microvolt = <1200000>;
425					regulator-max-microvolt = <1200000>;
426					regulator-always-on;
427				};
428
429				sm1 {
430					regulator-name = "vdd_sm1,vdd_cpu";
431					regulator-min-microvolt = <1000000>;
432					regulator-max-microvolt = <1000000>;
433					regulator-always-on;
434				};
435
436				sm2_reg: sm2 {
437					regulator-name = "vdd_sm2,vin_ldo*";
438					regulator-min-microvolt = <3700000>;
439					regulator-max-microvolt = <3700000>;
440					regulator-always-on;
441				};
442
443				/* LDO0 is not connected to anything */
444
445				ldo1 {
446					regulator-name = "vdd_ldo1,avdd_pll*";
447					regulator-min-microvolt = <1100000>;
448					regulator-max-microvolt = <1100000>;
449					regulator-always-on;
450				};
451
452				ldo2 {
453					regulator-name = "vdd_ldo2,vdd_rtc";
454					regulator-min-microvolt = <1200000>;
455					regulator-max-microvolt = <1200000>;
456				};
457
458				ldo3 {
459					regulator-name = "vdd_ldo3,avdd_usb*";
460					regulator-min-microvolt = <3300000>;
461					regulator-max-microvolt = <3300000>;
462					regulator-always-on;
463				};
464
465				ldo4 {
466					regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
467					regulator-min-microvolt = <1800000>;
468					regulator-max-microvolt = <1800000>;
469					regulator-always-on;
470				};
471
472				ldo5 {
473					regulator-name = "vdd_ldo5,vcore_mmc";
474					regulator-min-microvolt = <2850000>;
475					regulator-max-microvolt = <2850000>;
476					regulator-always-on;
477				};
478
479				ldo6 {
480					regulator-name = "vdd_ldo6,avdd_vdac";
481					regulator-min-microvolt = <1800000>;
482					regulator-max-microvolt = <1800000>;
483				};
484
485				hdmi_vdd_reg: ldo7 {
486					regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
487					regulator-min-microvolt = <3300000>;
488					regulator-max-microvolt = <3300000>;
489				};
490
491				hdmi_pll_reg: ldo8 {
492					regulator-name = "vdd_ldo8,avdd_hdmi_pll";
493					regulator-min-microvolt = <1800000>;
494					regulator-max-microvolt = <1800000>;
495				};
496
497				ldo9 {
498					regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
499					regulator-min-microvolt = <2850000>;
500					regulator-max-microvolt = <2850000>;
501					regulator-always-on;
502				};
503
504				ldo_rtc {
505					regulator-name = "vdd_rtc_out,vdd_cell";
506					regulator-min-microvolt = <3300000>;
507					regulator-max-microvolt = <3300000>;
508					regulator-always-on;
509				};
510			};
511		};
512
513		temperature-sensor@4c {
514			compatible = "onnn,nct1008";
515			reg = <0x4c>;
516		};
517	};
518
519	pmc@7000e400 {
520		nvidia,invert-interrupt;
521		nvidia,suspend-mode = <1>;
522		nvidia,cpu-pwr-good-time = <2000>;
523		nvidia,cpu-pwr-off-time = <100>;
524		nvidia,core-pwr-good-time = <3845 3845>;
525		nvidia,core-pwr-off-time = <458>;
526		nvidia,sys-clock-req-active-high;
527	};
528
529	usb@c5000000 {
530		status = "okay";
531	};
532
533	usb-phy@c5000000 {
534		status = "okay";
535	};
536
537	usb@c5004000 {
538		status = "okay";
539		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
540			GPIO_ACTIVE_LOW>;
541	};
542
543	usb-phy@c5004000 {
544		status = "okay";
545		nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
546			GPIO_ACTIVE_LOW>;
547	};
548
549	usb@c5008000 {
550		status = "okay";
551	};
552
553	usb-phy@c5008000 {
554		status = "okay";
555	};
556
557	sdhci@c8000000 {
558		status = "okay";
559		power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>;
560		bus-width = <4>;
561		keep-power-in-suspend;
562	};
563
564	sdhci@c8000400 {
565		status = "okay";
566		cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
567		wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
568		power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
569		bus-width = <4>;
570	};
571
572	sdhci@c8000600 {
573		status = "okay";
574		bus-width = <8>;
575		non-removable;
576	};
577
578	backlight: backlight {
579		compatible = "pwm-backlight";
580
581		enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
582		power-supply = <&vdd_bl_reg>;
583		pwms = <&pwm 2 5000000>;
584
585		brightness-levels = <0 4 8 16 32 64 128 255>;
586		default-brightness-level = <6>;
587	};
588
589	clocks {
590		compatible = "simple-bus";
591		#address-cells = <1>;
592		#size-cells = <0>;
593
594		clk32k_in: clock@0 {
595			compatible = "fixed-clock";
596			reg = <0>;
597			#clock-cells = <0>;
598			clock-frequency = <32768>;
599		};
600	};
601
602	gpio-keys {
603		compatible = "gpio-keys";
604
605		power {
606			label = "Power";
607			gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
608			linux,code = <KEY_POWER>;
609			wakeup-source;
610		};
611	};
612
613	panel: panel {
614		compatible = "chunghwa,claa101wa01a", "simple-panel";
615
616		power-supply = <&vdd_pnl_reg>;
617		enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
618
619		backlight = <&backlight>;
620		ddc-i2c-bus = <&lvds_ddc>;
621	};
622
623	regulators {
624		compatible = "simple-bus";
625		#address-cells = <1>;
626		#size-cells = <0>;
627
628		vdd_5v0_reg: regulator@0 {
629			compatible = "regulator-fixed";
630			reg = <0>;
631			regulator-name = "vdd_5v0";
632			regulator-min-microvolt = <5000000>;
633			regulator-max-microvolt = <5000000>;
634			regulator-always-on;
635		};
636
637		regulator@1 {
638			compatible = "regulator-fixed";
639			reg = <1>;
640			regulator-name = "vdd_1v5";
641			regulator-min-microvolt = <1500000>;
642			regulator-max-microvolt = <1500000>;
643			gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
644		};
645
646		regulator@2 {
647			compatible = "regulator-fixed";
648			reg = <2>;
649			regulator-name = "vdd_1v2";
650			regulator-min-microvolt = <1200000>;
651			regulator-max-microvolt = <1200000>;
652			gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
653			enable-active-high;
654		};
655
656		vdd_pnl_reg: regulator@3 {
657			compatible = "regulator-fixed";
658			reg = <3>;
659			regulator-name = "vdd_pnl";
660			regulator-min-microvolt = <2800000>;
661			regulator-max-microvolt = <2800000>;
662			gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
663			enable-active-high;
664		};
665
666		vdd_bl_reg: regulator@4 {
667			compatible = "regulator-fixed";
668			reg = <4>;
669			regulator-name = "vdd_bl";
670			regulator-min-microvolt = <2800000>;
671			regulator-max-microvolt = <2800000>;
672			gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
673			enable-active-high;
674		};
675	};
676
677	sound {
678		compatible = "nvidia,tegra-audio-wm8903-ventana",
679			     "nvidia,tegra-audio-wm8903";
680		nvidia,model = "NVIDIA Tegra Ventana";
681
682		nvidia,audio-routing =
683			"Headphone Jack", "HPOUTR",
684			"Headphone Jack", "HPOUTL",
685			"Int Spk", "ROP",
686			"Int Spk", "RON",
687			"Int Spk", "LOP",
688			"Int Spk", "LON",
689			"Mic Jack", "MICBIAS",
690			"IN1L", "Mic Jack";
691
692		nvidia,i2s-controller = <&tegra_i2s1>;
693		nvidia,audio-codec = <&wm8903>;
694
695		nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
696		nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
697		nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
698			GPIO_ACTIVE_HIGH>;
699		nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
700			GPIO_ACTIVE_HIGH>;
701
702		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
703			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
704			 <&tegra_car TEGRA20_CLK_CDEV1>;
705		clock-names = "pll_a", "pll_a_out0", "mclk";
706	};
707};
708