1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra114-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra114-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 compatible = "nvidia,tegra114"; 10 interrupt-parent = <&lic>; 11 #address-cells = <1>; 12 #size-cells = <1>; 13 14 memory@80000000 { 15 device_type = "memory"; 16 reg = <0x80000000 0x0>; 17 }; 18 19 host1x@50000000 { 20 compatible = "nvidia,tegra114-host1x", "simple-bus"; 21 reg = <0x50000000 0x00028000>; 22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 24 clocks = <&tegra_car TEGRA114_CLK_HOST1X>; 25 resets = <&tegra_car 28>; 26 reset-names = "host1x"; 27 iommus = <&mc TEGRA_SWGROUP_HC>; 28 29 #address-cells = <1>; 30 #size-cells = <1>; 31 32 ranges = <0x54000000 0x54000000 0x01000000>; 33 34 gr2d@54140000 { 35 compatible = "nvidia,tegra114-gr2d", "nvidia,tegra20-gr2d"; 36 reg = <0x54140000 0x00040000>; 37 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 38 clocks = <&tegra_car TEGRA114_CLK_GR2D>; 39 resets = <&tegra_car 21>; 40 reset-names = "2d"; 41 42 iommus = <&mc TEGRA_SWGROUP_G2>; 43 }; 44 45 gr3d@54180000 { 46 compatible = "nvidia,tegra114-gr3d", "nvidia,tegra20-gr3d"; 47 reg = <0x54180000 0x00040000>; 48 clocks = <&tegra_car TEGRA114_CLK_GR3D>; 49 resets = <&tegra_car 24>; 50 reset-names = "3d"; 51 52 iommus = <&mc TEGRA_SWGROUP_NV>; 53 }; 54 55 dc@54200000 { 56 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; 57 reg = <0x54200000 0x00040000>; 58 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 59 clocks = <&tegra_car TEGRA114_CLK_DISP1>, 60 <&tegra_car TEGRA114_CLK_PLL_P>; 61 clock-names = "dc", "parent"; 62 resets = <&tegra_car 27>; 63 reset-names = "dc"; 64 65 iommus = <&mc TEGRA_SWGROUP_DC>; 66 67 nvidia,head = <0>; 68 69 rgb { 70 status = "disabled"; 71 }; 72 }; 73 74 dc@54240000 { 75 compatible = "nvidia,tegra114-dc", "nvidia,tegra20-dc"; 76 reg = <0x54240000 0x00040000>; 77 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 78 clocks = <&tegra_car TEGRA114_CLK_DISP2>, 79 <&tegra_car TEGRA114_CLK_PLL_P>; 80 clock-names = "dc", "parent"; 81 resets = <&tegra_car 26>; 82 reset-names = "dc"; 83 84 iommus = <&mc TEGRA_SWGROUP_DCB>; 85 86 nvidia,head = <1>; 87 88 rgb { 89 status = "disabled"; 90 }; 91 }; 92 93 hdmi@54280000 { 94 compatible = "nvidia,tegra114-hdmi"; 95 reg = <0x54280000 0x00040000>; 96 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 97 clocks = <&tegra_car TEGRA114_CLK_HDMI>, 98 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; 99 clock-names = "hdmi", "parent"; 100 resets = <&tegra_car 51>; 101 reset-names = "hdmi"; 102 status = "disabled"; 103 }; 104 105 dsi@54300000 { 106 compatible = "nvidia,tegra114-dsi"; 107 reg = <0x54300000 0x00040000>; 108 clocks = <&tegra_car TEGRA114_CLK_DSIA>, 109 <&tegra_car TEGRA114_CLK_DSIALP>, 110 <&tegra_car TEGRA114_CLK_PLL_D_OUT0>; 111 clock-names = "dsi", "lp", "parent"; 112 resets = <&tegra_car 48>; 113 reset-names = "dsi"; 114 nvidia,mipi-calibrate = <&mipi 0x060>; /* DSIA & DSIB pads */ 115 status = "disabled"; 116 117 #address-cells = <1>; 118 #size-cells = <0>; 119 }; 120 121 dsi@54400000 { 122 compatible = "nvidia,tegra114-dsi"; 123 reg = <0x54400000 0x00040000>; 124 clocks = <&tegra_car TEGRA114_CLK_DSIB>, 125 <&tegra_car TEGRA114_CLK_DSIBLP>, 126 <&tegra_car TEGRA114_CLK_PLL_D2_OUT0>; 127 clock-names = "dsi", "lp", "parent"; 128 resets = <&tegra_car 82>; 129 reset-names = "dsi"; 130 nvidia,mipi-calibrate = <&mipi 0x180>; /* DSIC & DSID pads */ 131 status = "disabled"; 132 133 #address-cells = <1>; 134 #size-cells = <0>; 135 }; 136 }; 137 138 gic: interrupt-controller@50041000 { 139 compatible = "arm,cortex-a15-gic"; 140 #interrupt-cells = <3>; 141 interrupt-controller; 142 reg = <0x50041000 0x1000>, 143 <0x50042000 0x1000>, 144 <0x50044000 0x2000>, 145 <0x50046000 0x2000>; 146 interrupts = <GIC_PPI 9 147 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 148 interrupt-parent = <&gic>; 149 }; 150 151 lic: interrupt-controller@60004000 { 152 compatible = "nvidia,tegra114-ictlr", "nvidia,tegra30-ictlr"; 153 reg = <0x60004000 0x100>, 154 <0x60004100 0x50>, 155 <0x60004200 0x50>, 156 <0x60004300 0x50>, 157 <0x60004400 0x50>; 158 interrupt-controller; 159 #interrupt-cells = <3>; 160 interrupt-parent = <&gic>; 161 }; 162 163 timer@60005000 { 164 compatible = "nvidia,tegra114-timer", "nvidia,tegra30-timer", "nvidia,tegra20-timer"; 165 reg = <0x60005000 0x400>; 166 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 168 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 169 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 170 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&tegra_car TEGRA114_CLK_TIMER>; 173 }; 174 175 tegra_car: clock@60006000 { 176 compatible = "nvidia,tegra114-car"; 177 reg = <0x60006000 0x1000>; 178 #clock-cells = <1>; 179 #reset-cells = <1>; 180 }; 181 182 flow-controller@60007000 { 183 compatible = "nvidia,tegra114-flowctrl"; 184 reg = <0x60007000 0x1000>; 185 }; 186 187 apbdma: dma@6000a000 { 188 compatible = "nvidia,tegra114-apbdma"; 189 reg = <0x6000a000 0x1400>; 190 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&tegra_car TEGRA114_CLK_APBDMA>; 223 resets = <&tegra_car 34>; 224 reset-names = "dma"; 225 #dma-cells = <1>; 226 }; 227 228 ahb: ahb@6000c000 { 229 compatible = "nvidia,tegra114-ahb", "nvidia,tegra30-ahb"; 230 reg = <0x6000c000 0x150>; 231 }; 232 233 gpio: gpio@6000d000 { 234 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio"; 235 reg = <0x6000d000 0x1000>; 236 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 244 #gpio-cells = <2>; 245 gpio-controller; 246 #interrupt-cells = <2>; 247 interrupt-controller; 248 /* 249 gpio-ranges = <&pinmux 0 0 246>; 250 */ 251 }; 252 253 apbmisc@70000800 { 254 compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; 255 reg = <0x70000800 0x64 /* Chip revision */ 256 0x70000008 0x04>; /* Strapping options */ 257 }; 258 259 pinmux: pinmux@70000868 { 260 compatible = "nvidia,tegra114-pinmux"; 261 reg = <0x70000868 0x148 /* Pad control registers */ 262 0x70003000 0x40c>; /* Mux registers */ 263 }; 264 265 /* 266 * There are two serial driver i.e. 8250 based simple serial 267 * driver and APB DMA based serial driver for higher baudrate 268 * and performace. To enable the 8250 based driver, the compatible 269 * is "nvidia,tegra114-uart", "nvidia,tegra20-uart" and to enable 270 * the APB DMA based serial driver, the compatible is 271 * "nvidia,tegra114-hsuart", "nvidia,tegra30-hsuart". 272 */ 273 uarta: serial@70006000 { 274 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 275 reg = <0x70006000 0x40>; 276 reg-shift = <2>; 277 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&tegra_car TEGRA114_CLK_UARTA>; 279 resets = <&tegra_car 6>; 280 reset-names = "serial"; 281 dmas = <&apbdma 8>, <&apbdma 8>; 282 dma-names = "rx", "tx"; 283 status = "disabled"; 284 }; 285 286 uartb: serial@70006040 { 287 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 288 reg = <0x70006040 0x40>; 289 reg-shift = <2>; 290 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&tegra_car TEGRA114_CLK_UARTB>; 292 resets = <&tegra_car 7>; 293 reset-names = "serial"; 294 dmas = <&apbdma 9>, <&apbdma 9>; 295 dma-names = "rx", "tx"; 296 status = "disabled"; 297 }; 298 299 uartc: serial@70006200 { 300 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 301 reg = <0x70006200 0x100>; 302 reg-shift = <2>; 303 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&tegra_car TEGRA114_CLK_UARTC>; 305 resets = <&tegra_car 55>; 306 reset-names = "serial"; 307 dmas = <&apbdma 10>, <&apbdma 10>; 308 dma-names = "rx", "tx"; 309 status = "disabled"; 310 }; 311 312 uartd: serial@70006300 { 313 compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart"; 314 reg = <0x70006300 0x100>; 315 reg-shift = <2>; 316 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 317 clocks = <&tegra_car TEGRA114_CLK_UARTD>; 318 resets = <&tegra_car 65>; 319 reset-names = "serial"; 320 dmas = <&apbdma 19>, <&apbdma 19>; 321 dma-names = "rx", "tx"; 322 status = "disabled"; 323 }; 324 325 pwm: pwm@7000a000 { 326 compatible = "nvidia,tegra114-pwm", "nvidia,tegra20-pwm"; 327 reg = <0x7000a000 0x100>; 328 #pwm-cells = <2>; 329 clocks = <&tegra_car TEGRA114_CLK_PWM>; 330 resets = <&tegra_car 17>; 331 reset-names = "pwm"; 332 status = "disabled"; 333 }; 334 335 i2c@7000c000 { 336 compatible = "nvidia,tegra114-i2c"; 337 reg = <0x7000c000 0x100>; 338 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 clocks = <&tegra_car TEGRA114_CLK_I2C1>; 342 clock-names = "div-clk"; 343 resets = <&tegra_car 12>; 344 reset-names = "i2c"; 345 dmas = <&apbdma 21>, <&apbdma 21>; 346 dma-names = "rx", "tx"; 347 status = "disabled"; 348 }; 349 350 i2c@7000c400 { 351 compatible = "nvidia,tegra114-i2c"; 352 reg = <0x7000c400 0x100>; 353 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 clocks = <&tegra_car TEGRA114_CLK_I2C2>; 357 clock-names = "div-clk"; 358 resets = <&tegra_car 54>; 359 reset-names = "i2c"; 360 dmas = <&apbdma 22>, <&apbdma 22>; 361 dma-names = "rx", "tx"; 362 status = "disabled"; 363 }; 364 365 i2c@7000c500 { 366 compatible = "nvidia,tegra114-i2c"; 367 reg = <0x7000c500 0x100>; 368 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clocks = <&tegra_car TEGRA114_CLK_I2C3>; 372 clock-names = "div-clk"; 373 resets = <&tegra_car 67>; 374 reset-names = "i2c"; 375 dmas = <&apbdma 23>, <&apbdma 23>; 376 dma-names = "rx", "tx"; 377 status = "disabled"; 378 }; 379 380 i2c@7000c700 { 381 compatible = "nvidia,tegra114-i2c"; 382 reg = <0x7000c700 0x100>; 383 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 clocks = <&tegra_car TEGRA114_CLK_I2C4>; 387 clock-names = "div-clk"; 388 resets = <&tegra_car 103>; 389 reset-names = "i2c"; 390 dmas = <&apbdma 26>, <&apbdma 26>; 391 dma-names = "rx", "tx"; 392 status = "disabled"; 393 }; 394 395 i2c@7000d000 { 396 compatible = "nvidia,tegra114-i2c"; 397 reg = <0x7000d000 0x100>; 398 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 clocks = <&tegra_car TEGRA114_CLK_I2C5>; 402 clock-names = "div-clk"; 403 resets = <&tegra_car 47>; 404 reset-names = "i2c"; 405 dmas = <&apbdma 24>, <&apbdma 24>; 406 dma-names = "rx", "tx"; 407 status = "disabled"; 408 }; 409 410 spi@7000d400 { 411 compatible = "nvidia,tegra114-spi"; 412 reg = <0x7000d400 0x200>; 413 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 clocks = <&tegra_car TEGRA114_CLK_SBC1>; 417 clock-names = "spi"; 418 resets = <&tegra_car 41>; 419 reset-names = "spi"; 420 dmas = <&apbdma 15>, <&apbdma 15>; 421 dma-names = "rx", "tx"; 422 status = "disabled"; 423 }; 424 425 spi@7000d600 { 426 compatible = "nvidia,tegra114-spi"; 427 reg = <0x7000d600 0x200>; 428 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 clocks = <&tegra_car TEGRA114_CLK_SBC2>; 432 clock-names = "spi"; 433 resets = <&tegra_car 44>; 434 reset-names = "spi"; 435 dmas = <&apbdma 16>, <&apbdma 16>; 436 dma-names = "rx", "tx"; 437 status = "disabled"; 438 }; 439 440 spi@7000d800 { 441 compatible = "nvidia,tegra114-spi"; 442 reg = <0x7000d800 0x200>; 443 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 444 #address-cells = <1>; 445 #size-cells = <0>; 446 clocks = <&tegra_car TEGRA114_CLK_SBC3>; 447 clock-names = "spi"; 448 resets = <&tegra_car 46>; 449 reset-names = "spi"; 450 dmas = <&apbdma 17>, <&apbdma 17>; 451 dma-names = "rx", "tx"; 452 status = "disabled"; 453 }; 454 455 spi@7000da00 { 456 compatible = "nvidia,tegra114-spi"; 457 reg = <0x7000da00 0x200>; 458 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 clocks = <&tegra_car TEGRA114_CLK_SBC4>; 462 clock-names = "spi"; 463 resets = <&tegra_car 68>; 464 reset-names = "spi"; 465 dmas = <&apbdma 18>, <&apbdma 18>; 466 dma-names = "rx", "tx"; 467 status = "disabled"; 468 }; 469 470 spi@7000dc00 { 471 compatible = "nvidia,tegra114-spi"; 472 reg = <0x7000dc00 0x200>; 473 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 474 #address-cells = <1>; 475 #size-cells = <0>; 476 clocks = <&tegra_car TEGRA114_CLK_SBC5>; 477 clock-names = "spi"; 478 resets = <&tegra_car 104>; 479 reset-names = "spi"; 480 dmas = <&apbdma 27>, <&apbdma 27>; 481 dma-names = "rx", "tx"; 482 status = "disabled"; 483 }; 484 485 spi@7000de00 { 486 compatible = "nvidia,tegra114-spi"; 487 reg = <0x7000de00 0x200>; 488 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 clocks = <&tegra_car TEGRA114_CLK_SBC6>; 492 clock-names = "spi"; 493 resets = <&tegra_car 105>; 494 reset-names = "spi"; 495 dmas = <&apbdma 28>, <&apbdma 28>; 496 dma-names = "rx", "tx"; 497 status = "disabled"; 498 }; 499 500 rtc@7000e000 { 501 compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc"; 502 reg = <0x7000e000 0x100>; 503 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&tegra_car TEGRA114_CLK_RTC>; 505 }; 506 507 kbc@7000e200 { 508 compatible = "nvidia,tegra114-kbc"; 509 reg = <0x7000e200 0x100>; 510 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&tegra_car TEGRA114_CLK_KBC>; 512 resets = <&tegra_car 36>; 513 reset-names = "kbc"; 514 status = "disabled"; 515 }; 516 517 pmc@7000e400 { 518 compatible = "nvidia,tegra114-pmc"; 519 reg = <0x7000e400 0x400>; 520 clocks = <&tegra_car TEGRA114_CLK_PCLK>, <&clk32k_in>; 521 clock-names = "pclk", "clk32k_in"; 522 }; 523 524 fuse@7000f800 { 525 compatible = "nvidia,tegra114-efuse"; 526 reg = <0x7000f800 0x400>; 527 clocks = <&tegra_car TEGRA114_CLK_FUSE>; 528 clock-names = "fuse"; 529 resets = <&tegra_car 39>; 530 reset-names = "fuse"; 531 }; 532 533 mc: memory-controller@70019000 { 534 compatible = "nvidia,tegra114-mc"; 535 reg = <0x70019000 0x1000>; 536 clocks = <&tegra_car TEGRA114_CLK_MC>; 537 clock-names = "mc"; 538 539 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 540 541 #iommu-cells = <1>; 542 }; 543 544 ahub@70080000 { 545 compatible = "nvidia,tegra114-ahub"; 546 reg = <0x70080000 0x200>, 547 <0x70080200 0x100>, 548 <0x70081000 0x200>; 549 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 550 clocks = <&tegra_car TEGRA114_CLK_D_AUDIO>, 551 <&tegra_car TEGRA114_CLK_APBIF>; 552 clock-names = "d_audio", "apbif"; 553 resets = <&tegra_car 106>, /* d_audio */ 554 <&tegra_car 107>, /* apbif */ 555 <&tegra_car 30>, /* i2s0 */ 556 <&tegra_car 11>, /* i2s1 */ 557 <&tegra_car 18>, /* i2s2 */ 558 <&tegra_car 101>, /* i2s3 */ 559 <&tegra_car 102>, /* i2s4 */ 560 <&tegra_car 108>, /* dam0 */ 561 <&tegra_car 109>, /* dam1 */ 562 <&tegra_car 110>, /* dam2 */ 563 <&tegra_car 10>, /* spdif */ 564 <&tegra_car 153>, /* amx */ 565 <&tegra_car 154>; /* adx */ 566 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 567 "i2s3", "i2s4", "dam0", "dam1", "dam2", 568 "spdif", "amx", "adx"; 569 dmas = <&apbdma 1>, <&apbdma 1>, 570 <&apbdma 2>, <&apbdma 2>, 571 <&apbdma 3>, <&apbdma 3>, 572 <&apbdma 4>, <&apbdma 4>, 573 <&apbdma 6>, <&apbdma 6>, 574 <&apbdma 7>, <&apbdma 7>, 575 <&apbdma 12>, <&apbdma 12>, 576 <&apbdma 13>, <&apbdma 13>, 577 <&apbdma 14>, <&apbdma 14>, 578 <&apbdma 29>, <&apbdma 29>; 579 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 580 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 581 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 582 "rx9", "tx9"; 583 ranges; 584 #address-cells = <1>; 585 #size-cells = <1>; 586 587 tegra_i2s0: i2s@70080300 { 588 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 589 reg = <0x70080300 0x100>; 590 nvidia,ahub-cif-ids = <4 4>; 591 clocks = <&tegra_car TEGRA114_CLK_I2S0>; 592 resets = <&tegra_car 30>; 593 reset-names = "i2s"; 594 status = "disabled"; 595 }; 596 597 tegra_i2s1: i2s@70080400 { 598 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 599 reg = <0x70080400 0x100>; 600 nvidia,ahub-cif-ids = <5 5>; 601 clocks = <&tegra_car TEGRA114_CLK_I2S1>; 602 resets = <&tegra_car 11>; 603 reset-names = "i2s"; 604 status = "disabled"; 605 }; 606 607 tegra_i2s2: i2s@70080500 { 608 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 609 reg = <0x70080500 0x100>; 610 nvidia,ahub-cif-ids = <6 6>; 611 clocks = <&tegra_car TEGRA114_CLK_I2S2>; 612 resets = <&tegra_car 18>; 613 reset-names = "i2s"; 614 status = "disabled"; 615 }; 616 617 tegra_i2s3: i2s@70080600 { 618 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 619 reg = <0x70080600 0x100>; 620 nvidia,ahub-cif-ids = <7 7>; 621 clocks = <&tegra_car TEGRA114_CLK_I2S3>; 622 resets = <&tegra_car 101>; 623 reset-names = "i2s"; 624 status = "disabled"; 625 }; 626 627 tegra_i2s4: i2s@70080700 { 628 compatible = "nvidia,tegra114-i2s", "nvidia,tegra30-i2s"; 629 reg = <0x70080700 0x100>; 630 nvidia,ahub-cif-ids = <8 8>; 631 clocks = <&tegra_car TEGRA114_CLK_I2S4>; 632 resets = <&tegra_car 102>; 633 reset-names = "i2s"; 634 status = "disabled"; 635 }; 636 }; 637 638 mipi: mipi@700e3000 { 639 compatible = "nvidia,tegra114-mipi"; 640 reg = <0x700e3000 0x100>; 641 clocks = <&tegra_car TEGRA114_CLK_MIPI_CAL>; 642 #nvidia,mipi-calibrate-cells = <1>; 643 }; 644 645 sdhci@78000000 { 646 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 647 reg = <0x78000000 0x200>; 648 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&tegra_car TEGRA114_CLK_SDMMC1>; 650 resets = <&tegra_car 14>; 651 reset-names = "sdhci"; 652 status = "disabled"; 653 }; 654 655 sdhci@78000200 { 656 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 657 reg = <0x78000200 0x200>; 658 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&tegra_car TEGRA114_CLK_SDMMC2>; 660 resets = <&tegra_car 9>; 661 reset-names = "sdhci"; 662 status = "disabled"; 663 }; 664 665 sdhci@78000400 { 666 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 667 reg = <0x78000400 0x200>; 668 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 669 clocks = <&tegra_car TEGRA114_CLK_SDMMC3>; 670 resets = <&tegra_car 69>; 671 reset-names = "sdhci"; 672 status = "disabled"; 673 }; 674 675 sdhci@78000600 { 676 compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; 677 reg = <0x78000600 0x200>; 678 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 679 clocks = <&tegra_car TEGRA114_CLK_SDMMC4>; 680 resets = <&tegra_car 15>; 681 reset-names = "sdhci"; 682 status = "disabled"; 683 }; 684 685 usb@7d000000 { 686 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 687 reg = <0x7d000000 0x4000>; 688 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 689 phy_type = "utmi"; 690 clocks = <&tegra_car TEGRA114_CLK_USBD>; 691 resets = <&tegra_car 22>; 692 reset-names = "usb"; 693 nvidia,phy = <&phy1>; 694 status = "disabled"; 695 }; 696 697 phy1: usb-phy@7d000000 { 698 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 699 reg = <0x7d000000 0x4000 0x7d000000 0x4000>; 700 phy_type = "utmi"; 701 clocks = <&tegra_car TEGRA114_CLK_USBD>, 702 <&tegra_car TEGRA114_CLK_PLL_U>, 703 <&tegra_car TEGRA114_CLK_USBD>; 704 clock-names = "reg", "pll_u", "utmi-pads"; 705 resets = <&tegra_car 22>, <&tegra_car 22>; 706 reset-names = "usb", "utmi-pads"; 707 nvidia,hssync-start-delay = <0>; 708 nvidia,idle-wait-delay = <17>; 709 nvidia,elastic-limit = <16>; 710 nvidia,term-range-adj = <6>; 711 nvidia,xcvr-setup = <9>; 712 nvidia,xcvr-lsfslew = <0>; 713 nvidia,xcvr-lsrslew = <3>; 714 nvidia,hssquelch-level = <2>; 715 nvidia,hsdiscon-level = <5>; 716 nvidia,xcvr-hsslew = <12>; 717 nvidia,has-utmi-pad-registers; 718 status = "disabled"; 719 }; 720 721 usb@7d008000 { 722 compatible = "nvidia,tegra114-ehci", "nvidia,tegra30-ehci", "usb-ehci"; 723 reg = <0x7d008000 0x4000>; 724 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 725 phy_type = "utmi"; 726 clocks = <&tegra_car TEGRA114_CLK_USB3>; 727 resets = <&tegra_car 59>; 728 reset-names = "usb"; 729 nvidia,phy = <&phy3>; 730 status = "disabled"; 731 }; 732 733 phy3: usb-phy@7d008000 { 734 compatible = "nvidia,tegra114-usb-phy", "nvidia,tegra30-usb-phy"; 735 reg = <0x7d008000 0x4000 0x7d000000 0x4000>; 736 phy_type = "utmi"; 737 clocks = <&tegra_car TEGRA114_CLK_USB3>, 738 <&tegra_car TEGRA114_CLK_PLL_U>, 739 <&tegra_car TEGRA114_CLK_USBD>; 740 clock-names = "reg", "pll_u", "utmi-pads"; 741 resets = <&tegra_car 59>, <&tegra_car 22>; 742 reset-names = "usb", "utmi-pads"; 743 nvidia,hssync-start-delay = <0>; 744 nvidia,idle-wait-delay = <17>; 745 nvidia,elastic-limit = <16>; 746 nvidia,term-range-adj = <6>; 747 nvidia,xcvr-setup = <9>; 748 nvidia,xcvr-lsfslew = <0>; 749 nvidia,xcvr-lsrslew = <3>; 750 nvidia,hssquelch-level = <2>; 751 nvidia,hsdiscon-level = <5>; 752 nvidia,xcvr-hsslew = <12>; 753 status = "disabled"; 754 }; 755 756 cpus { 757 #address-cells = <1>; 758 #size-cells = <0>; 759 760 cpu@0 { 761 device_type = "cpu"; 762 compatible = "arm,cortex-a15"; 763 reg = <0>; 764 }; 765 766 cpu@1 { 767 device_type = "cpu"; 768 compatible = "arm,cortex-a15"; 769 reg = <1>; 770 }; 771 772 cpu@2 { 773 device_type = "cpu"; 774 compatible = "arm,cortex-a15"; 775 reg = <2>; 776 }; 777 778 cpu@3 { 779 device_type = "cpu"; 780 compatible = "arm,cortex-a15"; 781 reg = <3>; 782 }; 783 }; 784 785 timer { 786 compatible = "arm,armv7-timer"; 787 interrupts = 788 <GIC_PPI 13 789 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 790 <GIC_PPI 14 791 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 792 <GIC_PPI 11 793 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 794 <GIC_PPI 10 795 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 796 interrupt-parent = <&gic>; 797 }; 798}; 799
