1/* 2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include <dt-bindings/clock/sun8i-de2.h> 44#include <dt-bindings/clock/sun8i-h3-ccu.h> 45#include <dt-bindings/clock/sun8i-r-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/reset/sun8i-de2.h> 48#include <dt-bindings/reset/sun8i-h3-ccu.h> 49#include <dt-bindings/reset/sun8i-r-ccu.h> 50 51/ { 52 interrupt-parent = <&gic>; 53 #address-cells = <1>; 54 #size-cells = <1>; 55 56 chosen { 57 #address-cells = <1>; 58 #size-cells = <1>; 59 ranges; 60 61 framebuffer-hdmi { 62 compatible = "allwinner,simple-framebuffer", 63 "simple-framebuffer"; 64 allwinner,pipeline = "mixer0-lcd0-hdmi"; 65 clocks = <&display_clocks CLK_MIXER0>, 66 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>; 67 status = "disabled"; 68 }; 69 70 framebuffer-tve { 71 compatible = "allwinner,simple-framebuffer", 72 "simple-framebuffer"; 73 allwinner,pipeline = "mixer1-lcd1-tve"; 74 clocks = <&display_clocks CLK_MIXER1>, 75 <&ccu CLK_TVE>; 76 status = "disabled"; 77 }; 78 }; 79 80 clocks { 81 #address-cells = <1>; 82 #size-cells = <1>; 83 ranges; 84 85 osc24M: osc24M_clk { 86 #clock-cells = <0>; 87 compatible = "fixed-clock"; 88 clock-frequency = <24000000>; 89 clock-accuracy = <50000>; 90 clock-output-names = "osc24M"; 91 }; 92 93 osc32k: osc32k_clk { 94 #clock-cells = <0>; 95 compatible = "fixed-clock"; 96 clock-frequency = <32768>; 97 clock-accuracy = <50000>; 98 clock-output-names = "ext_osc32k"; 99 }; 100 }; 101 102 de: display-engine { 103 compatible = "allwinner,sun8i-h3-display-engine"; 104 allwinner,pipelines = <&mixer0>; 105 status = "disabled"; 106 }; 107 108 soc { 109 compatible = "simple-bus"; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges; 113 114 display_clocks: clock@1000000 { 115 /* compatible is in per SoC .dtsi file */ 116 reg = <0x01000000 0x100000>; 117 clocks = <&ccu CLK_BUS_DE>, 118 <&ccu CLK_DE>; 119 clock-names = "bus", 120 "mod"; 121 resets = <&ccu RST_BUS_DE>; 122 #clock-cells = <1>; 123 #reset-cells = <1>; 124 }; 125 126 mixer0: mixer@1100000 { 127 compatible = "allwinner,sun8i-h3-de2-mixer-0"; 128 reg = <0x01100000 0x100000>; 129 clocks = <&display_clocks CLK_BUS_MIXER0>, 130 <&display_clocks CLK_MIXER0>; 131 clock-names = "bus", 132 "mod"; 133 resets = <&display_clocks RST_MIXER0>; 134 135 ports { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 mixer0_out: port@1 { 140 reg = <1>; 141 142 mixer0_out_tcon0: endpoint { 143 remote-endpoint = <&tcon0_in_mixer0>; 144 }; 145 }; 146 }; 147 }; 148 149 dma: dma-controller@1c02000 { 150 compatible = "allwinner,sun8i-h3-dma"; 151 reg = <0x01c02000 0x1000>; 152 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&ccu CLK_BUS_DMA>; 154 resets = <&ccu RST_BUS_DMA>; 155 #dma-cells = <1>; 156 }; 157 158 tcon0: lcd-controller@1c0c000 { 159 compatible = "allwinner,sun8i-h3-tcon-tv", 160 "allwinner,sun8i-a83t-tcon-tv"; 161 reg = <0x01c0c000 0x1000>; 162 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 163 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>; 164 clock-names = "ahb", "tcon-ch1"; 165 resets = <&ccu RST_BUS_TCON0>; 166 reset-names = "lcd"; 167 168 ports { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 172 tcon0_in: port@0 { 173 reg = <0>; 174 175 tcon0_in_mixer0: endpoint { 176 remote-endpoint = <&mixer0_out_tcon0>; 177 }; 178 }; 179 180 tcon0_out: port@1 { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 reg = <1>; 184 185 tcon0_out_hdmi: endpoint@1 { 186 reg = <1>; 187 remote-endpoint = <&hdmi_in_tcon0>; 188 }; 189 }; 190 }; 191 }; 192 193 mmc0: mmc@1c0f000 { 194 /* compatible and clocks are in per SoC .dtsi file */ 195 reg = <0x01c0f000 0x1000>; 196 pinctrl-names = "default"; 197 pinctrl-0 = <&mmc0_pins>; 198 resets = <&ccu RST_BUS_MMC0>; 199 reset-names = "ahb"; 200 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 201 status = "disabled"; 202 #address-cells = <1>; 203 #size-cells = <0>; 204 }; 205 206 mmc1: mmc@1c10000 { 207 /* compatible and clocks are in per SoC .dtsi file */ 208 reg = <0x01c10000 0x1000>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&mmc1_pins>; 211 resets = <&ccu RST_BUS_MMC1>; 212 reset-names = "ahb"; 213 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 214 status = "disabled"; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 }; 218 219 mmc2: mmc@1c11000 { 220 /* compatible and clocks are in per SoC .dtsi file */ 221 reg = <0x01c11000 0x1000>; 222 resets = <&ccu RST_BUS_MMC2>; 223 reset-names = "ahb"; 224 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 225 status = "disabled"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 }; 229 230 sid: eeprom@1c14000 { 231 /* compatible is in per SoC .dtsi file */ 232 reg = <0x1c14000 0x400>; 233 }; 234 235 usb_otg: usb@1c19000 { 236 compatible = "allwinner,sun8i-h3-musb"; 237 reg = <0x01c19000 0x400>; 238 clocks = <&ccu CLK_BUS_OTG>; 239 resets = <&ccu RST_BUS_OTG>; 240 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 241 interrupt-names = "mc"; 242 phys = <&usbphy 0>; 243 phy-names = "usb"; 244 extcon = <&usbphy 0>; 245 dr_mode = "otg"; 246 status = "disabled"; 247 }; 248 249 usbphy: phy@1c19400 { 250 compatible = "allwinner,sun8i-h3-usb-phy"; 251 reg = <0x01c19400 0x2c>, 252 <0x01c1a800 0x4>, 253 <0x01c1b800 0x4>, 254 <0x01c1c800 0x4>, 255 <0x01c1d800 0x4>; 256 reg-names = "phy_ctrl", 257 "pmu0", 258 "pmu1", 259 "pmu2", 260 "pmu3"; 261 clocks = <&ccu CLK_USB_PHY0>, 262 <&ccu CLK_USB_PHY1>, 263 <&ccu CLK_USB_PHY2>, 264 <&ccu CLK_USB_PHY3>; 265 clock-names = "usb0_phy", 266 "usb1_phy", 267 "usb2_phy", 268 "usb3_phy"; 269 resets = <&ccu RST_USB_PHY0>, 270 <&ccu RST_USB_PHY1>, 271 <&ccu RST_USB_PHY2>, 272 <&ccu RST_USB_PHY3>; 273 reset-names = "usb0_reset", 274 "usb1_reset", 275 "usb2_reset", 276 "usb3_reset"; 277 status = "disabled"; 278 #phy-cells = <1>; 279 }; 280 281 ehci0: usb@1c1a000 { 282 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 283 reg = <0x01c1a000 0x100>; 284 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 285 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>; 286 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 287 status = "disabled"; 288 }; 289 290 ohci0: usb@1c1a400 { 291 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 292 reg = <0x01c1a400 0x100>; 293 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>, 295 <&ccu CLK_USB_OHCI0>; 296 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>; 297 status = "disabled"; 298 }; 299 300 ehci1: usb@1c1b000 { 301 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 302 reg = <0x01c1b000 0x100>; 303 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 304 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>; 305 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 306 phys = <&usbphy 1>; 307 phy-names = "usb"; 308 status = "disabled"; 309 }; 310 311 ohci1: usb@1c1b400 { 312 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 313 reg = <0x01c1b400 0x100>; 314 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>, 316 <&ccu CLK_USB_OHCI1>; 317 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>; 318 phys = <&usbphy 1>; 319 phy-names = "usb"; 320 status = "disabled"; 321 }; 322 323 ehci2: usb@1c1c000 { 324 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 325 reg = <0x01c1c000 0x100>; 326 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 327 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>; 328 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 329 phys = <&usbphy 2>; 330 phy-names = "usb"; 331 status = "disabled"; 332 }; 333 334 ohci2: usb@1c1c400 { 335 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 336 reg = <0x01c1c400 0x100>; 337 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>, 339 <&ccu CLK_USB_OHCI2>; 340 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>; 341 phys = <&usbphy 2>; 342 phy-names = "usb"; 343 status = "disabled"; 344 }; 345 346 ehci3: usb@1c1d000 { 347 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci"; 348 reg = <0x01c1d000 0x100>; 349 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 350 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>; 351 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 352 phys = <&usbphy 3>; 353 phy-names = "usb"; 354 status = "disabled"; 355 }; 356 357 ohci3: usb@1c1d400 { 358 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci"; 359 reg = <0x01c1d400 0x100>; 360 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 361 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>, 362 <&ccu CLK_USB_OHCI3>; 363 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>; 364 phys = <&usbphy 3>; 365 phy-names = "usb"; 366 status = "disabled"; 367 }; 368 369 ccu: clock@1c20000 { 370 /* compatible is in per SoC .dtsi file */ 371 reg = <0x01c20000 0x400>; 372 clocks = <&osc24M>, <&rtc 0>; 373 clock-names = "hosc", "losc"; 374 #clock-cells = <1>; 375 #reset-cells = <1>; 376 }; 377 378 pio: pinctrl@1c20800 { 379 /* compatible is in per SoC .dtsi file */ 380 reg = <0x01c20800 0x400>; 381 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 383 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&rtc 0>; 384 clock-names = "apb", "hosc", "losc"; 385 gpio-controller; 386 #gpio-cells = <3>; 387 interrupt-controller; 388 #interrupt-cells = <3>; 389 390 csi_pins: csi-pins { 391 pins = "PE0", "PE2", "PE3", "PE4", "PE5", 392 "PE6", "PE7", "PE8", "PE9", "PE10", 393 "PE11"; 394 function = "csi"; 395 }; 396 397 emac_rgmii_pins: emac-rgmii-pins { 398 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 399 "PD5", "PD7", "PD8", "PD9", "PD10", 400 "PD12", "PD13", "PD15", "PD16", "PD17"; 401 function = "emac"; 402 drive-strength = <40>; 403 }; 404 405 i2c0_pins: i2c0-pins { 406 pins = "PA11", "PA12"; 407 function = "i2c0"; 408 }; 409 410 i2c1_pins: i2c1-pins { 411 pins = "PA18", "PA19"; 412 function = "i2c1"; 413 }; 414 415 i2c2_pins: i2c2-pins { 416 pins = "PE12", "PE13"; 417 function = "i2c2"; 418 }; 419 420 mmc0_pins: mmc0-pins { 421 pins = "PF0", "PF1", "PF2", "PF3", 422 "PF4", "PF5"; 423 function = "mmc0"; 424 drive-strength = <30>; 425 bias-pull-up; 426 }; 427 428 mmc1_pins: mmc1-pins { 429 pins = "PG0", "PG1", "PG2", "PG3", 430 "PG4", "PG5"; 431 function = "mmc1"; 432 drive-strength = <30>; 433 bias-pull-up; 434 }; 435 436 mmc2_8bit_pins: mmc2-8bit-pins { 437 pins = "PC5", "PC6", "PC8", 438 "PC9", "PC10", "PC11", 439 "PC12", "PC13", "PC14", 440 "PC15", "PC16"; 441 function = "mmc2"; 442 drive-strength = <30>; 443 bias-pull-up; 444 }; 445 446 spdif_tx_pin: spdif-tx-pin { 447 pins = "PA17"; 448 function = "spdif"; 449 }; 450 451 spi0_pins: spi0-pins { 452 pins = "PC0", "PC1", "PC2", "PC3"; 453 function = "spi0"; 454 }; 455 456 spi1_pins: spi1-pins { 457 pins = "PA15", "PA16", "PA14", "PA13"; 458 function = "spi1"; 459 }; 460 461 uart0_pa_pins: uart0-pa-pins { 462 pins = "PA4", "PA5"; 463 function = "uart0"; 464 }; 465 466 uart1_pins: uart1-pins { 467 pins = "PG6", "PG7"; 468 function = "uart1"; 469 }; 470 471 uart1_rts_cts_pins: uart1-rts-cts-pins { 472 pins = "PG8", "PG9"; 473 function = "uart1"; 474 }; 475 476 uart2_pins: uart2-pins { 477 pins = "PA0", "PA1"; 478 function = "uart2"; 479 }; 480 481 uart3_pins: uart3-pins { 482 pins = "PA13", "PA14"; 483 function = "uart3"; 484 }; 485 486 uart3_rts_cts_pins: uart3-rts-cts-pins { 487 pins = "PA15", "PA16"; 488 function = "uart3"; 489 }; 490 }; 491 492 timer@1c20c00 { 493 compatible = "allwinner,sun8i-a23-timer"; 494 reg = <0x01c20c00 0xa0>; 495 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 497 clocks = <&osc24M>; 498 }; 499 500 emac: ethernet@1c30000 { 501 compatible = "allwinner,sun8i-h3-emac"; 502 syscon = <&syscon>; 503 reg = <0x01c30000 0x10000>; 504 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "macirq"; 506 resets = <&ccu RST_BUS_EMAC>; 507 reset-names = "stmmaceth"; 508 clocks = <&ccu CLK_BUS_EMAC>; 509 clock-names = "stmmaceth"; 510 status = "disabled"; 511 512 mdio: mdio { 513 #address-cells = <1>; 514 #size-cells = <0>; 515 compatible = "snps,dwmac-mdio"; 516 }; 517 518 mdio-mux { 519 compatible = "allwinner,sun8i-h3-mdio-mux"; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 523 mdio-parent-bus = <&mdio>; 524 /* Only one MDIO is usable at the time */ 525 internal_mdio: mdio@1 { 526 compatible = "allwinner,sun8i-h3-mdio-internal"; 527 reg = <1>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 531 int_mii_phy: ethernet-phy@1 { 532 compatible = "ethernet-phy-ieee802.3-c22"; 533 reg = <1>; 534 clocks = <&ccu CLK_BUS_EPHY>; 535 resets = <&ccu RST_BUS_EPHY>; 536 }; 537 }; 538 539 external_mdio: mdio@2 { 540 reg = <2>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 }; 544 }; 545 }; 546 547 spi0: spi@1c68000 { 548 compatible = "allwinner,sun8i-h3-spi"; 549 reg = <0x01c68000 0x1000>; 550 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 551 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 552 clock-names = "ahb", "mod"; 553 dmas = <&dma 23>, <&dma 23>; 554 dma-names = "rx", "tx"; 555 pinctrl-names = "default"; 556 pinctrl-0 = <&spi0_pins>; 557 resets = <&ccu RST_BUS_SPI0>; 558 status = "disabled"; 559 #address-cells = <1>; 560 #size-cells = <0>; 561 }; 562 563 spi1: spi@1c69000 { 564 compatible = "allwinner,sun8i-h3-spi"; 565 reg = <0x01c69000 0x1000>; 566 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 568 clock-names = "ahb", "mod"; 569 dmas = <&dma 24>, <&dma 24>; 570 dma-names = "rx", "tx"; 571 pinctrl-names = "default"; 572 pinctrl-0 = <&spi1_pins>; 573 resets = <&ccu RST_BUS_SPI1>; 574 status = "disabled"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 }; 578 579 wdt0: watchdog@1c20ca0 { 580 compatible = "allwinner,sun6i-a31-wdt"; 581 reg = <0x01c20ca0 0x20>; 582 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 583 clocks = <&osc24M>; 584 }; 585 586 spdif: spdif@1c21000 { 587 #sound-dai-cells = <0>; 588 compatible = "allwinner,sun8i-h3-spdif"; 589 reg = <0x01c21000 0x400>; 590 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 592 resets = <&ccu RST_BUS_SPDIF>; 593 clock-names = "apb", "spdif"; 594 dmas = <&dma 2>; 595 dma-names = "tx"; 596 status = "disabled"; 597 }; 598 599 pwm: pwm@1c21400 { 600 compatible = "allwinner,sun8i-h3-pwm"; 601 reg = <0x01c21400 0x8>; 602 clocks = <&osc24M>; 603 #pwm-cells = <3>; 604 status = "disabled"; 605 }; 606 607 i2s0: i2s@1c22000 { 608 #sound-dai-cells = <0>; 609 compatible = "allwinner,sun8i-h3-i2s"; 610 reg = <0x01c22000 0x400>; 611 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>; 613 clock-names = "apb", "mod"; 614 dmas = <&dma 3>, <&dma 3>; 615 resets = <&ccu RST_BUS_I2S0>; 616 dma-names = "rx", "tx"; 617 status = "disabled"; 618 }; 619 620 i2s1: i2s@1c22400 { 621 #sound-dai-cells = <0>; 622 compatible = "allwinner,sun8i-h3-i2s"; 623 reg = <0x01c22400 0x400>; 624 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 626 clock-names = "apb", "mod"; 627 dmas = <&dma 4>, <&dma 4>; 628 resets = <&ccu RST_BUS_I2S1>; 629 dma-names = "rx", "tx"; 630 status = "disabled"; 631 }; 632 633 codec: codec@1c22c00 { 634 #sound-dai-cells = <0>; 635 compatible = "allwinner,sun8i-h3-codec"; 636 reg = <0x01c22c00 0x400>; 637 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 638 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>; 639 clock-names = "apb", "codec"; 640 resets = <&ccu RST_BUS_CODEC>; 641 dmas = <&dma 15>, <&dma 15>; 642 dma-names = "rx", "tx"; 643 allwinner,codec-analog-controls = <&codec_analog>; 644 status = "disabled"; 645 }; 646 647 uart0: serial@1c28000 { 648 compatible = "snps,dw-apb-uart"; 649 reg = <0x01c28000 0x400>; 650 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 651 reg-shift = <2>; 652 reg-io-width = <4>; 653 clocks = <&ccu CLK_BUS_UART0>; 654 resets = <&ccu RST_BUS_UART0>; 655 dmas = <&dma 6>, <&dma 6>; 656 dma-names = "rx", "tx"; 657 status = "disabled"; 658 }; 659 660 uart1: serial@1c28400 { 661 compatible = "snps,dw-apb-uart"; 662 reg = <0x01c28400 0x400>; 663 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 664 reg-shift = <2>; 665 reg-io-width = <4>; 666 clocks = <&ccu CLK_BUS_UART1>; 667 resets = <&ccu RST_BUS_UART1>; 668 dmas = <&dma 7>, <&dma 7>; 669 dma-names = "rx", "tx"; 670 status = "disabled"; 671 }; 672 673 uart2: serial@1c28800 { 674 compatible = "snps,dw-apb-uart"; 675 reg = <0x01c28800 0x400>; 676 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 677 reg-shift = <2>; 678 reg-io-width = <4>; 679 clocks = <&ccu CLK_BUS_UART2>; 680 resets = <&ccu RST_BUS_UART2>; 681 dmas = <&dma 8>, <&dma 8>; 682 dma-names = "rx", "tx"; 683 status = "disabled"; 684 }; 685 686 uart3: serial@1c28c00 { 687 compatible = "snps,dw-apb-uart"; 688 reg = <0x01c28c00 0x400>; 689 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 690 reg-shift = <2>; 691 reg-io-width = <4>; 692 clocks = <&ccu CLK_BUS_UART3>; 693 resets = <&ccu RST_BUS_UART3>; 694 dmas = <&dma 9>, <&dma 9>; 695 dma-names = "rx", "tx"; 696 status = "disabled"; 697 }; 698 699 i2c0: i2c@1c2ac00 { 700 compatible = "allwinner,sun6i-a31-i2c"; 701 reg = <0x01c2ac00 0x400>; 702 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 703 clocks = <&ccu CLK_BUS_I2C0>; 704 resets = <&ccu RST_BUS_I2C0>; 705 pinctrl-names = "default"; 706 pinctrl-0 = <&i2c0_pins>; 707 status = "disabled"; 708 #address-cells = <1>; 709 #size-cells = <0>; 710 }; 711 712 i2c1: i2c@1c2b000 { 713 compatible = "allwinner,sun6i-a31-i2c"; 714 reg = <0x01c2b000 0x400>; 715 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&ccu CLK_BUS_I2C1>; 717 resets = <&ccu RST_BUS_I2C1>; 718 pinctrl-names = "default"; 719 pinctrl-0 = <&i2c1_pins>; 720 status = "disabled"; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 }; 724 725 i2c2: i2c@1c2b400 { 726 compatible = "allwinner,sun6i-a31-i2c"; 727 reg = <0x01c2b400 0x400>; 728 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 729 clocks = <&ccu CLK_BUS_I2C2>; 730 resets = <&ccu RST_BUS_I2C2>; 731 pinctrl-names = "default"; 732 pinctrl-0 = <&i2c2_pins>; 733 status = "disabled"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 }; 737 738 gic: interrupt-controller@1c81000 { 739 compatible = "arm,gic-400"; 740 reg = <0x01c81000 0x1000>, 741 <0x01c82000 0x2000>, 742 <0x01c84000 0x2000>, 743 <0x01c86000 0x2000>; 744 interrupt-controller; 745 #interrupt-cells = <3>; 746 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 747 }; 748 749 csi: camera@1cb0000 { 750 compatible = "allwinner,sun8i-h3-csi"; 751 reg = <0x01cb0000 0x1000>; 752 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&ccu CLK_BUS_CSI>, 754 <&ccu CLK_CSI_SCLK>, 755 <&ccu CLK_DRAM_CSI>; 756 clock-names = "bus", "mod", "ram"; 757 resets = <&ccu RST_BUS_CSI>; 758 pinctrl-names = "default"; 759 pinctrl-0 = <&csi_pins>; 760 status = "disabled"; 761 }; 762 763 hdmi: hdmi@1ee0000 { 764 compatible = "allwinner,sun8i-h3-dw-hdmi", 765 "allwinner,sun8i-a83t-dw-hdmi"; 766 reg = <0x01ee0000 0x10000>; 767 reg-io-width = <1>; 768 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 770 <&ccu CLK_HDMI>; 771 clock-names = "iahb", "isfr", "tmds"; 772 resets = <&ccu RST_BUS_HDMI1>; 773 reset-names = "ctrl"; 774 phys = <&hdmi_phy>; 775 phy-names = "phy"; 776 status = "disabled"; 777 778 ports { 779 #address-cells = <1>; 780 #size-cells = <0>; 781 782 hdmi_in: port@0 { 783 reg = <0>; 784 785 hdmi_in_tcon0: endpoint { 786 remote-endpoint = <&tcon0_out_hdmi>; 787 }; 788 }; 789 790 hdmi_out: port@1 { 791 reg = <1>; 792 }; 793 }; 794 }; 795 796 hdmi_phy: hdmi-phy@1ef0000 { 797 compatible = "allwinner,sun8i-h3-hdmi-phy"; 798 reg = <0x01ef0000 0x10000>; 799 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>, 800 <&ccu 6>; 801 clock-names = "bus", "mod", "pll-0"; 802 resets = <&ccu RST_BUS_HDMI0>; 803 reset-names = "phy"; 804 #phy-cells = <0>; 805 }; 806 807 rtc: rtc@1f00000 { 808 /* compatible is in per SoC .dtsi file */ 809 reg = <0x01f00000 0x400>; 810 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 811 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 812 clock-output-names = "osc32k", "osc32k-out", "iosc"; 813 clocks = <&osc32k>; 814 #clock-cells = <1>; 815 }; 816 817 r_ccu: clock@1f01400 { 818 compatible = "allwinner,sun8i-h3-r-ccu"; 819 reg = <0x01f01400 0x100>; 820 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, <&ccu 9>; 821 clock-names = "hosc", "losc", "iosc", "pll-periph"; 822 #clock-cells = <1>; 823 #reset-cells = <1>; 824 }; 825 826 codec_analog: codec-analog@1f015c0 { 827 compatible = "allwinner,sun8i-h3-codec-analog"; 828 reg = <0x01f015c0 0x4>; 829 }; 830 831 ir: ir@1f02000 { 832 compatible = "allwinner,sun6i-a31-ir"; 833 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>; 834 clock-names = "apb", "ir"; 835 resets = <&r_ccu RST_APB0_IR>; 836 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 837 reg = <0x01f02000 0x400>; 838 status = "disabled"; 839 }; 840 841 r_i2c: i2c@1f02400 { 842 compatible = "allwinner,sun6i-a31-i2c"; 843 reg = <0x01f02400 0x400>; 844 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 845 pinctrl-names = "default"; 846 pinctrl-0 = <&r_i2c_pins>; 847 clocks = <&r_ccu CLK_APB0_I2C>; 848 resets = <&r_ccu RST_APB0_I2C>; 849 status = "disabled"; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 }; 853 854 r_pio: pinctrl@1f02c00 { 855 compatible = "allwinner,sun8i-h3-r-pinctrl"; 856 reg = <0x01f02c00 0x400>; 857 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 858 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&rtc 0>; 859 clock-names = "apb", "hosc", "losc"; 860 gpio-controller; 861 #gpio-cells = <3>; 862 interrupt-controller; 863 #interrupt-cells = <3>; 864 865 r_ir_rx_pin: r-ir-rx-pin { 866 pins = "PL11"; 867 function = "s_cir_rx"; 868 }; 869 870 r_i2c_pins: r-i2c-pins { 871 pins = "PL0", "PL1"; 872 function = "s_i2c"; 873 }; 874 }; 875 }; 876}; 877
