1/* 2 * Copyright 2012-2015 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This library is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This library is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun5i-ccu.h> 46#include <dt-bindings/dma/sun4i-a10.h> 47#include <dt-bindings/reset/sun5i-ccu.h> 48 49/ { 50 interrupt-parent = <&intc>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a8"; 61 reg = <0x0>; 62 clocks = <&ccu CLK_CPU>; 63 }; 64 }; 65 66 chosen { 67 #address-cells = <1>; 68 #size-cells = <1>; 69 ranges; 70 71 framebuffer-lcd0 { 72 compatible = "allwinner,simple-framebuffer", 73 "simple-framebuffer"; 74 allwinner,pipeline = "de_be0-lcd0"; 75 clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, 76 <&ccu CLK_TCON_CH0>, <&ccu CLK_DRAM_DE_BE>; 77 status = "disabled"; 78 }; 79 80 framebuffer-lcd0-tve0 { 81 compatible = "allwinner,simple-framebuffer", 82 "simple-framebuffer"; 83 allwinner,pipeline = "de_be0-lcd0-tve0"; 84 clocks = <&ccu CLK_AHB_TVE>, <&ccu CLK_AHB_LCD>, 85 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, 86 <&ccu CLK_TCON_CH1>, <&ccu CLK_DRAM_DE_BE>; 87 status = "disabled"; 88 }; 89 }; 90 91 clocks { 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges; 95 96 osc24M: clk-24M { 97 #clock-cells = <0>; 98 compatible = "fixed-clock"; 99 clock-frequency = <24000000>; 100 clock-output-names = "osc24M"; 101 }; 102 103 osc32k: clk-32k { 104 #clock-cells = <0>; 105 compatible = "fixed-clock"; 106 clock-frequency = <32768>; 107 clock-output-names = "osc32k"; 108 }; 109 }; 110 111 reserved-memory { 112 #address-cells = <1>; 113 #size-cells = <1>; 114 ranges; 115 116 /* Address must be kept in the lower 256 MiBs of DRAM for VE. */ 117 default-pool { 118 compatible = "shared-dma-pool"; 119 size = <0x6000000>; 120 alloc-ranges = <0x4a000000 0x6000000>; 121 reusable; 122 linux,cma-default; 123 }; 124 }; 125 126 soc { 127 compatible = "simple-bus"; 128 #address-cells = <1>; 129 #size-cells = <1>; 130 dma-ranges; 131 ranges; 132 133 system-control@1c00000 { 134 compatible = "allwinner,sun5i-a13-system-control"; 135 reg = <0x01c00000 0x30>; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 ranges; 139 140 sram_a: sram@0 { 141 compatible = "mmio-sram"; 142 reg = <0x00000000 0xc000>; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 ranges = <0 0x00000000 0xc000>; 146 147 emac_sram: sram-section@8000 { 148 compatible = "allwinner,sun5i-a13-sram-a3-a4", 149 "allwinner,sun4i-a10-sram-a3-a4"; 150 reg = <0x8000 0x4000>; 151 status = "disabled"; 152 }; 153 }; 154 155 sram_d: sram@10000 { 156 compatible = "mmio-sram"; 157 reg = <0x00010000 0x1000>; 158 #address-cells = <1>; 159 #size-cells = <1>; 160 ranges = <0 0x00010000 0x1000>; 161 162 otg_sram: sram-section@0 { 163 compatible = "allwinner,sun5i-a13-sram-d", 164 "allwinner,sun4i-a10-sram-d"; 165 reg = <0x0000 0x1000>; 166 status = "disabled"; 167 }; 168 }; 169 170 sram_c: sram@1d00000 { 171 compatible = "mmio-sram"; 172 reg = <0x01d00000 0xd0000>; 173 #address-cells = <1>; 174 #size-cells = <1>; 175 ranges = <0 0x01d00000 0xd0000>; 176 177 ve_sram: sram-section@0 { 178 compatible = "allwinner,sun5i-a13-sram-c1", 179 "allwinner,sun4i-a10-sram-c1"; 180 reg = <0x000000 0x80000>; 181 }; 182 }; 183 }; 184 185 mbus: dram-controller@1c01000 { 186 compatible = "allwinner,sun5i-a13-mbus"; 187 reg = <0x01c01000 0x1000>; 188 clocks = <&ccu 99>; 189 dma-ranges = <0x00000000 0x40000000 0x20000000>; 190 #interconnect-cells = <1>; 191 }; 192 193 dma: dma-controller@1c02000 { 194 compatible = "allwinner,sun4i-a10-dma"; 195 reg = <0x01c02000 0x1000>; 196 interrupts = <27>; 197 clocks = <&ccu CLK_AHB_DMA>; 198 #dma-cells = <2>; 199 }; 200 201 nfc: nand-controller@1c03000 { 202 compatible = "allwinner,sun4i-a10-nand"; 203 reg = <0x01c03000 0x1000>; 204 interrupts = <37>; 205 clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>; 206 clock-names = "ahb", "mod"; 207 dmas = <&dma SUN4I_DMA_DEDICATED 3>; 208 dma-names = "rxtx"; 209 status = "disabled"; 210 #address-cells = <1>; 211 #size-cells = <0>; 212 }; 213 214 spi0: spi@1c05000 { 215 compatible = "allwinner,sun4i-a10-spi"; 216 reg = <0x01c05000 0x1000>; 217 interrupts = <10>; 218 clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>; 219 clock-names = "ahb", "mod"; 220 dmas = <&dma SUN4I_DMA_DEDICATED 27>, 221 <&dma SUN4I_DMA_DEDICATED 26>; 222 dma-names = "rx", "tx"; 223 status = "disabled"; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 }; 227 228 spi1: spi@1c06000 { 229 compatible = "allwinner,sun4i-a10-spi"; 230 reg = <0x01c06000 0x1000>; 231 interrupts = <11>; 232 clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>; 233 clock-names = "ahb", "mod"; 234 dmas = <&dma SUN4I_DMA_DEDICATED 9>, 235 <&dma SUN4I_DMA_DEDICATED 8>; 236 dma-names = "rx", "tx"; 237 status = "disabled"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 }; 241 242 tve0: tv-encoder@1c0a000 { 243 compatible = "allwinner,sun4i-a10-tv-encoder"; 244 reg = <0x01c0a000 0x1000>; 245 clocks = <&ccu CLK_AHB_TVE>; 246 resets = <&ccu RST_TVE>; 247 status = "disabled"; 248 249 port { 250 251 tve0_in_tcon0: endpoint { 252 remote-endpoint = <&tcon0_out_tve0>; 253 }; 254 }; 255 }; 256 257 emac: ethernet@1c0b000 { 258 compatible = "allwinner,sun4i-a10-emac"; 259 reg = <0x01c0b000 0x1000>; 260 interrupts = <55>; 261 clocks = <&ccu CLK_AHB_EMAC>; 262 allwinner,sram = <&emac_sram 1>; 263 status = "disabled"; 264 }; 265 266 mdio: mdio@1c0b080 { 267 compatible = "allwinner,sun4i-a10-mdio"; 268 reg = <0x01c0b080 0x14>; 269 status = "disabled"; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 }; 273 274 tcon0: lcd-controller@1c0c000 { 275 compatible = "allwinner,sun5i-a13-tcon"; 276 reg = <0x01c0c000 0x1000>; 277 interrupts = <44>; 278 resets = <&ccu RST_LCD>; 279 reset-names = "lcd"; 280 clocks = <&ccu CLK_AHB_LCD>, 281 <&ccu CLK_TCON_CH0>, 282 <&ccu CLK_TCON_CH1>; 283 clock-names = "ahb", 284 "tcon-ch0", 285 "tcon-ch1"; 286 clock-output-names = "tcon-pixel-clock"; 287 #clock-cells = <0>; 288 status = "disabled"; 289 290 ports { 291 #address-cells = <1>; 292 #size-cells = <0>; 293 294 tcon0_in: port@0 { 295 reg = <0>; 296 297 tcon0_in_be0: endpoint { 298 remote-endpoint = <&be0_out_tcon0>; 299 }; 300 }; 301 302 tcon0_out: port@1 { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 reg = <1>; 306 307 tcon0_out_tve0: endpoint@1 { 308 reg = <1>; 309 remote-endpoint = <&tve0_in_tcon0>; 310 allwinner,tcon-channel = <1>; 311 }; 312 }; 313 }; 314 }; 315 316 video-codec@1c0e000 { 317 compatible = "allwinner,sun5i-a13-video-engine"; 318 reg = <0x01c0e000 0x1000>; 319 clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>, 320 <&ccu CLK_DRAM_VE>; 321 clock-names = "ahb", "mod", "ram"; 322 resets = <&ccu RST_VE>; 323 interrupts = <53>; 324 allwinner,sram = <&ve_sram 1>; 325 }; 326 327 mmc0: mmc@1c0f000 { 328 compatible = "allwinner,sun5i-a13-mmc"; 329 reg = <0x01c0f000 0x1000>; 330 clocks = <&ccu CLK_AHB_MMC0>, <&ccu CLK_MMC0>; 331 clock-names = "ahb", "mmc"; 332 interrupts = <32>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&mmc0_pins>; 335 status = "disabled"; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 }; 339 340 mmc1: mmc@1c10000 { 341 compatible = "allwinner,sun5i-a13-mmc"; 342 reg = <0x01c10000 0x1000>; 343 clocks = <&ccu CLK_AHB_MMC1>, <&ccu CLK_MMC1>; 344 clock-names = "ahb", "mmc"; 345 interrupts = <33>; 346 status = "disabled"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 }; 350 351 mmc2: mmc@1c11000 { 352 compatible = "allwinner,sun5i-a13-mmc"; 353 reg = <0x01c11000 0x1000>; 354 clocks = <&ccu CLK_AHB_MMC2>, <&ccu CLK_MMC2>; 355 clock-names = "ahb", "mmc"; 356 interrupts = <34>; 357 status = "disabled"; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 }; 361 362 usb_otg: usb@1c13000 { 363 compatible = "allwinner,sun4i-a10-musb"; 364 reg = <0x01c13000 0x0400>; 365 clocks = <&ccu CLK_AHB_OTG>; 366 interrupts = <38>; 367 interrupt-names = "mc"; 368 phys = <&usbphy 0>; 369 phy-names = "usb"; 370 extcon = <&usbphy 0>; 371 allwinner,sram = <&otg_sram 1>; 372 dr_mode = "otg"; 373 status = "disabled"; 374 }; 375 376 usbphy: phy@1c13400 { 377 #phy-cells = <1>; 378 compatible = "allwinner,sun5i-a13-usb-phy"; 379 reg = <0x01c13400 0x10>, <0x01c14800 0x4>; 380 reg-names = "phy_ctrl", "pmu1"; 381 clocks = <&ccu CLK_USB_PHY0>; 382 clock-names = "usb_phy"; 383 resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>; 384 reset-names = "usb0_reset", "usb1_reset"; 385 status = "disabled"; 386 }; 387 388 ehci0: usb@1c14000 { 389 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci"; 390 reg = <0x01c14000 0x100>; 391 interrupts = <39>; 392 clocks = <&ccu CLK_AHB_EHCI>; 393 phys = <&usbphy 1>; 394 phy-names = "usb"; 395 status = "disabled"; 396 }; 397 398 ohci0: usb@1c14400 { 399 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci"; 400 reg = <0x01c14400 0x100>; 401 interrupts = <40>; 402 clocks = <&ccu CLK_USB_OHCI>, <&ccu CLK_AHB_OHCI>; 403 phys = <&usbphy 1>; 404 phy-names = "usb"; 405 status = "disabled"; 406 }; 407 408 crypto: crypto-engine@1c15000 { 409 compatible = "allwinner,sun5i-a13-crypto", 410 "allwinner,sun4i-a10-crypto"; 411 reg = <0x01c15000 0x1000>; 412 interrupts = <54>; 413 clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>; 414 clock-names = "ahb", "mod"; 415 }; 416 417 spi2: spi@1c17000 { 418 compatible = "allwinner,sun4i-a10-spi"; 419 reg = <0x01c17000 0x1000>; 420 interrupts = <12>; 421 clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>; 422 clock-names = "ahb", "mod"; 423 dmas = <&dma SUN4I_DMA_DEDICATED 29>, 424 <&dma SUN4I_DMA_DEDICATED 28>; 425 dma-names = "rx", "tx"; 426 status = "disabled"; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 }; 430 431 ccu: clock@1c20000 { 432 reg = <0x01c20000 0x400>; 433 clocks = <&osc24M>, <&osc32k>; 434 clock-names = "hosc", "losc"; 435 #clock-cells = <1>; 436 #reset-cells = <1>; 437 }; 438 439 intc: interrupt-controller@1c20400 { 440 compatible = "allwinner,sun4i-a10-ic"; 441 reg = <0x01c20400 0x400>; 442 interrupt-controller; 443 #interrupt-cells = <1>; 444 }; 445 446 pio: pinctrl@1c20800 { 447 reg = <0x01c20800 0x400>; 448 interrupts = <28>; 449 clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>; 450 clock-names = "apb", "hosc", "losc"; 451 gpio-controller; 452 interrupt-controller; 453 #interrupt-cells = <3>; 454 #gpio-cells = <3>; 455 456 emac_pd_pins: emac-pd-pins { 457 pins = "PD6", "PD7", "PD10", 458 "PD11", "PD12", "PD13", "PD14", 459 "PD15", "PD18", "PD19", "PD20", 460 "PD21", "PD22", "PD23", "PD24", 461 "PD25", "PD26", "PD27"; 462 function = "emac"; 463 }; 464 465 i2c0_pins: i2c0-pins { 466 pins = "PB0", "PB1"; 467 function = "i2c0"; 468 }; 469 470 i2c1_pins: i2c1-pins { 471 pins = "PB15", "PB16"; 472 function = "i2c1"; 473 }; 474 475 i2c2_pins: i2c2-pins { 476 pins = "PB17", "PB18"; 477 function = "i2c2"; 478 }; 479 480 ir0_rx_pin: ir0-rx-pin { 481 pins = "PB4"; 482 function = "ir0"; 483 }; 484 485 lcd_rgb565_pins: lcd-rgb565-pins { 486 pins = "PD3", "PD4", "PD5", "PD6", "PD7", 487 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 488 "PD19", "PD20", "PD21", "PD22", "PD23", 489 "PD24", "PD25", "PD26", "PD27"; 490 function = "lcd0"; 491 }; 492 493 lcd_rgb666_pins: lcd-rgb666-pins { 494 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", 495 "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", 496 "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", 497 "PD24", "PD25", "PD26", "PD27"; 498 function = "lcd0"; 499 }; 500 501 mmc0_pins: mmc0-pins { 502 pins = "PF0", "PF1", "PF2", "PF3", 503 "PF4", "PF5"; 504 function = "mmc0"; 505 drive-strength = <30>; 506 bias-pull-up; 507 }; 508 509 mmc2_4bit_pc_pins: mmc2-4bit-pc-pins { 510 pins = "PC6", "PC7", "PC8", "PC9", 511 "PC10", "PC11"; 512 function = "mmc2"; 513 drive-strength = <30>; 514 bias-pull-up; 515 }; 516 517 mmc2_8bit_pins: mmc2-8bit-pins { 518 pins = "PC6", "PC7", "PC8", "PC9", 519 "PC10", "PC11", "PC12", "PC13", 520 "PC14", "PC15"; 521 function = "mmc2"; 522 drive-strength = <30>; 523 bias-pull-up; 524 }; 525 526 nand_pins: nand-pins { 527 pins = "PC0", "PC1", "PC2", 528 "PC5", "PC8", "PC9", "PC10", 529 "PC11", "PC12", "PC13", "PC14", 530 "PC15"; 531 function = "nand0"; 532 }; 533 534 nand_cs0_pin: nand-cs0-pin { 535 pins = "PC4"; 536 function = "nand0"; 537 }; 538 539 nand_rb0_pin: nand-rb0-pin { 540 pins = "PC6"; 541 function = "nand0"; 542 }; 543 544 pwm0_pin: pwm0-pin { 545 pins = "PB2"; 546 function = "pwm"; 547 }; 548 549 spi2_pe_pins: spi2-pe-pins { 550 pins = "PE1", "PE2", "PE3"; 551 function = "spi2"; 552 }; 553 554 spi2_cs0_pe_pin: spi2-cs0-pe-pin { 555 pins = "PE0"; 556 function = "spi2"; 557 }; 558 559 uart1_pe_pins: uart1-pe-pins { 560 pins = "PE10", "PE11"; 561 function = "uart1"; 562 }; 563 564 uart1_pg_pins: uart1-pg-pins { 565 pins = "PG3", "PG4"; 566 function = "uart1"; 567 }; 568 569 uart2_pd_pins: uart2-pd-pins { 570 pins = "PD2", "PD3"; 571 function = "uart2"; 572 }; 573 574 uart2_cts_rts_pd_pins: uart2-cts-rts-pd-pins { 575 pins = "PD4", "PD5"; 576 function = "uart2"; 577 }; 578 579 uart3_pg_pins: uart3-pg-pins { 580 pins = "PG9", "PG10"; 581 function = "uart3"; 582 }; 583 584 uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins { 585 pins = "PG11", "PG12"; 586 function = "uart3"; 587 }; 588 }; 589 590 timer@1c20c00 { 591 compatible = "allwinner,sun4i-a10-timer"; 592 reg = <0x01c20c00 0x90>; 593 interrupts = <22>, 594 <23>, 595 <24>, 596 <25>, 597 <67>, 598 <68>; 599 clocks = <&ccu CLK_HOSC>; 600 }; 601 602 wdt: watchdog@1c20c90 { 603 compatible = "allwinner,sun4i-a10-wdt"; 604 reg = <0x01c20c90 0x10>; 605 interrupts = <24>; 606 clocks = <&osc24M>; 607 }; 608 609 ir0: ir@1c21800 { 610 compatible = "allwinner,sun4i-a10-ir"; 611 clocks = <&ccu CLK_APB0_IR>, <&ccu CLK_IR>; 612 clock-names = "apb", "ir"; 613 interrupts = <5>; 614 reg = <0x01c21800 0x40>; 615 status = "disabled"; 616 }; 617 618 lradc: lradc@1c22800 { 619 compatible = "allwinner,sun4i-a10-lradc-keys"; 620 reg = <0x01c22800 0x100>; 621 interrupts = <31>; 622 status = "disabled"; 623 }; 624 625 codec: codec@1c22c00 { 626 #sound-dai-cells = <0>; 627 compatible = "allwinner,sun4i-a10-codec"; 628 reg = <0x01c22c00 0x40>; 629 interrupts = <30>; 630 clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>; 631 clock-names = "apb", "codec"; 632 dmas = <&dma SUN4I_DMA_NORMAL 19>, 633 <&dma SUN4I_DMA_NORMAL 19>; 634 dma-names = "rx", "tx"; 635 status = "disabled"; 636 }; 637 638 sid: eeprom@1c23800 { 639 compatible = "allwinner,sun4i-a10-sid"; 640 reg = <0x01c23800 0x10>; 641 }; 642 643 rtp: rtp@1c25000 { 644 compatible = "allwinner,sun5i-a13-ts"; 645 reg = <0x01c25000 0x100>; 646 interrupts = <29>; 647 #thermal-sensor-cells = <0>; 648 }; 649 650 uart0: serial@1c28000 { 651 compatible = "snps,dw-apb-uart"; 652 reg = <0x01c28000 0x400>; 653 interrupts = <1>; 654 reg-shift = <2>; 655 reg-io-width = <4>; 656 clocks = <&ccu CLK_APB1_UART0>; 657 status = "disabled"; 658 }; 659 660 uart1: serial@1c28400 { 661 compatible = "snps,dw-apb-uart"; 662 reg = <0x01c28400 0x400>; 663 interrupts = <2>; 664 reg-shift = <2>; 665 reg-io-width = <4>; 666 clocks = <&ccu CLK_APB1_UART1>; 667 status = "disabled"; 668 }; 669 670 uart2: serial@1c28800 { 671 compatible = "snps,dw-apb-uart"; 672 reg = <0x01c28800 0x400>; 673 interrupts = <3>; 674 reg-shift = <2>; 675 reg-io-width = <4>; 676 clocks = <&ccu CLK_APB1_UART2>; 677 status = "disabled"; 678 }; 679 680 uart3: serial@1c28c00 { 681 compatible = "snps,dw-apb-uart"; 682 reg = <0x01c28c00 0x400>; 683 interrupts = <4>; 684 reg-shift = <2>; 685 reg-io-width = <4>; 686 clocks = <&ccu CLK_APB1_UART3>; 687 status = "disabled"; 688 }; 689 690 i2c0: i2c@1c2ac00 { 691 compatible = "allwinner,sun4i-a10-i2c"; 692 reg = <0x01c2ac00 0x400>; 693 interrupts = <7>; 694 clocks = <&ccu CLK_APB1_I2C0>; 695 pinctrl-names = "default"; 696 pinctrl-0 = <&i2c0_pins>; 697 status = "disabled"; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 }; 701 702 i2c1: i2c@1c2b000 { 703 compatible = "allwinner,sun4i-a10-i2c"; 704 reg = <0x01c2b000 0x400>; 705 interrupts = <8>; 706 clocks = <&ccu CLK_APB1_I2C1>; 707 pinctrl-names = "default"; 708 pinctrl-0 = <&i2c1_pins>; 709 status = "disabled"; 710 #address-cells = <1>; 711 #size-cells = <0>; 712 }; 713 714 i2c2: i2c@1c2b400 { 715 compatible = "allwinner,sun4i-a10-i2c"; 716 reg = <0x01c2b400 0x400>; 717 interrupts = <9>; 718 clocks = <&ccu CLK_APB1_I2C2>; 719 pinctrl-names = "default"; 720 pinctrl-0 = <&i2c2_pins>; 721 status = "disabled"; 722 #address-cells = <1>; 723 #size-cells = <0>; 724 }; 725 726 timer@1c60000 { 727 compatible = "allwinner,sun5i-a13-hstimer"; 728 reg = <0x01c60000 0x1000>; 729 interrupts = <82>, <83>; 730 clocks = <&ccu CLK_AHB_HSTIMER>; 731 }; 732 733 fe0: display-frontend@1e00000 { 734 compatible = "allwinner,sun5i-a13-display-frontend"; 735 reg = <0x01e00000 0x20000>; 736 interrupts = <47>; 737 clocks = <&ccu CLK_DE_FE>, <&ccu CLK_DE_FE>, 738 <&ccu CLK_DRAM_DE_FE>; 739 clock-names = "ahb", "mod", 740 "ram"; 741 resets = <&ccu RST_DE_FE>; 742 interconnects = <&mbus 19>; 743 interconnect-names = "dma-mem"; 744 status = "disabled"; 745 746 ports { 747 #address-cells = <1>; 748 #size-cells = <0>; 749 750 fe0_out: port@1 { 751 reg = <1>; 752 753 fe0_out_be0: endpoint { 754 remote-endpoint = <&be0_in_fe0>; 755 }; 756 }; 757 }; 758 }; 759 760 be0: display-backend@1e60000 { 761 compatible = "allwinner,sun5i-a13-display-backend"; 762 reg = <0x01e60000 0x10000>; 763 interrupts = <47>; 764 clocks = <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>, 765 <&ccu CLK_DRAM_DE_BE>; 766 clock-names = "ahb", "mod", 767 "ram"; 768 resets = <&ccu RST_DE_BE>; 769 interconnects = <&mbus 18>; 770 interconnect-names = "dma-mem"; 771 status = "disabled"; 772 773 assigned-clocks = <&ccu CLK_DE_BE>; 774 assigned-clock-rates = <300000000>; 775 776 ports { 777 #address-cells = <1>; 778 #size-cells = <0>; 779 780 be0_in: port@0 { 781 reg = <0>; 782 783 be0_in_fe0: endpoint { 784 remote-endpoint = <&fe0_out_be0>; 785 }; 786 }; 787 788 be0_out: port@1 { 789 reg = <1>; 790 791 be0_out_tcon0: endpoint { 792 remote-endpoint = <&tcon0_in_be0>; 793 }; 794 }; 795 }; 796 }; 797 }; 798}; 799
