1/* 2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com> 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43#include "armv7-m.dtsi" 44#include <dt-bindings/clock/stm32h7-clks.h> 45#include <dt-bindings/mfd/stm32h7-rcc.h> 46#include <dt-bindings/interrupt-controller/irq.h> 47 48/ { 49 #address-cells = <1>; 50 #size-cells = <1>; 51 52 clocks { 53 clk_hse: clk-hse { 54 #clock-cells = <0>; 55 compatible = "fixed-clock"; 56 clock-frequency = <0>; 57 }; 58 59 clk_lse: clk-lse { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <32768>; 63 }; 64 65 clk_i2s: i2s_ckin { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <0>; 69 }; 70 }; 71 72 soc { 73 timer5: timer@40000c00 { 74 compatible = "st,stm32-timer"; 75 reg = <0x40000c00 0x400>; 76 interrupts = <50>; 77 clocks = <&rcc TIM5_CK>; 78 }; 79 80 lptimer1: timer@40002400 { 81 #address-cells = <1>; 82 #size-cells = <0>; 83 compatible = "st,stm32-lptimer"; 84 reg = <0x40002400 0x400>; 85 clocks = <&rcc LPTIM1_CK>; 86 clock-names = "mux"; 87 status = "disabled"; 88 89 pwm { 90 compatible = "st,stm32-pwm-lp"; 91 #pwm-cells = <3>; 92 status = "disabled"; 93 }; 94 95 trigger@0 { 96 compatible = "st,stm32-lptimer-trigger"; 97 reg = <0>; 98 status = "disabled"; 99 }; 100 101 counter { 102 compatible = "st,stm32-lptimer-counter"; 103 status = "disabled"; 104 }; 105 }; 106 107 spi2: spi@40003800 { 108 #address-cells = <1>; 109 #size-cells = <0>; 110 compatible = "st,stm32h7-spi"; 111 reg = <0x40003800 0x400>; 112 interrupts = <36>; 113 clocks = <&rcc SPI2_CK>; 114 status = "disabled"; 115 116 }; 117 118 spi3: spi@40003c00 { 119 #address-cells = <1>; 120 #size-cells = <0>; 121 compatible = "st,stm32h7-spi"; 122 reg = <0x40003c00 0x400>; 123 interrupts = <51>; 124 clocks = <&rcc SPI3_CK>; 125 status = "disabled"; 126 }; 127 128 usart2: serial@40004400 { 129 compatible = "st,stm32f7-uart"; 130 reg = <0x40004400 0x400>; 131 interrupts = <38>; 132 status = "disabled"; 133 clocks = <&rcc USART2_CK>; 134 }; 135 136 i2c1: i2c@40005400 { 137 compatible = "st,stm32f7-i2c"; 138 #address-cells = <1>; 139 #size-cells = <0>; 140 reg = <0x40005400 0x400>; 141 interrupts = <31>, 142 <32>; 143 resets = <&rcc STM32H7_APB1L_RESET(I2C1)>; 144 clocks = <&rcc I2C1_CK>; 145 status = "disabled"; 146 }; 147 148 i2c2: i2c@40005800 { 149 compatible = "st,stm32f7-i2c"; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 reg = <0x40005800 0x400>; 153 interrupts = <33>, 154 <34>; 155 resets = <&rcc STM32H7_APB1L_RESET(I2C2)>; 156 clocks = <&rcc I2C2_CK>; 157 status = "disabled"; 158 }; 159 160 i2c3: i2c@40005C00 { 161 compatible = "st,stm32f7-i2c"; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 reg = <0x40005C00 0x400>; 165 interrupts = <72>, 166 <73>; 167 resets = <&rcc STM32H7_APB1L_RESET(I2C3)>; 168 clocks = <&rcc I2C3_CK>; 169 status = "disabled"; 170 }; 171 172 dac: dac@40007400 { 173 compatible = "st,stm32h7-dac-core"; 174 reg = <0x40007400 0x400>; 175 clocks = <&rcc DAC12_CK>; 176 clock-names = "pclk"; 177 #address-cells = <1>; 178 #size-cells = <0>; 179 status = "disabled"; 180 181 dac1: dac@1 { 182 compatible = "st,stm32-dac"; 183 #io-channels-cells = <1>; 184 reg = <1>; 185 status = "disabled"; 186 }; 187 188 dac2: dac@2 { 189 compatible = "st,stm32-dac"; 190 #io-channels-cells = <1>; 191 reg = <2>; 192 status = "disabled"; 193 }; 194 }; 195 196 usart1: serial@40011000 { 197 compatible = "st,stm32f7-uart"; 198 reg = <0x40011000 0x400>; 199 interrupts = <37>; 200 status = "disabled"; 201 clocks = <&rcc USART1_CK>; 202 }; 203 204 spi1: spi@40013000 { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 compatible = "st,stm32h7-spi"; 208 reg = <0x40013000 0x400>; 209 interrupts = <35>; 210 clocks = <&rcc SPI1_CK>; 211 status = "disabled"; 212 }; 213 214 spi4: spi@40013400 { 215 #address-cells = <1>; 216 #size-cells = <0>; 217 compatible = "st,stm32h7-spi"; 218 reg = <0x40013400 0x400>; 219 interrupts = <84>; 220 clocks = <&rcc SPI4_CK>; 221 status = "disabled"; 222 }; 223 224 spi5: spi@40015000 { 225 #address-cells = <1>; 226 #size-cells = <0>; 227 compatible = "st,stm32h7-spi"; 228 reg = <0x40015000 0x400>; 229 interrupts = <85>; 230 clocks = <&rcc SPI5_CK>; 231 status = "disabled"; 232 }; 233 234 dma1: dma@40020000 { 235 compatible = "st,stm32-dma"; 236 reg = <0x40020000 0x400>; 237 interrupts = <11>, 238 <12>, 239 <13>, 240 <14>, 241 <15>, 242 <16>, 243 <17>, 244 <47>; 245 clocks = <&rcc DMA1_CK>; 246 #dma-cells = <4>; 247 st,mem2mem; 248 dma-requests = <8>; 249 status = "disabled"; 250 }; 251 252 dma2: dma@40020400 { 253 compatible = "st,stm32-dma"; 254 reg = <0x40020400 0x400>; 255 interrupts = <56>, 256 <57>, 257 <58>, 258 <59>, 259 <60>, 260 <68>, 261 <69>, 262 <70>; 263 clocks = <&rcc DMA2_CK>; 264 #dma-cells = <4>; 265 st,mem2mem; 266 dma-requests = <8>; 267 status = "disabled"; 268 }; 269 270 dmamux1: dma-router@40020800 { 271 compatible = "st,stm32h7-dmamux"; 272 reg = <0x40020800 0x1c>; 273 #dma-cells = <3>; 274 dma-channels = <16>; 275 dma-requests = <128>; 276 dma-masters = <&dma1 &dma2>; 277 clocks = <&rcc DMA1_CK>; 278 }; 279 280 adc_12: adc@40022000 { 281 compatible = "st,stm32h7-adc-core"; 282 reg = <0x40022000 0x400>; 283 interrupts = <18>; 284 clocks = <&rcc ADC12_CK>; 285 clock-names = "bus"; 286 interrupt-controller; 287 #interrupt-cells = <1>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 status = "disabled"; 291 292 adc1: adc@0 { 293 compatible = "st,stm32h7-adc"; 294 #io-channel-cells = <1>; 295 reg = <0x0>; 296 interrupt-parent = <&adc_12>; 297 interrupts = <0>; 298 status = "disabled"; 299 }; 300 301 adc2: adc@100 { 302 compatible = "st,stm32h7-adc"; 303 #io-channel-cells = <1>; 304 reg = <0x100>; 305 interrupt-parent = <&adc_12>; 306 interrupts = <1>; 307 status = "disabled"; 308 }; 309 }; 310 311 usbotg_hs: usb@40040000 { 312 compatible = "st,stm32f7-hsotg"; 313 reg = <0x40040000 0x40000>; 314 interrupts = <77>; 315 clocks = <&rcc USB1OTG_CK>; 316 clock-names = "otg"; 317 g-rx-fifo-size = <256>; 318 g-np-tx-fifo-size = <32>; 319 g-tx-fifo-size = <128 128 64 64 64 64 32 32>; 320 status = "disabled"; 321 }; 322 323 usbotg_fs: usb@40080000 { 324 compatible = "st,stm32f4x9-fsotg"; 325 reg = <0x40080000 0x40000>; 326 interrupts = <101>; 327 clocks = <&rcc USB2OTG_CK>; 328 clock-names = "otg"; 329 status = "disabled"; 330 }; 331 332 mdma1: dma@52000000 { 333 compatible = "st,stm32h7-mdma"; 334 reg = <0x52000000 0x1000>; 335 interrupts = <122>; 336 clocks = <&rcc MDMA_CK>; 337 #dma-cells = <5>; 338 dma-channels = <16>; 339 dma-requests = <32>; 340 }; 341 342 sdmmc1: sdmmc@52007000 { 343 compatible = "arm,pl18x", "arm,primecell"; 344 arm,primecell-periphid = <0x10153180>; 345 reg = <0x52007000 0x1000>; 346 interrupts = <49>; 347 interrupt-names = "cmd_irq"; 348 clocks = <&rcc SDMMC1_CK>; 349 clock-names = "apb_pclk"; 350 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; 351 cap-sd-highspeed; 352 cap-mmc-highspeed; 353 max-frequency = <120000000>; 354 }; 355 356 exti: interrupt-controller@58000000 { 357 compatible = "st,stm32h7-exti"; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 reg = <0x58000000 0x400>; 361 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>; 362 }; 363 364 syscfg: system-config@58000400 { 365 compatible = "syscon"; 366 reg = <0x58000400 0x400>; 367 }; 368 369 spi6: spi@58001400 { 370 #address-cells = <1>; 371 #size-cells = <0>; 372 compatible = "st,stm32h7-spi"; 373 reg = <0x58001400 0x400>; 374 interrupts = <86>; 375 clocks = <&rcc SPI6_CK>; 376 status = "disabled"; 377 }; 378 379 i2c4: i2c@58001C00 { 380 compatible = "st,stm32f7-i2c"; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 reg = <0x58001C00 0x400>; 384 interrupts = <95>, 385 <96>; 386 resets = <&rcc STM32H7_APB4_RESET(I2C4)>; 387 clocks = <&rcc I2C4_CK>; 388 status = "disabled"; 389 }; 390 391 lptimer2: timer@58002400 { 392 #address-cells = <1>; 393 #size-cells = <0>; 394 compatible = "st,stm32-lptimer"; 395 reg = <0x58002400 0x400>; 396 clocks = <&rcc LPTIM2_CK>; 397 clock-names = "mux"; 398 status = "disabled"; 399 400 pwm { 401 compatible = "st,stm32-pwm-lp"; 402 #pwm-cells = <3>; 403 status = "disabled"; 404 }; 405 406 trigger@1 { 407 compatible = "st,stm32-lptimer-trigger"; 408 reg = <1>; 409 status = "disabled"; 410 }; 411 412 counter { 413 compatible = "st,stm32-lptimer-counter"; 414 status = "disabled"; 415 }; 416 }; 417 418 lptimer3: timer@58002800 { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 compatible = "st,stm32-lptimer"; 422 reg = <0x58002800 0x400>; 423 clocks = <&rcc LPTIM3_CK>; 424 clock-names = "mux"; 425 status = "disabled"; 426 427 pwm { 428 compatible = "st,stm32-pwm-lp"; 429 #pwm-cells = <3>; 430 status = "disabled"; 431 }; 432 433 trigger@2 { 434 compatible = "st,stm32-lptimer-trigger"; 435 reg = <2>; 436 status = "disabled"; 437 }; 438 }; 439 440 lptimer4: timer@58002c00 { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 compatible = "st,stm32-lptimer"; 444 reg = <0x58002c00 0x400>; 445 clocks = <&rcc LPTIM4_CK>; 446 clock-names = "mux"; 447 status = "disabled"; 448 449 pwm { 450 compatible = "st,stm32-pwm-lp"; 451 #pwm-cells = <3>; 452 status = "disabled"; 453 }; 454 }; 455 456 lptimer5: timer@58003000 { 457 #address-cells = <1>; 458 #size-cells = <0>; 459 compatible = "st,stm32-lptimer"; 460 reg = <0x58003000 0x400>; 461 clocks = <&rcc LPTIM5_CK>; 462 clock-names = "mux"; 463 status = "disabled"; 464 465 pwm { 466 compatible = "st,stm32-pwm-lp"; 467 #pwm-cells = <3>; 468 status = "disabled"; 469 }; 470 }; 471 472 vrefbuf: regulator@58003c00 { 473 compatible = "st,stm32-vrefbuf"; 474 reg = <0x58003C00 0x8>; 475 clocks = <&rcc VREF_CK>; 476 regulator-min-microvolt = <1500000>; 477 regulator-max-microvolt = <2500000>; 478 status = "disabled"; 479 }; 480 481 rtc: rtc@58004000 { 482 compatible = "st,stm32h7-rtc"; 483 reg = <0x58004000 0x400>; 484 clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>; 485 clock-names = "pclk", "rtc_ck"; 486 assigned-clocks = <&rcc RTC_CK>; 487 assigned-clock-parents = <&rcc LSE_CK>; 488 interrupt-parent = <&exti>; 489 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 490 interrupt-names = "alarm"; 491 st,syscfg = <&pwrcfg 0x00 0x100>; 492 status = "disabled"; 493 }; 494 495 rcc: reset-clock-controller@58024400 { 496 compatible = "st,stm32h743-rcc", "st,stm32-rcc"; 497 reg = <0x58024400 0x400>; 498 #clock-cells = <1>; 499 #reset-cells = <1>; 500 clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>; 501 st,syscfg = <&pwrcfg>; 502 }; 503 504 pwrcfg: power-config@58024800 { 505 compatible = "syscon"; 506 reg = <0x58024800 0x400>; 507 }; 508 509 adc_3: adc@58026000 { 510 compatible = "st,stm32h7-adc-core"; 511 reg = <0x58026000 0x400>; 512 interrupts = <127>; 513 clocks = <&rcc ADC3_CK>; 514 clock-names = "bus"; 515 interrupt-controller; 516 #interrupt-cells = <1>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 521 adc3: adc@0 { 522 compatible = "st,stm32h7-adc"; 523 #io-channel-cells = <1>; 524 reg = <0x0>; 525 interrupt-parent = <&adc_3>; 526 interrupts = <0>; 527 status = "disabled"; 528 }; 529 }; 530 531 mac: ethernet@40028000 { 532 compatible = "st,stm32-dwmac", "snps,dwmac-4.10a"; 533 reg = <0x40028000 0x8000>; 534 reg-names = "stmmaceth"; 535 interrupts = <61>; 536 interrupt-names = "macirq"; 537 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx"; 538 clocks = <&rcc ETH1MAC_CK>, <&rcc ETH1TX_CK>, <&rcc ETH1RX_CK>; 539 st,syscon = <&syscfg 0x4>; 540 snps,pbl = <8>; 541 status = "disabled"; 542 }; 543 }; 544}; 545 546&systick { 547 clock-frequency = <250000000>; 548 status = "okay"; 549}; 550
