1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC 4 * 5 * Copyright (C) 2014 Atmel, 6 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> 7 */ 8 9#include <dt-bindings/clock/at91.h> 10#include <dt-bindings/dma/at91.h> 11#include <dt-bindings/pinctrl/at91.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/gpio/gpio.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 model = "Atmel SAMA5D4 family SoC"; 19 compatible = "atmel,sama5d4"; 20 interrupt-parent = <&aic>; 21 22 aliases { 23 serial0 = &usart3; 24 serial1 = &usart4; 25 serial2 = &usart2; 26 serial3 = &usart0; 27 serial4 = &usart1; 28 serial5 = &uart0; 29 serial6 = &uart1; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 gpio3 = &pioD; 34 gpio4 = &pioE; 35 pwm0 = &pwm0; 36 ssc0 = &ssc0; 37 ssc1 = &ssc1; 38 tcb0 = &tcb0; 39 tcb1 = &tcb1; 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 }; 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a5"; 51 reg = <0>; 52 next-level-cache = <&L2>; 53 }; 54 }; 55 56 memory { 57 device_type = "memory"; 58 reg = <0x20000000 0x20000000>; 59 }; 60 61 clocks { 62 slow_xtal: slow_xtal { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 }; 67 68 main_xtal: main_xtal { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <0>; 72 }; 73 74 adc_op_clk: adc_op_clk{ 75 compatible = "fixed-clock"; 76 #clock-cells = <0>; 77 clock-frequency = <1000000>; 78 }; 79 }; 80 81 ns_sram: sram@210000 { 82 compatible = "mmio-sram"; 83 reg = <0x00210000 0x10000>; 84 }; 85 86 ahb { 87 compatible = "simple-bus"; 88 #address-cells = <1>; 89 #size-cells = <1>; 90 ranges; 91 92 nfc_sram: sram@100000 { 93 compatible = "mmio-sram"; 94 no-memory-wc; 95 reg = <0x100000 0x2400>; 96 }; 97 98 usb0: gadget@400000 { 99 #address-cells = <1>; 100 #size-cells = <0>; 101 compatible = "atmel,sama5d3-udc"; 102 reg = <0x00400000 0x100000 103 0xfc02c000 0x4000>; 104 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; 105 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 106 clock-names = "pclk", "hclk"; 107 status = "disabled"; 108 109 ep@0 { 110 reg = <0>; 111 atmel,fifo-size = <64>; 112 atmel,nb-banks = <1>; 113 }; 114 115 ep@1 { 116 reg = <1>; 117 atmel,fifo-size = <1024>; 118 atmel,nb-banks = <3>; 119 atmel,can-dma; 120 atmel,can-isoc; 121 }; 122 123 ep@2 { 124 reg = <2>; 125 atmel,fifo-size = <1024>; 126 atmel,nb-banks = <3>; 127 atmel,can-dma; 128 atmel,can-isoc; 129 }; 130 131 ep@3 { 132 reg = <3>; 133 atmel,fifo-size = <1024>; 134 atmel,nb-banks = <2>; 135 atmel,can-dma; 136 atmel,can-isoc; 137 }; 138 139 ep@4 { 140 reg = <4>; 141 atmel,fifo-size = <1024>; 142 atmel,nb-banks = <2>; 143 atmel,can-dma; 144 atmel,can-isoc; 145 }; 146 147 ep@5 { 148 reg = <5>; 149 atmel,fifo-size = <1024>; 150 atmel,nb-banks = <2>; 151 atmel,can-dma; 152 atmel,can-isoc; 153 }; 154 155 ep@6 { 156 reg = <6>; 157 atmel,fifo-size = <1024>; 158 atmel,nb-banks = <2>; 159 atmel,can-dma; 160 atmel,can-isoc; 161 }; 162 163 ep@7 { 164 reg = <7>; 165 atmel,fifo-size = <1024>; 166 atmel,nb-banks = <2>; 167 atmel,can-dma; 168 atmel,can-isoc; 169 }; 170 171 ep@8 { 172 reg = <8>; 173 atmel,fifo-size = <1024>; 174 atmel,nb-banks = <2>; 175 atmel,can-isoc; 176 }; 177 178 ep@9 { 179 reg = <9>; 180 atmel,fifo-size = <1024>; 181 atmel,nb-banks = <2>; 182 atmel,can-isoc; 183 }; 184 185 ep@10 { 186 reg = <10>; 187 atmel,fifo-size = <1024>; 188 atmel,nb-banks = <2>; 189 atmel,can-isoc; 190 }; 191 192 ep@11 { 193 reg = <11>; 194 atmel,fifo-size = <1024>; 195 atmel,nb-banks = <2>; 196 atmel,can-isoc; 197 }; 198 199 ep@12 { 200 reg = <12>; 201 atmel,fifo-size = <1024>; 202 atmel,nb-banks = <2>; 203 atmel,can-isoc; 204 }; 205 206 ep@13 { 207 reg = <13>; 208 atmel,fifo-size = <1024>; 209 atmel,nb-banks = <2>; 210 atmel,can-isoc; 211 }; 212 213 ep@14 { 214 reg = <14>; 215 atmel,fifo-size = <1024>; 216 atmel,nb-banks = <2>; 217 atmel,can-isoc; 218 }; 219 220 ep@15 { 221 reg = <15>; 222 atmel,fifo-size = <1024>; 223 atmel,nb-banks = <2>; 224 atmel,can-isoc; 225 }; 226 }; 227 228 usb1: ohci@500000 { 229 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 230 reg = <0x00500000 0x100000>; 231 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 232 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 6>; 233 clock-names = "ohci_clk", "hclk", "uhpck"; 234 status = "disabled"; 235 }; 236 237 usb2: ehci@600000 { 238 compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; 239 reg = <0x00600000 0x100000>; 240 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; 241 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 46>; 242 clock-names = "usb_clk", "ehci_clk"; 243 status = "disabled"; 244 }; 245 246 L2: cache-controller@a00000 { 247 compatible = "arm,pl310-cache"; 248 reg = <0x00a00000 0x1000>; 249 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; 250 cache-unified; 251 cache-level = <2>; 252 }; 253 254 ebi: ebi@10000000 { 255 compatible = "atmel,sama5d3-ebi"; 256 #address-cells = <2>; 257 #size-cells = <1>; 258 atmel,smc = <&hsmc>; 259 reg = <0x10000000 0x10000000 260 0x60000000 0x28000000>; 261 ranges = <0x0 0x0 0x10000000 0x10000000 262 0x1 0x0 0x60000000 0x10000000 263 0x2 0x0 0x70000000 0x10000000 264 0x3 0x0 0x80000000 0x8000000>; 265 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; 266 status = "disabled"; 267 268 nand_controller: nand-controller { 269 compatible = "atmel,sama5d3-nand-controller"; 270 atmel,nfc-sram = <&nfc_sram>; 271 atmel,nfc-io = <&nfc_io>; 272 ecc-engine = <&pmecc>; 273 #address-cells = <2>; 274 #size-cells = <1>; 275 ranges; 276 status = "disabled"; 277 }; 278 }; 279 280 nfc_io: nfc-io@90000000 { 281 compatible = "atmel,sama5d3-nfc-io", "syscon"; 282 reg = <0x90000000 0x8000000>; 283 }; 284 285 apb { 286 compatible = "simple-bus"; 287 #address-cells = <1>; 288 #size-cells = <1>; 289 ranges; 290 291 hlcdc: hlcdc@f0000000 { 292 compatible = "atmel,sama5d4-hlcdc"; 293 reg = <0xf0000000 0x4000>; 294 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>; 295 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>; 296 clock-names = "periph_clk","sys_clk", "slow_clk"; 297 status = "disabled"; 298 299 hlcdc-display-controller { 300 compatible = "atmel,hlcdc-display-controller"; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 304 port@0 { 305 #address-cells = <1>; 306 #size-cells = <0>; 307 reg = <0>; 308 }; 309 }; 310 311 hlcdc_pwm: hlcdc-pwm { 312 compatible = "atmel,hlcdc-pwm"; 313 pinctrl-names = "default"; 314 pinctrl-0 = <&pinctrl_lcd_pwm>; 315 #pwm-cells = <3>; 316 }; 317 }; 318 319 dma1: dma-controller@f0004000 { 320 compatible = "atmel,sama5d4-dma"; 321 reg = <0xf0004000 0x200>; 322 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; 323 #dma-cells = <1>; 324 clocks = <&pmc PMC_TYPE_PERIPHERAL 50>; 325 clock-names = "dma_clk"; 326 }; 327 328 isi: isi@f0008000 { 329 compatible = "atmel,at91sam9g45-isi"; 330 reg = <0xf0008000 0x4000>; 331 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>; 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_isi_data_0_7>; 334 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>; 335 clock-names = "isi_clk"; 336 status = "disabled"; 337 port { 338 #address-cells = <1>; 339 #size-cells = <0>; 340 }; 341 }; 342 343 ramc0: ramc@f0010000 { 344 compatible = "atmel,sama5d3-ddramc"; 345 reg = <0xf0010000 0x200>; 346 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 16>; 347 clock-names = "ddrck", "mpddr"; 348 }; 349 350 dma0: dma-controller@f0014000 { 351 compatible = "atmel,sama5d4-dma"; 352 reg = <0xf0014000 0x200>; 353 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; 354 #dma-cells = <1>; 355 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 356 clock-names = "dma_clk"; 357 }; 358 359 pmc: pmc@f0018000 { 360 compatible = "atmel,sama5d4-pmc", "syscon"; 361 reg = <0xf0018000 0x120>; 362 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 363 #clock-cells = <2>; 364 clocks = <&clk32k>, <&main_xtal>; 365 clock-names = "slow_clk", "main_xtal"; 366 }; 367 368 mmc0: mmc@f8000000 { 369 compatible = "atmel,hsmci"; 370 reg = <0xf8000000 0x600>; 371 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; 372 dmas = <&dma1 373 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 374 | AT91_XDMAC_DT_PERID(0))>; 375 dma-names = "rxtx"; 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; 378 status = "disabled"; 379 #address-cells = <1>; 380 #size-cells = <0>; 381 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>; 382 clock-names = "mci_clk"; 383 }; 384 385 uart0: serial@f8004000 { 386 compatible = "atmel,at91sam9260-usart"; 387 reg = <0xf8004000 0x100>; 388 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>; 389 dmas = <&dma0 390 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 391 | AT91_XDMAC_DT_PERID(22))>, 392 <&dma0 393 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 394 | AT91_XDMAC_DT_PERID(23))>; 395 dma-names = "tx", "rx"; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&pinctrl_uart0>; 398 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>; 399 clock-names = "usart"; 400 status = "disabled"; 401 }; 402 403 ssc0: ssc@f8008000 { 404 compatible = "atmel,at91sam9g45-ssc"; 405 reg = <0xf8008000 0x4000>; 406 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>; 407 pinctrl-names = "default"; 408 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 409 dmas = <&dma1 410 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 411 | AT91_XDMAC_DT_PERID(26))>, 412 <&dma1 413 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 414 | AT91_XDMAC_DT_PERID(27))>; 415 dma-names = "tx", "rx"; 416 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>; 417 clock-names = "pclk"; 418 status = "disabled"; 419 }; 420 421 pwm0: pwm@f800c000 { 422 compatible = "atmel,sama5d3-pwm"; 423 reg = <0xf800c000 0x300>; 424 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>; 425 #pwm-cells = <3>; 426 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>; 427 status = "disabled"; 428 }; 429 430 spi0: spi@f8010000 { 431 #address-cells = <1>; 432 #size-cells = <0>; 433 compatible = "atmel,at91rm9200-spi"; 434 reg = <0xf8010000 0x100>; 435 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; 436 dmas = <&dma1 437 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 438 | AT91_XDMAC_DT_PERID(10))>, 439 <&dma1 440 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 441 | AT91_XDMAC_DT_PERID(11))>; 442 dma-names = "tx", "rx"; 443 pinctrl-names = "default"; 444 pinctrl-0 = <&pinctrl_spi0>; 445 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>; 446 clock-names = "spi_clk"; 447 status = "disabled"; 448 }; 449 450 i2c0: i2c@f8014000 { 451 compatible = "atmel,sama5d4-i2c"; 452 reg = <0xf8014000 0x4000>; 453 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; 454 dmas = <&dma1 455 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 456 | AT91_XDMAC_DT_PERID(2))>, 457 <&dma1 458 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 459 | AT91_XDMAC_DT_PERID(3))>; 460 dma-names = "tx", "rx"; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&pinctrl_i2c0>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 466 status = "disabled"; 467 }; 468 469 i2c1: i2c@f8018000 { 470 compatible = "atmel,sama5d4-i2c"; 471 reg = <0xf8018000 0x4000>; 472 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>; 473 dmas = <&dma0 474 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 475 | AT91_XDMAC_DT_PERID(4))>, 476 <&dma0 477 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 478 | AT91_XDMAC_DT_PERID(5))>; 479 dma-names = "tx", "rx"; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&pinctrl_i2c1>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 485 status = "disabled"; 486 }; 487 488 tcb0: timer@f801c000 { 489 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 reg = <0xf801c000 0x100>; 493 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 494 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>, <&clk32k>; 495 clock-names = "t0_clk", "slow_clk"; 496 }; 497 498 macb0: ethernet@f8020000 { 499 compatible = "atmel,sama5d4-gem"; 500 reg = <0xf8020000 0x100>; 501 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pinctrl_macb0_rmii>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_PERIPHERAL 54>; 507 clock-names = "hclk", "pclk"; 508 status = "disabled"; 509 }; 510 511 i2c2: i2c@f8024000 { 512 compatible = "atmel,sama5d4-i2c"; 513 reg = <0xf8024000 0x4000>; 514 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; 515 dmas = <&dma1 516 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 517 | AT91_XDMAC_DT_PERID(6))>, 518 <&dma1 519 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 520 | AT91_XDMAC_DT_PERID(7))>; 521 dma-names = "tx", "rx"; 522 pinctrl-names = "default"; 523 pinctrl-0 = <&pinctrl_i2c2>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>; 527 status = "disabled"; 528 }; 529 530 sfr: sfr@f8028000 { 531 compatible = "atmel,sama5d4-sfr", "syscon"; 532 reg = <0xf8028000 0x60>; 533 }; 534 535 usart0: serial@f802c000 { 536 compatible = "atmel,at91sam9260-usart"; 537 reg = <0xf802c000 0x100>; 538 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 539 dmas = <&dma0 540 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 541 | AT91_XDMAC_DT_PERID(36))>, 542 <&dma0 543 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 544 | AT91_XDMAC_DT_PERID(37))>; 545 dma-names = "tx", "rx"; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>; 548 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 549 clock-names = "usart"; 550 status = "disabled"; 551 }; 552 553 usart1: serial@f8030000 { 554 compatible = "atmel,at91sam9260-usart"; 555 reg = <0xf8030000 0x100>; 556 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 557 dmas = <&dma0 558 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 559 | AT91_XDMAC_DT_PERID(38))>, 560 <&dma0 561 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 562 | AT91_XDMAC_DT_PERID(39))>; 563 dma-names = "tx", "rx"; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>; 566 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 567 clock-names = "usart"; 568 status = "disabled"; 569 }; 570 571 mmc1: mmc@fc000000 { 572 compatible = "atmel,hsmci"; 573 reg = <0xfc000000 0x600>; 574 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; 575 dmas = <&dma1 576 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 577 | AT91_XDMAC_DT_PERID(1))>; 578 dma-names = "rxtx"; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; 581 status = "disabled"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>; 585 clock-names = "mci_clk"; 586 }; 587 588 uart1: serial@fc004000 { 589 compatible = "atmel,at91sam9260-usart"; 590 reg = <0xfc004000 0x100>; 591 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 592 dmas = <&dma0 593 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 594 | AT91_XDMAC_DT_PERID(24))>, 595 <&dma0 596 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 597 | AT91_XDMAC_DT_PERID(25))>; 598 dma-names = "tx", "rx"; 599 pinctrl-names = "default"; 600 pinctrl-0 = <&pinctrl_uart1>; 601 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 602 clock-names = "usart"; 603 status = "disabled"; 604 }; 605 606 usart2: serial@fc008000 { 607 compatible = "atmel,at91sam9260-usart"; 608 reg = <0xfc008000 0x100>; 609 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; 610 dmas = <&dma1 611 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 612 | AT91_XDMAC_DT_PERID(16))>, 613 <&dma1 614 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 615 | AT91_XDMAC_DT_PERID(17))>; 616 dma-names = "tx", "rx"; 617 pinctrl-names = "default"; 618 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; 619 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>; 620 clock-names = "usart"; 621 status = "disabled"; 622 }; 623 624 usart3: serial@fc00c000 { 625 compatible = "atmel,at91sam9260-usart"; 626 reg = <0xfc00c000 0x100>; 627 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; 628 dmas = <&dma1 629 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 630 | AT91_XDMAC_DT_PERID(18))>, 631 <&dma1 632 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 633 | AT91_XDMAC_DT_PERID(19))>; 634 dma-names = "tx", "rx"; 635 pinctrl-names = "default"; 636 pinctrl-0 = <&pinctrl_usart3>; 637 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>; 638 clock-names = "usart"; 639 status = "disabled"; 640 }; 641 642 usart4: serial@fc010000 { 643 compatible = "atmel,at91sam9260-usart"; 644 reg = <0xfc010000 0x100>; 645 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; 646 dmas = <&dma1 647 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 648 | AT91_XDMAC_DT_PERID(20))>, 649 <&dma1 650 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 651 | AT91_XDMAC_DT_PERID(21))>; 652 dma-names = "tx", "rx"; 653 pinctrl-names = "default"; 654 pinctrl-0 = <&pinctrl_usart4>; 655 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>; 656 clock-names = "usart"; 657 status = "disabled"; 658 }; 659 660 ssc1: ssc@fc014000 { 661 compatible = "atmel,at91sam9g45-ssc"; 662 reg = <0xfc014000 0x4000>; 663 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>; 664 pinctrl-names = "default"; 665 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 666 dmas = <&dma1 667 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 668 | AT91_XDMAC_DT_PERID(28))>, 669 <&dma1 670 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 671 | AT91_XDMAC_DT_PERID(29))>; 672 dma-names = "tx", "rx"; 673 clocks = <&pmc PMC_TYPE_PERIPHERAL 49>; 674 clock-names = "pclk"; 675 status = "disabled"; 676 }; 677 678 spi1: spi@fc018000 { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 compatible = "atmel,at91rm9200-spi"; 682 reg = <0xfc018000 0x100>; 683 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>; 684 dmas = <&dma1 685 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 686 | AT91_XDMAC_DT_PERID(12))>, 687 <&dma1 688 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 689 | AT91_XDMAC_DT_PERID(13))>; 690 dma-names = "tx", "rx"; 691 pinctrl-names = "default"; 692 pinctrl-0 = <&pinctrl_spi1>; 693 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 694 clock-names = "spi_clk"; 695 status = "disabled"; 696 }; 697 698 spi2: spi@fc01c000 { 699 #address-cells = <1>; 700 #size-cells = <0>; 701 compatible = "atmel,at91rm9200-spi"; 702 reg = <0xfc01c000 0x100>; 703 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>; 704 dmas = <&dma0 705 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 706 | AT91_XDMAC_DT_PERID(14))>, 707 <&dma0 708 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 709 | AT91_XDMAC_DT_PERID(15))>; 710 dma-names = "tx", "rx"; 711 pinctrl-names = "default"; 712 pinctrl-0 = <&pinctrl_spi2>; 713 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 714 clock-names = "spi_clk"; 715 status = "disabled"; 716 }; 717 718 tcb1: timer@fc020000 { 719 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 reg = <0xfc020000 0x100>; 723 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 724 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&clk32k>; 725 clock-names = "t0_clk", "slow_clk"; 726 }; 727 728 tcb2: timer@fc024000 { 729 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon"; 730 #address-cells = <1>; 731 #size-cells = <0>; 732 reg = <0xfc024000 0x100>; 733 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; 734 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&clk32k>; 735 clock-names = "t0_clk", "slow_clk"; 736 }; 737 738 macb1: ethernet@fc028000 { 739 compatible = "atmel,sama5d4-gem"; 740 reg = <0xfc028000 0x100>; 741 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 3>; 742 pinctrl-names = "default"; 743 pinctrl-0 = <&pinctrl_macb1_rmii>; 744 #address-cells = <1>; 745 #size-cells = <0>; 746 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_PERIPHERAL 55>; 747 clock-names = "hclk", "pclk"; 748 status = "disabled"; 749 }; 750 751 trng@fc030000 { 752 compatible = "atmel,at91sam9g45-trng"; 753 reg = <0xfc030000 0x100>; 754 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 0>; 755 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>; 756 }; 757 758 adc0: adc@fc034000 { 759 compatible = "atmel,at91sam9x5-adc"; 760 reg = <0xfc034000 0x100>; 761 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; 762 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>, 763 <&adc_op_clk>; 764 clock-names = "adc_clk", "adc_op_clk"; 765 atmel,adc-channels-used = <0x01f>; 766 atmel,adc-startup-time = <40>; 767 atmel,adc-use-external-triggers; 768 atmel,adc-vref = <3000>; 769 atmel,adc-res = <8 10>; 770 atmel,adc-sample-hold-time = <11>; 771 atmel,adc-res-names = "lowres", "highres"; 772 atmel,adc-ts-pressure-threshold = <10000>; 773 status = "disabled"; 774 775 trigger0 { 776 trigger-name = "external-rising"; 777 trigger-value = <0x1>; 778 trigger-external; 779 }; 780 trigger1 { 781 trigger-name = "external-falling"; 782 trigger-value = <0x2>; 783 trigger-external; 784 }; 785 trigger2 { 786 trigger-name = "external-any"; 787 trigger-value = <0x3>; 788 trigger-external; 789 }; 790 trigger3 { 791 trigger-name = "continuous"; 792 trigger-value = <0x6>; 793 }; 794 }; 795 796 aes@fc044000 { 797 compatible = "atmel,at91sam9g46-aes"; 798 reg = <0xfc044000 0x100>; 799 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 800 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 801 | AT91_XDMAC_DT_PERID(41))>, 802 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 803 | AT91_XDMAC_DT_PERID(40))>; 804 dma-names = "tx", "rx"; 805 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>; 806 clock-names = "aes_clk"; 807 status = "okay"; 808 }; 809 810 tdes@fc04c000 { 811 compatible = "atmel,at91sam9g46-tdes"; 812 reg = <0xfc04c000 0x100>; 813 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>; 814 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 815 | AT91_XDMAC_DT_PERID(42))>, 816 <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 817 | AT91_XDMAC_DT_PERID(43))>; 818 dma-names = "tx", "rx"; 819 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 820 clock-names = "tdes_clk"; 821 status = "okay"; 822 }; 823 824 sha@fc050000 { 825 compatible = "atmel,at91sam9g46-sha"; 826 reg = <0xfc050000 0x100>; 827 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>; 828 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) 829 | AT91_XDMAC_DT_PERID(44))>; 830 dma-names = "tx"; 831 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 832 clock-names = "sha_clk"; 833 status = "okay"; 834 }; 835 836 hsmc: smc@fc05c000 { 837 compatible = "atmel,sama5d3-smc", "syscon", "simple-mfd"; 838 reg = <0xfc05c000 0x1000>; 839 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; 840 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>; 841 #address-cells = <1>; 842 #size-cells = <1>; 843 ranges; 844 845 pmecc: ecc-engine@ffffc070 { 846 compatible = "atmel,sama5d4-pmecc"; 847 reg = <0xfc05c070 0x490>, 848 <0xfc05c500 0x100>; 849 }; 850 }; 851 852 reset_controller: rstc@fc068600 { 853 compatible = "atmel,sama5d3-rstc", "atmel,at91sam9g45-rstc"; 854 reg = <0xfc068600 0x10>; 855 clocks = <&clk32k>; 856 }; 857 858 shutdown_controller: shdwc@fc068610 { 859 compatible = "atmel,at91sam9x5-shdwc"; 860 reg = <0xfc068610 0x10>; 861 clocks = <&clk32k>; 862 }; 863 864 pit: timer@fc068630 { 865 compatible = "atmel,at91sam9260-pit"; 866 reg = <0xfc068630 0x10>; 867 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; 868 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>; 869 }; 870 871 watchdog: watchdog@fc068640 { 872 compatible = "atmel,sama5d4-wdt"; 873 reg = <0xfc068640 0x10>; 874 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>; 875 clocks = <&clk32k>; 876 status = "disabled"; 877 }; 878 879 clk32k: sckc@fc068650 { 880 compatible = "atmel,sama5d4-sckc"; 881 reg = <0xfc068650 0x4>; 882 #clock-cells = <0>; 883 clocks = <&slow_xtal>; 884 }; 885 886 rtc@fc0686b0 { 887 compatible = "atmel,at91rm9200-rtc"; 888 reg = <0xfc0686b0 0x30>; 889 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 890 clocks = <&clk32k>; 891 }; 892 893 dbgu: serial@fc069000 { 894 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; 895 reg = <0xfc069000 0x200>; 896 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 7>; 897 pinctrl-names = "default"; 898 pinctrl-0 = <&pinctrl_dbgu>; 899 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>; 900 clock-names = "usart"; 901 status = "disabled"; 902 }; 903 904 905 pinctrl: pinctrl@fc06a000 { 906 #address-cells = <1>; 907 #size-cells = <1>; 908 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus"; 909 ranges = <0xfc068000 0xfc068000 0x100 910 0xfc06a000 0xfc06a000 0x4000>; 911 /* WARNING: revisit as pin spec has changed */ 912 atmel,mux-mask = < 913 /* A B C */ 914 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ 915 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ 916 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ 917 0x0003ff00 0x8002a800 0x00000000 /* pioD */ 918 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ 919 >; 920 921 pioA: gpio@fc06a000 { 922 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 923 reg = <0xfc06a000 0x100>; 924 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; 925 #gpio-cells = <2>; 926 gpio-controller; 927 interrupt-controller; 928 #interrupt-cells = <2>; 929 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>; 930 }; 931 932 pioB: gpio@fc06b000 { 933 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 934 reg = <0xfc06b000 0x100>; 935 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; 936 #gpio-cells = <2>; 937 gpio-controller; 938 interrupt-controller; 939 #interrupt-cells = <2>; 940 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>; 941 }; 942 943 pioC: gpio@fc06c000 { 944 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 945 reg = <0xfc06c000 0x100>; 946 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; 947 #gpio-cells = <2>; 948 gpio-controller; 949 interrupt-controller; 950 #interrupt-cells = <2>; 951 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>; 952 }; 953 954 pioD: gpio@fc068000 { 955 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 956 reg = <0xfc068000 0x100>; 957 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 958 #gpio-cells = <2>; 959 gpio-controller; 960 interrupt-controller; 961 #interrupt-cells = <2>; 962 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 963 }; 964 965 pioE: gpio@fc06d000 { 966 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; 967 reg = <0xfc06d000 0x100>; 968 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; 969 #gpio-cells = <2>; 970 gpio-controller; 971 interrupt-controller; 972 #interrupt-cells = <2>; 973 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>; 974 }; 975 976 /* pinctrl pin settings */ 977 adc0 { 978 pinctrl_adc0_adtrg: adc0_adtrg { 979 atmel,pins = 980 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */ 981 }; 982 pinctrl_adc0_ad0: adc0_ad0 { 983 atmel,pins = 984 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 985 }; 986 pinctrl_adc0_ad1: adc0_ad1 { 987 atmel,pins = 988 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 989 }; 990 pinctrl_adc0_ad2: adc0_ad2 { 991 atmel,pins = 992 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 993 }; 994 pinctrl_adc0_ad3: adc0_ad3 { 995 atmel,pins = 996 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 997 }; 998 pinctrl_adc0_ad4: adc0_ad4 { 999 atmel,pins = 1000 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1001 }; 1002 }; 1003 1004 dbgu { 1005 pinctrl_dbgu: dbgu-0 { 1006 atmel,pins = 1007 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* conflicts with D14 and TDI */ 1008 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with D15 and TDO */ 1009 }; 1010 }; 1011 1012 ebi { 1013 pinctrl_ebi_addr: ebi-addr-0 { 1014 atmel,pins = 1015 <AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE 1016 AT91_PIOE 1 AT91_PERIPH_A AT91_PINCTRL_NONE 1017 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE 1018 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE 1019 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE 1020 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE 1021 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE 1022 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE 1023 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE 1024 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE 1025 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE 1026 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE 1027 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE 1028 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE 1029 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE 1030 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE 1031 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE 1032 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE 1033 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE 1034 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE 1035 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE 1036 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE 1037 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE 1038 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE 1039 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE 1040 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1041 }; 1042 1043 pinctrl_ebi_nand_addr: ebi-addr-1 { 1044 atmel,pins = 1045 <AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE 1046 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1047 }; 1048 1049 pinctrl_ebi_cs0: ebi-cs0-0 { 1050 atmel,pins = 1051 <AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1052 }; 1053 1054 pinctrl_ebi_cs1: ebi-cs1-0 { 1055 atmel,pins = 1056 <AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1057 }; 1058 1059 pinctrl_ebi_cs2: ebi-cs2-0 { 1060 atmel,pins = 1061 <AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1062 }; 1063 1064 pinctrl_ebi_cs3: ebi-cs3-0 { 1065 atmel,pins = 1066 <AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1067 }; 1068 1069 pinctrl_ebi_data_0_7: ebi-data-lsb-0 { 1070 atmel,pins = 1071 <AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE 1072 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE 1073 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE 1074 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE 1075 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE 1076 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE 1077 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE 1078 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1079 }; 1080 1081 pinctrl_ebi_data_8_15: ebi-data-msb-0 { 1082 atmel,pins = 1083 <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE 1084 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE 1085 AT91_PIOB 20 AT91_PERIPH_B AT91_PINCTRL_NONE 1086 AT91_PIOB 21 AT91_PERIPH_B AT91_PINCTRL_NONE 1087 AT91_PIOB 22 AT91_PERIPH_B AT91_PINCTRL_NONE 1088 AT91_PIOB 23 AT91_PERIPH_B AT91_PINCTRL_NONE 1089 AT91_PIOB 24 AT91_PERIPH_B AT91_PINCTRL_NONE 1090 AT91_PIOB 25 AT91_PERIPH_B AT91_PINCTRL_NONE>; 1091 }; 1092 1093 pinctrl_ebi_nandrdy: ebi-nandrdy-0 { 1094 atmel,pins = 1095 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1096 }; 1097 1098 pinctrl_ebi_nrd_nandoe: ebi-nrd-nandoe-0 { 1099 atmel,pins = 1100 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1101 }; 1102 1103 pinctrl_ebi_nwait: ebi-nwait-0 { 1104 atmel,pins = 1105 <AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1106 }; 1107 1108 pinctrl_ebi_nwe_nandwe: ebi-nwe-nandwe-0 { 1109 atmel,pins = 1110 <AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1111 }; 1112 1113 pinctrl_ebi_nwr1_nbs1: ebi-nwr1-nbs1-0 { 1114 atmel,pins = 1115 <AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1116 }; 1117 }; 1118 1119 i2c0 { 1120 pinctrl_i2c0: i2c0-0 { 1121 atmel,pins = 1122 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE 1123 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1124 }; 1125 }; 1126 1127 i2c1 { 1128 pinctrl_i2c1: i2c1-0 { 1129 atmel,pins = 1130 <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* TWD1, conflicts with UART0 RX and DIBP */ 1131 AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */ 1132 }; 1133 }; 1134 1135 i2c2 { 1136 pinctrl_i2c2: i2c2-0 { 1137 atmel,pins = 1138 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ 1139 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ 1140 }; 1141 }; 1142 1143 isi { 1144 pinctrl_isi_data_0_7: isi-0-data-0-7 { 1145 atmel,pins = 1146 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D0 */ 1147 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D1 */ 1148 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D2 */ 1149 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D3 */ 1150 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D4 */ 1151 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D5 */ 1152 AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D6 */ 1153 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* ISI_D7 */ 1154 AT91_PIOB 1 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_PCK, conflict with G0_RXCK */ 1155 AT91_PIOB 3 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_VSYNC */ 1156 AT91_PIOB 4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */ 1157 }; 1158 pinctrl_isi_data_8_9: isi-0-data-8-9 { 1159 atmel,pins = 1160 <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */ 1161 AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */ 1162 }; 1163 pinctrl_isi_data_10_11: isi-0-data-10-11 { 1164 atmel,pins = 1165 <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */ 1166 AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */ 1167 }; 1168 }; 1169 1170 lcd { 1171 pinctrl_lcd_base: lcd-base-0 { 1172 atmel,pins = 1173 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDVSYNC */ 1174 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDHSYNC */ 1175 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDDEN */ 1176 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */ 1177 }; 1178 pinctrl_lcd_pwm: lcd-pwm-0 { 1179 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPWM */ 1180 }; 1181 pinctrl_lcd_rgb444: lcd-rgb-0 { 1182 atmel,pins = 1183 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1184 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1185 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1186 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1187 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1188 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1189 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1190 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1191 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1192 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1193 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1194 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */ 1195 }; 1196 pinctrl_lcd_rgb565: lcd-rgb-1 { 1197 atmel,pins = 1198 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1199 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1200 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1201 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1202 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1203 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1204 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1205 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1206 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1207 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1208 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1209 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1210 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1211 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1212 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1213 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */ 1214 }; 1215 pinctrl_lcd_rgb666: lcd-rgb-2 { 1216 atmel,pins = 1217 <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1218 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1219 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1220 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1221 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1222 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1223 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1224 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1225 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1226 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1227 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1228 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1229 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1230 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1231 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1232 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1233 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1234 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1235 }; 1236 pinctrl_lcd_rgb777: lcd-rgb-3 { 1237 atmel,pins = 1238 /* LCDDAT0 conflicts with TMS */ 1239 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1240 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1241 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1242 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1243 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1244 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1245 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1246 /* LCDDAT8 conflicts with TCK */ 1247 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1248 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1249 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1250 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1251 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1252 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1253 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1254 /* LCDDAT16 conflicts with NTRST */ 1255 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ 1256 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1257 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1258 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1259 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1260 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1261 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1262 }; 1263 pinctrl_lcd_rgb888: lcd-rgb-4 { 1264 atmel,pins = 1265 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD0 pin */ 1266 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD1 pin */ 1267 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD2 pin */ 1268 AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD3 pin */ 1269 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD4 pin */ 1270 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD5 pin */ 1271 AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD6 pin */ 1272 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD7 pin */ 1273 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD8 pin */ 1274 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD9 pin */ 1275 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD10 pin */ 1276 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD11 pin */ 1277 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD12 pin */ 1278 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD13 pin */ 1279 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD14 pin */ 1280 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD15 pin */ 1281 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD16 pin */ 1282 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD17 pin */ 1283 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD18 pin */ 1284 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD19 pin */ 1285 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD20 pin */ 1286 AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD21 pin */ 1287 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* LCDD22 pin */ 1288 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */ 1289 }; 1290 }; 1291 1292 macb0 { 1293 pinctrl_macb0_rmii: macb0_rmii-0 { 1294 atmel,pins = 1295 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */ 1296 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */ 1297 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */ 1298 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */ 1299 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */ 1300 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */ 1301 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */ 1302 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */ 1303 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */ 1304 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */ 1305 >; 1306 }; 1307 }; 1308 1309 macb1 { 1310 pinctrl_macb1_rmii: macb1_rmii-0 { 1311 atmel,pins = 1312 <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX0 */ 1313 AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TX1 */ 1314 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX0 */ 1315 AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RX1 */ 1316 AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXDV */ 1317 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_RXER */ 1318 AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXEN */ 1319 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_TXCK */ 1320 AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDC */ 1321 AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* G1_MDIO */ 1322 >; 1323 }; 1324 }; 1325 1326 mmc0 { 1327 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { 1328 atmel,pins = 1329 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */ 1330 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDA, conflict with NAND_D0 */ 1331 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA0, conflict with NAND_D1 */ 1332 >; 1333 }; 1334 pinctrl_mmc0_dat1_3: mmc0_dat1_3 { 1335 atmel,pins = 1336 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA1, conflict with NAND_D2 */ 1337 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA2, conflict with NAND_D3 */ 1338 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA3, conflict with NAND_D4 */ 1339 >; 1340 }; 1341 pinctrl_mmc0_dat4_7: mmc0_dat4_7 { 1342 atmel,pins = 1343 <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA4, conflict with NAND_D5 */ 1344 AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA5, conflict with NAND_D6 */ 1345 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA6, conflict with NAND_D7 */ 1346 AT91_PIOC 13 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DA7, conflict with NAND_OE */ 1347 >; 1348 }; 1349 }; 1350 1351 mmc1 { 1352 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { 1353 atmel,pins = 1354 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */ 1355 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */ 1356 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */ 1357 >; 1358 }; 1359 pinctrl_mmc1_dat1_3: mmc1_dat1_3 { 1360 atmel,pins = 1361 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */ 1362 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */ 1363 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */ 1364 >; 1365 }; 1366 }; 1367 1368 nand0 { 1369 pinctrl_nand: nand-0 { 1370 atmel,pins = 1371 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */ 1372 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */ 1373 1374 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */ 1375 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */ 1376 1377 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */ 1378 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */ 1379 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */ 1380 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */ 1381 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */ 1382 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */ 1383 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */ 1384 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */ 1385 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */ 1386 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */ 1387 }; 1388 }; 1389 1390 spi0 { 1391 pinctrl_spi0: spi0-0 { 1392 atmel,pins = 1393 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */ 1394 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */ 1395 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ 1396 >; 1397 }; 1398 }; 1399 1400 ssc0 { 1401 pinctrl_ssc0_tx: ssc0_tx { 1402 atmel,pins = 1403 <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK0 */ 1404 AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF0 */ 1405 AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */ 1406 }; 1407 1408 pinctrl_ssc0_rx: ssc0_rx { 1409 atmel,pins = 1410 <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK0 */ 1411 AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF0 */ 1412 AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */ 1413 }; 1414 }; 1415 1416 ssc1 { 1417 pinctrl_ssc1_tx: ssc1_tx { 1418 atmel,pins = 1419 <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE /* TK1 */ 1420 AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* TF1 */ 1421 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */ 1422 }; 1423 1424 pinctrl_ssc1_rx: ssc1_rx { 1425 atmel,pins = 1426 <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* RK1 */ 1427 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* RF1 */ 1428 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */ 1429 }; 1430 }; 1431 1432 spi1 { 1433 pinctrl_spi1: spi1-0 { 1434 atmel,pins = 1435 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MISO */ 1436 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_MOSI */ 1437 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI1_SPCK */ 1438 >; 1439 }; 1440 }; 1441 1442 spi2 { 1443 pinctrl_spi2: spi2-0 { 1444 atmel,pins = 1445 <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MISO conflicts with RTS0 */ 1446 AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_MOSI conflicts with TXD0 */ 1447 AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* SPI2_SPCK conflicts with RTS1 */ 1448 >; 1449 }; 1450 }; 1451 1452 uart0 { 1453 pinctrl_uart0: uart0-0 { 1454 atmel,pins = 1455 <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */ 1456 AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */ 1457 >; 1458 }; 1459 }; 1460 1461 uart1 { 1462 pinctrl_uart1: uart1-0 { 1463 atmel,pins = 1464 <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* RXD */ 1465 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE /* TXD */ 1466 >; 1467 }; 1468 }; 1469 1470 usart0 { 1471 pinctrl_usart0: usart0-0 { 1472 atmel,pins = 1473 <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */ 1474 AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */ 1475 >; 1476 }; 1477 pinctrl_usart0_rts: usart0_rts-0 { 1478 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1479 }; 1480 pinctrl_usart0_cts: usart0_cts-0 { 1481 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1482 }; 1483 }; 1484 1485 usart1 { 1486 pinctrl_usart1: usart1-0 { 1487 atmel,pins = 1488 <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* RXD */ 1489 AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* TXD */ 1490 >; 1491 }; 1492 pinctrl_usart1_rts: usart1_rts-0 { 1493 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1494 }; 1495 pinctrl_usart1_cts: usart1_cts-0 { 1496 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; 1497 }; 1498 }; 1499 1500 usart2 { 1501 pinctrl_usart2: usart2-0 { 1502 atmel,pins = 1503 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD - conflicts with G0_CRS, ISI_HSYNC */ 1504 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD - conflicts with G0_COL, PCK2 */ 1505 >; 1506 }; 1507 pinctrl_usart2_rts: usart2_rts-0 { 1508 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */ 1509 }; 1510 pinctrl_usart2_cts: usart2_cts-0 { 1511 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */ 1512 }; 1513 }; 1514 1515 usart3 { 1516 pinctrl_usart3: usart3-0 { 1517 atmel,pins = 1518 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */ 1519 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */ 1520 >; 1521 }; 1522 }; 1523 1524 usart4 { 1525 pinctrl_usart4: usart4-0 { 1526 atmel,pins = 1527 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* RXD */ 1528 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* TXD */ 1529 >; 1530 }; 1531 pinctrl_usart4_rts: usart4_rts-0 { 1532 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */ 1533 }; 1534 pinctrl_usart4_cts: usart4_cts-0 { 1535 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */ 1536 }; 1537 }; 1538 }; 1539 1540 aic: interrupt-controller@fc06e000 { 1541 #interrupt-cells = <3>; 1542 compatible = "atmel,sama5d4-aic"; 1543 interrupt-controller; 1544 reg = <0xfc06e000 0x200>; 1545 atmel,external-irqs = <56>; 1546 }; 1547 }; 1548 }; 1549}; 1550
