1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Veyron Minnie Rev 0+ board device tree source
4 *
5 * Copyright 2015 Google, Inc
6 */
7
8/dts-v1/;
9#include "rk3288-veyron-chromebook.dtsi"
10
11/ {
12	model = "Google Minnie";
13	compatible = "google,veyron-minnie-rev4", "google,veyron-minnie-rev3",
14		     "google,veyron-minnie-rev2", "google,veyron-minnie-rev1",
15		     "google,veyron-minnie-rev0", "google,veyron-minnie",
16		     "google,veyron", "rockchip,rk3288";
17
18	volume_buttons: volume-buttons {
19		compatible = "gpio-keys";
20		pinctrl-names = "default";
21		pinctrl-0 = <&volum_down_l &volum_up_l>;
22
23		volum_down {
24			label = "Volum_down";
25			gpios = <&gpio5 RK_PB3 GPIO_ACTIVE_LOW>;
26			linux,code = <KEY_VOLUMEDOWN>;
27			debounce-interval = <100>;
28		};
29
30		volum_up {
31			label = "Volum_up";
32			gpios = <&gpio5 RK_PB2 GPIO_ACTIVE_LOW>;
33			linux,code = <KEY_VOLUMEUP>;
34			debounce-interval = <100>;
35		};
36	};
37};
38
39&backlight {
40	/* Minnie panel PWM must be >= 1%, so start non-zero brightness at 3 */
41	brightness-levels = <
42			  0   3   4   5   6   7
43			  8   9  10  11  12  13  14  15
44			 16  17  18  19  20  21  22  23
45			 24  25  26  27  28  29  30  31
46			 32  33  34  35  36  37  38  39
47			 40  41  42  43  44  45  46  47
48			 48  49  50  51  52  53  54  55
49			 56  57  58  59  60  61  62  63
50			 64  65  66  67  68  69  70  71
51			 72  73  74  75  76  77  78  79
52			 80  81  82  83  84  85  86  87
53			 88  89  90  91  92  93  94  95
54			 96  97  98  99 100 101 102 103
55			104 105 106 107 108 109 110 111
56			112 113 114 115 116 117 118 119
57			120 121 122 123 124 125 126 127
58			128 129 130 131 132 133 134 135
59			136 137 138 139 140 141 142 143
60			144 145 146 147 148 149 150 151
61			152 153 154 155 156 157 158 159
62			160 161 162 163 164 165 166 167
63			168 169 170 171 172 173 174 175
64			176 177 178 179 180 181 182 183
65			184 185 186 187 188 189 190 191
66			192 193 194 195 196 197 198 199
67			200 201 202 203 204 205 206 207
68			208 209 210 211 212 213 214 215
69			216 217 218 219 220 221 222 223
70			224 225 226 227 228 229 230 231
71			232 233 234 235 236 237 238 239
72			240 241 242 243 244 245 246 247
73			248 249 250 251 252 253 254 255>;
74};
75
76&i2c_tunnel {
77	battery: bq27500@55 {
78		compatible = "ti,bq27500";
79		reg = <0x55>;
80	};
81};
82
83&i2c3 {
84	status = "okay";
85
86	clock-frequency = <400000>;
87	i2c-scl-falling-time-ns = <50>;
88	i2c-scl-rising-time-ns = <300>;
89
90	touchscreen@10 {
91		compatible = "elan,ekth3500";
92		reg = <0x10>;
93		interrupt-parent = <&gpio2>;
94		interrupts = <RK_PB6 IRQ_TYPE_EDGE_FALLING>;
95		pinctrl-names = "default";
96		pinctrl-0 = <&touch_int &touch_rst>;
97		reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
98		vcc33-supply = <&vcc33_touch>;
99		vccio-supply = <&vcc33_touch>;
100	};
101};
102
103&panel {
104	compatible = "auo,b101ean01", "simple-panel";
105
106	/delete-node/ panel-timing;
107
108	panel-timing {
109		clock-frequency = <66666667>;
110		hactive = <1280>;
111		hfront-porch = <18>;
112		hback-porch = <21>;
113		hsync-len = <32>;
114		vactive = <800>;
115		vfront-porch = <4>;
116		vback-porch = <8>;
117		vsync-len = <18>;
118	};
119};
120
121&rk808 {
122	pinctrl-names = "default";
123	pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
124
125	regulators {
126		vcc33_touch: LDO_REG2 {
127			regulator-min-microvolt = <3300000>;
128			regulator-max-microvolt = <3300000>;
129			regulator-name = "vcc33_touch";
130			regulator-state-mem {
131				regulator-off-in-suspend;
132			};
133		};
134
135		vcc5v_touch: SWITCH_REG2 {
136			regulator-name = "vcc5v_touch";
137			regulator-state-mem {
138				regulator-off-in-suspend;
139			};
140		};
141	};
142};
143
144&sdmmc {
145	disable-wp;
146	pinctrl-names = "default";
147	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
148			&sdmmc_bus4>;
149};
150
151&vcc_5v {
152	enable-active-high;
153	gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
154	pinctrl-names = "default";
155	pinctrl-0 = <&drv_5v>;
156};
157
158&vcc50_hdmi {
159	enable-active-high;
160	gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
161	pinctrl-names = "default";
162	pinctrl-0 = <&vcc50_hdmi_en>;
163};
164
165&gpio0 {
166	gpio-line-names = "PMIC_SLEEP_AP",
167			  "DDRIO_PWROFF",
168			  "DDRIO_RETEN",
169			  "TS3A227E_INT_L",
170			  "PMIC_INT_L",
171			  "PWR_KEY_L",
172			  "AP_LID_INT_L",
173			  "EC_IN_RW",
174
175			  "AC_PRESENT_AP",
176			  /*
177			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
178			   * it REC_MODE_L.
179			   */
180			  "RECOVERY_SW_L",
181			  "OTP_OUT",
182			  "HOST1_PWR_EN",
183			  "USBOTG_PWREN_H",
184			  "AP_WARM_RESET_H",
185			  "nFALUT2",
186			  "I2C0_SDA_PMIC",
187
188			  "I2C0_SCL_PMIC",
189			  "SUSPEND_L",
190			  "USB_INT";
191};
192
193&gpio2 {
194	gpio-line-names = "CONFIG0",
195			  "CONFIG1",
196			  "CONFIG2",
197			  "",
198			  "",
199			  "",
200			  "",
201			  "CONFIG3",
202
203			  "PROCHOT#",
204			  "EMMC_RST_L",
205			  "",
206			  "",
207			  "BL_PWR_EN",
208			  "AVDD_1V8_DISP_EN",
209			  "TOUCH_INT",
210			  "TOUCH_RST",
211
212			  "I2C3_SCL_TP",
213			  "I2C3_SDA_TP";
214};
215
216&gpio3 {
217	gpio-line-names = "FLASH0_D0",
218			  "FLASH0_D1",
219			  "FLASH0_D2",
220			  "FLASH0_D3",
221			  "FLASH0_D4",
222			  "FLASH0_D5",
223			  "FLASH0_D6",
224			  "FLASH0_D7",
225
226			  "",
227			  "",
228			  "",
229			  "",
230			  "",
231			  "",
232			  "",
233			  "",
234
235			  "FLASH0_CS2/EMMC_CMD",
236			  "",
237			  "FLASH0_DQS/EMMC_CLKO";
238};
239
240&gpio4 {
241	gpio-line-names = "",
242			  "",
243			  "",
244			  "",
245			  "",
246			  "",
247			  "",
248			  "",
249
250			  "",
251			  "",
252			  "",
253			  "",
254			  "",
255			  "",
256			  "",
257			  "",
258
259			  "UART0_RXD",
260			  "UART0_TXD",
261			  "UART0_CTS",
262			  "UART0_RTS",
263			  "SDIO0_D0",
264			  "SDIO0_D1",
265			  "SDIO0_D2",
266			  "SDIO0_D3",
267
268			  "SDIO0_CMD",
269			  "SDIO0_CLK",
270			  "dev_wake",
271			  "",
272			  "WIFI_ENABLE_H",
273			  "BT_ENABLE_L",
274			  "WIFI_HOST_WAKE",
275			  "BT_HOST_WAKE";
276};
277
278&gpio5 {
279	gpio-line-names = "",
280			  "",
281			  "",
282			  "",
283			  "",
284			  "",
285			  "",
286			  "",
287
288			  "",
289			  "",
290			  "Volum_Up#",
291			  "Volum_Down#",
292			  "SPI0_CLK",
293			  "SPI0_CS0",
294			  "SPI0_TXD",
295			  "SPI0_RXD",
296
297			  "",
298			  "",
299			  "",
300			  "VCC50_HDMI_EN";
301};
302
303&gpio6 {
304	gpio-line-names = "I2S0_SCLK",
305			  "I2S0_LRCK_RX",
306			  "I2S0_LRCK_TX",
307			  "I2S0_SDI",
308			  "I2S0_SDO0",
309			  "HP_DET_H",
310			  "",
311			  "INT_CODEC",
312
313			  "I2S0_CLK",
314			  "I2C2_SDA",
315			  "I2C2_SCL",
316			  "MICDET",
317			  "",
318			  "",
319			  "",
320			  "",
321
322			  "SDMMC_D0",
323			  "SDMMC_D1",
324			  "SDMMC_D2",
325			  "SDMMC_D3",
326			  "SDMMC_CLK",
327			  "SDMMC_CMD";
328};
329
330&gpio7 {
331	gpio-line-names = "LCDC_BL",
332			  "PWM_LOG",
333			  "BL_EN",
334			  "TRACKPAD_INT",
335			  "TPM_INT_H",
336			  "SDMMC_DET_L",
337			  /*
338			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
339			   * it FW_WP_AP.
340			   */
341			  "AP_FLASH_WP_L",
342			  "EC_INT",
343
344			  "CPU_NMI",
345			  "DVS_OK",
346			  "SDMMC_WP",
347			  "EDP_HPD",
348			  "DVS1",
349			  "nFALUT1",
350			  "LCD_EN",
351			  "DVS2",
352
353			  "VCC5V_GOOD_H",
354			  "I2C4_SDA_TP",
355			  "I2C4_SCL_TP",
356			  "I2C5_SDA_HDMI",
357			  "I2C5_SCL_HDMI",
358			  "5V_DRV",
359			  "UART2_RXD",
360			  "UART2_TXD";
361};
362
363&gpio8 {
364	gpio-line-names = "RAM_ID0",
365			  "RAM_ID1",
366			  "RAM_ID2",
367			  "RAM_ID3",
368			  "I2C1_SDA_TPM",
369			  "I2C1_SCL_TPM",
370			  "SPI2_CLK",
371			  "SPI2_CS0",
372
373			  "SPI2_RXD",
374			  "SPI2_TXD";
375};
376
377&pinctrl {
378	buck-5v {
379		drv_5v: drv-5v {
380			rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
381		};
382	};
383
384	buttons {
385		volum_down_l: volum-down-l {
386			rockchip,pins = <5 RK_PB3 RK_FUNC_GPIO &pcfg_pull_up>;
387		};
388
389		volum_up_l: volum-up-l {
390			rockchip,pins = <5 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
391		};
392	};
393
394	hdmi {
395		vcc50_hdmi_en: vcc50-hdmi-en {
396			rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
397		};
398	};
399
400	pmic {
401		dvs_1: dvs-1 {
402			rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
403		};
404
405		dvs_2: dvs-2 {
406			rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
407		};
408	};
409
410	prochot {
411		gpio_prochot: gpio-prochot {
412			rockchip,pins = <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
413		};
414	};
415
416	touchscreen {
417		touch_int: touch-int {
418			rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
419		};
420
421		touch_rst: touch-rst {
422			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
423		};
424	};
425};
426