1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Veyron Jaq Rev 1+ board device tree source
4 *
5 * Copyright 2015 Google, Inc
6 */
7
8/dts-v1/;
9
10#include "rk3288-veyron-chromebook.dtsi"
11#include "cros-ec-sbs.dtsi"
12
13/ {
14	model = "Google Jaq";
15	compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
16		     "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
17		     "google,veyron-jaq-rev1", "google,veyron-jaq",
18		     "google,veyron", "rockchip,rk3288";
19};
20
21&backlight {
22	/* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
23	brightness-levels = <
24		  0
25		  8   9  10  11  12  13  14  15
26		 16  17  18  19  20  21  22  23
27		 24  25  26  27  28  29  30  31
28		 32  33  34  35  36  37  38  39
29		 40  41  42  43  44  45  46  47
30		 48  49  50  51  52  53  54  55
31		 56  57  58  59  60  61  62  63
32		 64  65  66  67  68  69  70  71
33		 72  73  74  75  76  77  78  79
34		 80  81  82  83  84  85  86  87
35		 88  89  90  91  92  93  94  95
36		 96  97  98  99 100 101 102 103
37		104 105 106 107 108 109 110 111
38		112 113 114 115 116 117 118 119
39		120 121 122 123 124 125 126 127
40		128 129 130 131 132 133 134 135
41		136 137 138 139 140 141 142 143
42		144 145 146 147 148 149 150 151
43		152 153 154 155 156 157 158 159
44		160 161 162 163 164 165 166 167
45		168 169 170 171 172 173 174 175
46		176 177 178 179 180 181 182 183
47		184 185 186 187 188 189 190 191
48		192 193 194 195 196 197 198 199
49		200 201 202 203 204 205 206 207
50		208 209 210 211 212 213 214 215
51		216 217 218 219 220 221 222 223
52		224 225 226 227 228 229 230 231
53		232 233 234 235 236 237 238 239
54		240 241 242 243 244 245 246 247
55		248 249 250 251 252 253 254 255>;
56};
57
58&rk808 {
59	pinctrl-names = "default";
60	pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
61	dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
62		    <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
63
64	regulators {
65		mic_vcc: LDO_REG2 {
66			regulator-name = "mic_vcc";
67			regulator-always-on;
68			regulator-boot-on;
69			regulator-min-microvolt = <1800000>;
70			regulator-max-microvolt = <1800000>;
71			regulator-state-mem {
72				regulator-off-in-suspend;
73			};
74		};
75	};
76};
77
78&sdmmc {
79	disable-wp;
80	pinctrl-names = "default";
81	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
82			&sdmmc_bus4>;
83};
84
85&vcc_5v {
86	enable-active-high;
87	gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
88	pinctrl-names = "default";
89	pinctrl-0 = <&drv_5v>;
90};
91
92&vcc50_hdmi {
93	enable-active-high;
94	gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
95	pinctrl-names = "default";
96	pinctrl-0 = <&vcc50_hdmi_en>;
97};
98
99&gpio0 {
100	gpio-line-names = "PMIC_SLEEP_AP",
101			  "DDRIO_PWROFF",
102			  "DDRIO_RETEN",
103			  "TS3A227E_INT_L",
104			  "PMIC_INT_L",
105			  "PWR_KEY_L",
106			  "AP_LID_INT_L",
107			  "EC_IN_RW",
108
109			  "AC_PRESENT_AP",
110			  /*
111			   * RECOVERY_SW_L is Chrome OS ABI.  Schematics call
112			   * it REC_MODE_L.
113			   */
114			  "RECOVERY_SW_L",
115			  "OTP_OUT",
116			  "HOST1_PWR_EN",
117			  "USBOTG_PWREN_H",
118			  "AP_WARM_RESET_H",
119			  "nFALUT2",
120			  "I2C0_SDA_PMIC",
121
122			  "I2C0_SCL_PMIC",
123			  "SUSPEND_L",
124			  "USB_INT";
125};
126
127&gpio2 {
128	gpio-line-names = "CONFIG0",
129			  "CONFIG1",
130			  "CONFIG2",
131			  "",
132			  "",
133			  "",
134			  "",
135			  "CONFIG3",
136
137			  "",
138			  "EMMC_RST_L",
139			  "",
140			  "",
141			  "BL_PWR_EN",
142			  "AVDD_1V8_DISP_EN";
143};
144
145&gpio3 {
146	gpio-line-names = "FLASH0_D0",
147			  "FLASH0_D1",
148			  "FLASH0_D2",
149			  "FLASH0_D3",
150			  "FLASH0_D4",
151			  "FLASH0_D5",
152			  "FLASH0_D6",
153			  "FLASH0_D7",
154
155			  "",
156			  "",
157			  "",
158			  "",
159			  "",
160			  "",
161			  "",
162			  "",
163
164			  "FLASH0_CS2/EMMC_CMD",
165			  "",
166			  "FLASH0_DQS/EMMC_CLKO";
167};
168
169&gpio4 {
170	gpio-line-names = "",
171			  "",
172			  "",
173			  "",
174			  "",
175			  "",
176			  "",
177			  "",
178
179			  "",
180			  "",
181			  "",
182			  "",
183			  "",
184			  "",
185			  "",
186			  "",
187
188			  "UART0_RXD",
189			  "UART0_TXD",
190			  "UART0_CTS",
191			  "UART0_RTS",
192			  "SDIO0_D0",
193			  "SDIO0_D1",
194			  "SDIO0_D2",
195			  "SDIO0_D3",
196
197			  "SDIO0_CMD",
198			  "SDIO0_CLK",
199			  "BT_DEV_WAKE",	/* Maybe missing from mighty? */
200			  "",
201			  "WIFI_ENABLE_H",
202			  "BT_ENABLE_L",
203			  "WIFI_HOST_WAKE",
204			  "BT_HOST_WAKE";
205};
206
207&gpio5 {
208	gpio-line-names = "",
209			  "",
210			  "",
211			  "",
212			  "",
213			  "",
214			  "",
215			  "",
216
217			  "",
218			  "",
219			  "",
220			  "",
221			  "SPI0_CLK",
222			  "SPI0_CS0",
223			  "SPI0_TXD",
224			  "SPI0_RXD",
225
226			  "",
227			  "",
228			  "",
229			  "VCC50_HDMI_EN";
230};
231
232&gpio6 {
233	gpio-line-names = "I2S0_SCLK",
234			  "I2S0_LRCK_RX",
235			  "I2S0_LRCK_TX",
236			  "I2S0_SDI",
237			  "I2S0_SDO0",
238			  "HP_DET_H",
239			  "ALS_INT",
240			  "INT_CODEC",
241
242			  "I2S0_CLK",
243			  "I2C2_SDA",
244			  "I2C2_SCL",
245			  "MICDET",
246			  "",
247			  "",
248			  "",
249			  "",
250
251			  "SDMMC_D0",
252			  "SDMMC_D1",
253			  "SDMMC_D2",
254			  "SDMMC_D3",
255			  "SDMMC_CLK",
256			  "SDMMC_CMD";
257};
258
259&gpio7 {
260	gpio-line-names = "LCDC_BL",
261			  "PWM_LOG",
262			  "BL_EN",
263			  "TRACKPAD_INT",
264			  "TPM_INT_H",
265			  "SDMMC_DET_L",
266			  /*
267			   * AP_FLASH_WP_L is Chrome OS ABI.  Schematics call
268			   * it FW_WP_AP.
269			   */
270			  "AP_FLASH_WP_L",
271			  "EC_INT",
272
273			  "CPU_NMI",
274			  "DVSOK",
275			  "SDMMC_WP",		/* mighty only */
276			  "EDP_HPD",
277			  "DVS1",
278			  "nFALUT1",		/* nFAULT1 on jaq */
279			  "LCD_EN",
280			  "DVS2",
281
282			  "VCC5V_GOOD_H",
283			  "I2C4_SDA_TP",
284			  "I2C4_SCL_TP",
285			  "I2C5_SDA_HDMI",
286			  "I2C5_SCL_HDMI",
287			  "5V_DRV",
288			  "UART2_RXD",
289			  "UART2_TXD";
290};
291
292&gpio8 {
293	gpio-line-names = "RAM_ID0",
294			  "RAM_ID1",
295			  "RAM_ID2",
296			  "RAM_ID3",
297			  "I2C1_SDA_TPM",
298			  "I2C1_SCL_TPM",
299			  "SPI2_CLK",
300			  "SPI2_CS0",
301
302			  "SPI2_RXD",
303			  "SPI2_TXD";
304};
305
306&pinctrl {
307	buck-5v {
308		drv_5v: drv-5v {
309			rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
310		};
311	};
312
313	hdmi {
314		vcc50_hdmi_en: vcc50-hdmi-en {
315			rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
316		};
317	};
318
319	pmic {
320		dvs_1: dvs-1 {
321			rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
322		};
323
324		dvs_2: dvs-2 {
325			rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
326		};
327	};
328};
329