1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Veyron (and derivatives) fragment for the edp displays
4 *
5 * Copyright 2019 Google LLC
6 */
7
8/ {
9	backlight_regulator: backlight-regulator {
10		compatible = "regulator-fixed";
11		enable-active-high;
12		gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
13		pinctrl-names = "default";
14		pinctrl-0 = <&bl_pwr_en>;
15		regulator-name = "backlight_regulator";
16		vin-supply = <&vcc33_sys>;
17		startup-delay-us = <15000>;
18	};
19
20	panel_regulator: panel-regulator {
21		compatible = "regulator-fixed";
22		enable-active-high;
23		gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
24		pinctrl-names = "default";
25		pinctrl-0 = <&lcd_enable_h>;
26		regulator-name = "panel_regulator";
27		vin-supply = <&vcc33_sys>;
28	};
29
30	vcc18_lcd: vcc18-lcd {
31		compatible = "regulator-fixed";
32		enable-active-high;
33		gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
34		pinctrl-names = "default";
35		pinctrl-0 = <&avdd_1v8_disp_en>;
36		regulator-name = "vcc18_lcd";
37		regulator-always-on;
38		regulator-boot-on;
39		vin-supply = <&vcc18_wl>;
40	};
41
42	backlight: backlight {
43		compatible = "pwm-backlight";
44		brightness-levels = <
45			  0   1   2   3   4   5   6   7
46			  8   9  10  11  12  13  14  15
47			 16  17  18  19  20  21  22  23
48			 24  25  26  27  28  29  30  31
49			 32  33  34  35  36  37  38  39
50			 40  41  42  43  44  45  46  47
51			 48  49  50  51  52  53  54  55
52			 56  57  58  59  60  61  62  63
53			 64  65  66  67  68  69  70  71
54			 72  73  74  75  76  77  78  79
55			 80  81  82  83  84  85  86  87
56			 88  89  90  91  92  93  94  95
57			 96  97  98  99 100 101 102 103
58			104 105 106 107 108 109 110 111
59			112 113 114 115 116 117 118 119
60			120 121 122 123 124 125 126 127
61			128 129 130 131 132 133 134 135
62			136 137 138 139 140 141 142 143
63			144 145 146 147 148 149 150 151
64			152 153 154 155 156 157 158 159
65			160 161 162 163 164 165 166 167
66			168 169 170 171 172 173 174 175
67			176 177 178 179 180 181 182 183
68			184 185 186 187 188 189 190 191
69			192 193 194 195 196 197 198 199
70			200 201 202 203 204 205 206 207
71			208 209 210 211 212 213 214 215
72			216 217 218 219 220 221 222 223
73			224 225 226 227 228 229 230 231
74			232 233 234 235 236 237 238 239
75			240 241 242 243 244 245 246 247
76			248 249 250 251 252 253 254 255>;
77		default-brightness-level = <128>;
78		enable-gpios = <&gpio7 RK_PA2 GPIO_ACTIVE_HIGH>;
79		pinctrl-names = "default";
80		pinctrl-0 = <&bl_en>;
81		pwms = <&pwm0 0 1000000 0>;
82		post-pwm-on-delay-ms = <10>;
83		pwm-off-delay-ms = <10>;
84		power-supply = <&backlight_regulator>;
85	};
86
87	panel: panel {
88		compatible = "innolux,n116bge", "simple-panel";
89		status = "okay";
90		power-supply = <&panel_regulator>;
91		backlight = <&backlight>;
92
93		panel-timing {
94			clock-frequency = <74250000>;
95			hactive = <1366>;
96			hfront-porch = <136>;
97			hback-porch = <60>;
98			hsync-len = <30>;
99			hsync-active = <0>;
100			vactive = <768>;
101			vfront-porch = <8>;
102			vback-porch = <12>;
103			vsync-len = <12>;
104			vsync-active = <0>;
105		};
106
107		ports {
108			panel_in: port {
109				panel_in_edp: endpoint {
110					remote-endpoint = <&edp_out_panel>;
111				};
112			};
113		};
114	};
115};
116
117&edp {
118	status = "okay";
119
120	pinctrl-names = "default";
121	pinctrl-0 = <&edp_hpd>;
122
123	ports {
124		edp_out: port@1 {
125			reg = <1>;
126			#address-cells = <1>;
127			#size-cells = <0>;
128			edp_out_panel: endpoint@0 {
129				reg = <0>;
130				remote-endpoint = <&panel_in_edp>;
131			};
132		};
133	};
134};
135
136&edp_phy {
137	status = "okay";
138};
139
140&pwm0 {
141	status = "okay";
142};
143
144&vopl {
145	status = "okay";
146};
147
148&vopl_mmu {
149	status = "okay";
150};
151
152&pinctrl {
153	backlight {
154		bl_pwr_en: bl_pwr_en {
155			rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
156		};
157
158		bl_en: bl-en {
159			rockchip,pins = <7 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
160		};
161	};
162
163	lcd {
164		lcd_enable_h: lcd-en {
165			rockchip,pins = <7 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
166		};
167
168		avdd_1v8_disp_en: avdd-1v8-disp-en {
169			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
170		};
171	};
172};
173