1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
6#include <dt-bindings/bus/ti-sysc.h>
7#include <dt-bindings/clock/omap4.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/pinctrl/omap.h>
11#include <dt-bindings/clock/omap4.h>
12
13/ {
14	compatible = "ti,omap4430", "ti,omap4";
15	interrupt-parent = <&wakeupgen>;
16	#address-cells = <1>;
17	#size-cells = <1>;
18	chosen { };
19
20	aliases {
21		i2c0 = &i2c1;
22		i2c1 = &i2c2;
23		i2c2 = &i2c3;
24		i2c3 = &i2c4;
25		serial0 = &uart1;
26		serial1 = &uart2;
27		serial2 = &uart3;
28		serial3 = &uart4;
29	};
30
31	cpus {
32		#address-cells = <1>;
33		#size-cells = <0>;
34
35		cpu@0 {
36			compatible = "arm,cortex-a9";
37			device_type = "cpu";
38			next-level-cache = <&L2>;
39			reg = <0x0>;
40
41			clocks = <&dpll_mpu_ck>;
42			clock-names = "cpu";
43
44			clock-latency = <300000>; /* From omap-cpufreq driver */
45		};
46		cpu@1 {
47			compatible = "arm,cortex-a9";
48			device_type = "cpu";
49			next-level-cache = <&L2>;
50			reg = <0x1>;
51		};
52	};
53
54	/*
55	 * Note that 4430 needs cross trigger interface (CTI) supported
56	 * before we can configure the interrupts. This means sampling
57	 * events are not supported for pmu. Note that 4460 does not use
58	 * CTI, see also 4460.dtsi.
59	 */
60	pmu {
61		compatible = "arm,cortex-a9-pmu";
62		ti,hwmods = "debugss";
63	};
64
65	gic: interrupt-controller@48241000 {
66		compatible = "arm,cortex-a9-gic";
67		interrupt-controller;
68		#interrupt-cells = <3>;
69		reg = <0x48241000 0x1000>,
70		      <0x48240100 0x0100>;
71		interrupt-parent = <&gic>;
72	};
73
74	L2: l2-cache-controller@48242000 {
75		compatible = "arm,pl310-cache";
76		reg = <0x48242000 0x1000>;
77		cache-unified;
78		cache-level = <2>;
79	};
80
81	local-timer@48240600 {
82		compatible = "arm,cortex-a9-twd-timer";
83		clocks = <&mpu_periphclk>;
84		reg = <0x48240600 0x20>;
85		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
86		interrupt-parent = <&gic>;
87	};
88
89	wakeupgen: interrupt-controller@48281000 {
90		compatible = "ti,omap4-wugen-mpu";
91		interrupt-controller;
92		#interrupt-cells = <3>;
93		reg = <0x48281000 0x1000>;
94		interrupt-parent = <&gic>;
95	};
96
97	/*
98	 * The soc node represents the soc top level view. It is used for IPs
99	 * that are not memory mapped in the MPU view or for the MPU itself.
100	 */
101	soc {
102		compatible = "ti,omap-infra";
103		mpu {
104			compatible = "ti,omap4-mpu";
105			ti,hwmods = "mpu";
106			sram = <&ocmcram>;
107		};
108
109		dsp {
110			compatible = "ti,omap3-c64";
111			ti,hwmods = "dsp";
112		};
113
114		iva {
115			compatible = "ti,ivahd";
116			ti,hwmods = "iva";
117		};
118	};
119
120	/*
121	 * XXX: Use a flat representation of the OMAP4 interconnect.
122	 * The real OMAP interconnect network is quite complex.
123	 * Since it will not bring real advantage to represent that in DT for
124	 * the moment, just use a fake OCP bus entry to represent the whole bus
125	 * hierarchy.
126	 */
127	ocp {
128		compatible = "ti,omap4-l3-noc", "simple-bus";
129		#address-cells = <1>;
130		#size-cells = <1>;
131		ranges;
132		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
133		reg = <0x44000000 0x1000>,
134		      <0x44800000 0x2000>,
135		      <0x45000000 0x1000>;
136		interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
137			     <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
138
139		l4_wkup: interconnect@4a300000 {
140		};
141
142		l4_cfg: interconnect@4a000000 {
143		};
144
145		l4_per: interconnect@48000000 {
146		};
147
148		l4_abe: interconnect@40100000 {
149		};
150
151		ocmcram: ocmcram@40304000 {
152			compatible = "mmio-sram";
153			reg = <0x40304000 0xa000>; /* 40k */
154		};
155
156		gpmc: gpmc@50000000 {
157			compatible = "ti,omap4430-gpmc";
158			reg = <0x50000000 0x1000>;
159			#address-cells = <2>;
160			#size-cells = <1>;
161			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
162			dmas = <&sdma 4>;
163			dma-names = "rxtx";
164			gpmc,num-cs = <8>;
165			gpmc,num-waitpins = <4>;
166			ti,hwmods = "gpmc";
167			ti,no-idle-on-init;
168			clocks = <&l3_div_ck>;
169			clock-names = "fck";
170			interrupt-controller;
171			#interrupt-cells = <2>;
172			gpio-controller;
173			#gpio-cells = <2>;
174		};
175
176		mmu_dsp: mmu@4a066000 {
177			compatible = "ti,omap4-iommu";
178			reg = <0x4a066000 0x100>;
179			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
180			ti,hwmods = "mmu_dsp";
181			#iommu-cells = <0>;
182		};
183
184		target-module@52000000 {
185			compatible = "ti,sysc-omap4", "ti,sysc";
186			ti,hwmods = "iss";
187			reg = <0x52000000 0x4>,
188			      <0x52000010 0x4>;
189			reg-names = "rev", "sysc";
190			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
191			ti,sysc-midle = <SYSC_IDLE_FORCE>,
192					<SYSC_IDLE_NO>,
193					<SYSC_IDLE_SMART>,
194					<SYSC_IDLE_SMART_WKUP>;
195			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
196					<SYSC_IDLE_NO>,
197					<SYSC_IDLE_SMART>,
198					<SYSC_IDLE_SMART_WKUP>;
199			ti,sysc-delay-us = <2>;
200			clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
201			clock-names = "fck";
202			#address-cells = <1>;
203			#size-cells = <1>;
204			ranges = <0 0x52000000 0x1000000>;
205
206			/* No child device binding, driver in staging */
207		};
208
209		mmu_ipu: mmu@55082000 {
210			compatible = "ti,omap4-iommu";
211			reg = <0x55082000 0x100>;
212			interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
213			ti,hwmods = "mmu_ipu";
214			#iommu-cells = <0>;
215			ti,iommu-bus-err-back;
216		};
217		target-module@4012c000 {
218			compatible = "ti,sysc-omap4", "ti,sysc";
219			ti,hwmods = "slimbus1";
220			reg = <0x4012c000 0x4>,
221			      <0x4012c010 0x4>;
222			reg-names = "rev", "sysc";
223			ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
224			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
225					<SYSC_IDLE_NO>,
226					<SYSC_IDLE_SMART>,
227					<SYSC_IDLE_SMART_WKUP>;
228			clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
229			clock-names = "fck";
230			#address-cells = <1>;
231			#size-cells = <1>;
232			ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
233				 <0x4902c000 0x4902c000 0x1000>; /* L3 */
234
235			/* No child device binding or driver in mainline */
236		};
237
238		dmm@4e000000 {
239			compatible = "ti,omap4-dmm";
240			reg = <0x4e000000 0x800>;
241			interrupts = <0 113 0x4>;
242			ti,hwmods = "dmm";
243		};
244
245		emif1: emif@4c000000 {
246			compatible = "ti,emif-4d";
247			reg = <0x4c000000 0x100>;
248			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
249			ti,hwmods = "emif1";
250			ti,no-idle-on-init;
251			phy-type = <1>;
252			hw-caps-read-idle-ctrl;
253			hw-caps-ll-interface;
254			hw-caps-temp-alert;
255		};
256
257		emif2: emif@4d000000 {
258			compatible = "ti,emif-4d";
259			reg = <0x4d000000 0x100>;
260			interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
261			ti,hwmods = "emif2";
262			ti,no-idle-on-init;
263			phy-type = <1>;
264			hw-caps-read-idle-ctrl;
265			hw-caps-ll-interface;
266			hw-caps-temp-alert;
267		};
268
269		aes1: aes@4b501000 {
270			compatible = "ti,omap4-aes";
271			ti,hwmods = "aes1";
272			reg = <0x4b501000 0xa0>;
273			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
274			dmas = <&sdma 111>, <&sdma 110>;
275			dma-names = "tx", "rx";
276		};
277
278		aes2: aes@4b701000 {
279			compatible = "ti,omap4-aes";
280			ti,hwmods = "aes2";
281			reg = <0x4b701000 0xa0>;
282			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
283			dmas = <&sdma 114>, <&sdma 113>;
284			dma-names = "tx", "rx";
285		};
286
287		des: des@480a5000 {
288			compatible = "ti,omap4-des";
289			ti,hwmods = "des";
290			reg = <0x480a5000 0xa0>;
291			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
292			dmas = <&sdma 117>, <&sdma 116>;
293			dma-names = "tx", "rx";
294		};
295
296		sham: sham@4b100000 {
297			compatible = "ti,omap4-sham";
298			ti,hwmods = "sham";
299			reg = <0x4b100000 0x300>;
300			interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
301			dmas = <&sdma 119>;
302			dma-names = "rx";
303		};
304
305		abb_mpu: regulator-abb-mpu {
306			compatible = "ti,abb-v2";
307			regulator-name = "abb_mpu";
308			#address-cells = <0>;
309			#size-cells = <0>;
310			ti,tranxdone-status-mask = <0x80>;
311			clocks = <&sys_clkin_ck>;
312			ti,settling-time = <50>;
313			ti,clock-cycles = <16>;
314
315			status = "disabled";
316		};
317
318		abb_iva: regulator-abb-iva {
319			compatible = "ti,abb-v2";
320			regulator-name = "abb_iva";
321			#address-cells = <0>;
322			#size-cells = <0>;
323			ti,tranxdone-status-mask = <0x80000000>;
324			clocks = <&sys_clkin_ck>;
325			ti,settling-time = <50>;
326			ti,clock-cycles = <16>;
327
328			status = "disabled";
329		};
330
331		target-module@56000000 {
332			compatible = "ti,sysc-omap4", "ti,sysc";
333			reg = <0x5601fc00 0x4>,
334			      <0x5601fc10 0x4>;
335			reg-names = "rev", "sysc";
336			ti,sysc-midle = <SYSC_IDLE_FORCE>,
337					<SYSC_IDLE_NO>,
338					<SYSC_IDLE_SMART>,
339					<SYSC_IDLE_SMART_WKUP>;
340			ti,sysc-sidle = <SYSC_IDLE_FORCE>,
341					<SYSC_IDLE_NO>,
342					<SYSC_IDLE_SMART>,
343					<SYSC_IDLE_SMART_WKUP>;
344			clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
345			clock-names = "fck";
346			#address-cells = <1>;
347			#size-cells = <1>;
348			ranges = <0 0x56000000 0x2000000>;
349
350			/*
351			 * Closed source PowerVR driver, no child device
352			 * binding or driver in mainline
353			 */
354		};
355
356		dss: dss@58000000 {
357			compatible = "ti,omap4-dss";
358			reg = <0x58000000 0x80>;
359			status = "disabled";
360			ti,hwmods = "dss_core";
361			clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
362			clock-names = "fck";
363			#address-cells = <1>;
364			#size-cells = <1>;
365			ranges;
366
367			dispc@58001000 {
368				compatible = "ti,omap4-dispc";
369				reg = <0x58001000 0x1000>;
370				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
371				ti,hwmods = "dss_dispc";
372				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
373				clock-names = "fck";
374			};
375
376			rfbi: encoder@58002000  {
377				compatible = "ti,omap4-rfbi";
378				reg = <0x58002000 0x1000>;
379				status = "disabled";
380				ti,hwmods = "dss_rfbi";
381				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
382				clock-names = "fck", "ick";
383			};
384
385			venc: encoder@58003000 {
386				compatible = "ti,omap4-venc";
387				reg = <0x58003000 0x1000>;
388				status = "disabled";
389				ti,hwmods = "dss_venc";
390				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
391				clock-names = "fck";
392			};
393
394			dsi1: encoder@58004000 {
395				compatible = "ti,omap4-dsi";
396				reg = <0x58004000 0x200>,
397				      <0x58004200 0x40>,
398				      <0x58004300 0x20>;
399				reg-names = "proto", "phy", "pll";
400				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
401				status = "disabled";
402				ti,hwmods = "dss_dsi1";
403				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
404					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
405				clock-names = "fck", "sys_clk";
406			};
407
408			dsi2: encoder@58005000 {
409				compatible = "ti,omap4-dsi";
410				reg = <0x58005000 0x200>,
411				      <0x58005200 0x40>,
412				      <0x58005300 0x20>;
413				reg-names = "proto", "phy", "pll";
414				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
415				status = "disabled";
416				ti,hwmods = "dss_dsi2";
417				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
418					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
419				clock-names = "fck", "sys_clk";
420			};
421
422			hdmi: encoder@58006000 {
423				compatible = "ti,omap4-hdmi";
424				reg = <0x58006000 0x200>,
425				      <0x58006200 0x100>,
426				      <0x58006300 0x100>,
427				      <0x58006400 0x1000>;
428				reg-names = "wp", "pll", "phy", "core";
429				interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
430				status = "disabled";
431				ti,hwmods = "dss_hdmi";
432				clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
433					 <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
434				clock-names = "fck", "sys_clk";
435				dmas = <&sdma 76>;
436				dma-names = "audio_tx";
437			};
438		};
439	};
440};
441
442#include "omap4-l4.dtsi"
443#include "omap4-l4-abe.dtsi"
444#include "omap44xx-clocks.dtsi"
445