1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2014 Carlo Caione <carlo@caione.org>
4 */
5
6#include "meson.dtsi"
7
8/ {
9	model = "Amlogic Meson6 SoC";
10	compatible = "amlogic,meson6";
11
12	cpus {
13		#address-cells = <1>;
14		#size-cells = <0>;
15
16		cpu@200 {
17			device_type = "cpu";
18			compatible = "arm,cortex-a9";
19			next-level-cache = <&L2>;
20			reg = <0x200>;
21		};
22
23		cpu@201 {
24			device_type = "cpu";
25			compatible = "arm,cortex-a9";
26			next-level-cache = <&L2>;
27			reg = <0x201>;
28		};
29	};
30
31	apb2: bus@d0000000 {
32		compatible = "simple-bus";
33		reg = <0xd0000000 0x40000>;
34		#address-cells = <1>;
35		#size-cells = <1>;
36		ranges = <0x0 0xd0000000 0x40000>;
37	};
38
39	xtal: xtal-clk {
40		compatible = "fixed-clock";
41		clock-frequency = <24000000>;
42		clock-output-names = "xtal";
43		#clock-cells = <0>;
44	};
45
46	clk81: clk@0 {
47		#clock-cells = <0>;
48		compatible = "fixed-clock";
49		clock-frequency = <200000000>;
50	};
51}; /* end of / */
52
53&efuse {
54	status = "disabled";
55};
56
57&timer_abcde {
58	clocks = <&xtal>, <&clk81>;
59	clock-names = "xtal", "pclk";
60};
61
62&uart_AO {
63	clocks = <&xtal>, <&clk81>, <&clk81>;
64	clock-names = "xtal", "pclk", "baud";
65};
66
67&uart_A {
68	clocks = <&xtal>, <&clk81>, <&clk81>;
69	clock-names = "xtal", "pclk", "baud";
70};
71
72&uart_B {
73	clocks = <&xtal>, <&clk81>, <&clk81>;
74	clock-names = "xtal", "pclk", "baud";
75};
76
77&uart_C {
78	clocks = <&xtal>, <&clk81>, <&clk81>;
79	clock-names = "xtal", "pclk", "baud";
80};
81