1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * NXP LPC32xx SoC
4 *
5 * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
6 * Copyright 2012 Roland Stigge <stigge@antcom.de>
7 */
8
9#include <dt-bindings/clock/lpc32xx-clock.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11
12/ {
13	#address-cells = <1>;
14	#size-cells = <1>;
15	compatible = "nxp,lpc3220";
16	interrupt-parent = <&mic>;
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu@0 {
23			compatible = "arm,arm926ej-s";
24			device_type = "cpu";
25			reg = <0x0>;
26		};
27	};
28
29	clocks {
30		xtal_32k: xtal_32k {
31			compatible = "fixed-clock";
32			#clock-cells = <0>;
33			clock-frequency = <32768>;
34			clock-output-names = "xtal_32k";
35		};
36
37		xtal: xtal {
38			compatible = "fixed-clock";
39			#clock-cells = <0>;
40			clock-frequency = <13000000>;
41			clock-output-names = "xtal";
42		};
43	};
44
45	ahb {
46		#address-cells = <1>;
47		#size-cells = <1>;
48		compatible = "simple-bus";
49		ranges = <0x00000000 0x00000000 0x10000000>,
50			 <0x20000000 0x20000000 0x30000000>,
51			 <0xe0000000 0xe0000000 0x04000000>;
52
53		iram: sram@8000000 {
54			compatible = "mmio-sram";
55			reg = <0x08000000 0x20000>;
56
57			#address-cells = <1>;
58			#size-cells = <1>;
59			ranges = <0x00000000 0x08000000 0x20000>;
60		};
61
62		/*
63		 * Enable either SLC or MLC
64		 */
65		slc: flash@20020000 {
66			compatible = "nxp,lpc3220-slc";
67			reg = <0x20020000 0x1000>;
68			clocks = <&clk LPC32XX_CLK_SLC>;
69			status = "disabled";
70		};
71
72		mlc: flash@200a8000 {
73			compatible = "nxp,lpc3220-mlc";
74			reg = <0x200a8000 0x11000>;
75			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
76			clocks = <&clk LPC32XX_CLK_MLC>;
77			status = "disabled";
78		};
79
80		dma: dma@31000000 {
81			compatible = "arm,pl080", "arm,primecell";
82			reg = <0x31000000 0x1000>;
83			interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
84			clocks = <&clk LPC32XX_CLK_DMA>;
85			clock-names = "apb_pclk";
86		};
87
88		usb {
89			#address-cells = <1>;
90			#size-cells = <1>;
91			compatible = "simple-bus";
92			ranges = <0x0 0x31020000 0x00001000>;
93
94			/*
95			 * Enable either ohci or usbd (gadget)!
96			 */
97			ohci: ohci@0 {
98				compatible = "nxp,ohci-nxp", "usb-ohci";
99				reg = <0x0 0x300>;
100				interrupt-parent = <&sic1>;
101				interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
102				clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
103				status = "disabled";
104			};
105
106			usbd: usbd@0 {
107				compatible = "nxp,lpc3220-udc";
108				reg = <0x0 0x300>;
109				interrupt-parent = <&sic1>;
110				interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
111					     <30 IRQ_TYPE_LEVEL_HIGH>,
112					     <28 IRQ_TYPE_LEVEL_HIGH>,
113					     <26 IRQ_TYPE_LEVEL_LOW>;
114				clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
115				status = "disabled";
116			};
117
118			i2cusb: i2c@300 {
119				compatible = "nxp,pnx-i2c";
120				reg = <0x300 0x100>;
121				interrupt-parent = <&sic1>;
122				interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
123				clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
124				#address-cells = <1>;
125				#size-cells = <0>;
126				pnx,timeout = <0x64>;
127			};
128
129			usbclk: clock-controller@f00 {
130				compatible = "nxp,lpc3220-usb-clk";
131				reg = <0xf00 0x100>;
132				#clock-cells = <1>;
133			};
134		};
135
136		clcd: clcd@31040000 {
137			compatible = "arm,pl111", "arm,primecell";
138			reg = <0x31040000 0x1000>;
139			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
140			clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
141			clock-names = "clcdclk", "apb_pclk";
142			status = "disabled";
143		};
144
145		mac: ethernet@31060000 {
146			compatible = "nxp,lpc-eth";
147			reg = <0x31060000 0x1000>;
148			interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
149			clocks = <&clk LPC32XX_CLK_MAC>;
150			status = "disabled";
151		};
152
153		emc: memory-controller@31080000 {
154			compatible = "arm,pl175", "arm,primecell";
155			reg = <0x31080000 0x1000>;
156			clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
157			clock-names = "mpmcclk", "apb_pclk";
158			#address-cells = <1>;
159			#size-cells = <1>;
160
161			ranges = <0 0xe0000000 0x01000000>,
162				 <1 0xe1000000 0x01000000>,
163				 <2 0xe2000000 0x01000000>,
164				 <3 0xe3000000 0x01000000>;
165			status = "disabled";
166		};
167
168		apb {
169			#address-cells = <1>;
170			#size-cells = <1>;
171			compatible = "simple-bus";
172			ranges = <0x20000000 0x20000000 0x30000000>;
173
174			/*
175			 * ssp0 and spi1 are shared pins;
176			 * enable one in your board dts, as needed.
177			 */
178			ssp0: spi@20084000 {
179				compatible = "arm,pl022", "arm,primecell";
180				reg = <0x20084000 0x1000>;
181				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
182				clocks = <&clk LPC32XX_CLK_SSP0>;
183				clock-names = "apb_pclk";
184				#address-cells = <1>;
185				#size-cells = <0>;
186				status = "disabled";
187			};
188
189			spi1: spi@20088000 {
190				compatible = "nxp,lpc3220-spi";
191				reg = <0x20088000 0x1000>;
192				clocks = <&clk LPC32XX_CLK_SPI1>;
193				#address-cells = <1>;
194				#size-cells = <0>;
195				status = "disabled";
196			};
197
198			/*
199			 * ssp1 and spi2 are shared pins;
200			 * enable one in your board dts, as needed.
201			 */
202			ssp1: spi@2008c000 {
203				compatible = "arm,pl022", "arm,primecell";
204				reg = <0x2008c000 0x1000>;
205				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
206				clocks = <&clk LPC32XX_CLK_SSP1>;
207				clock-names = "apb_pclk";
208				#address-cells = <1>;
209				#size-cells = <0>;
210				status = "disabled";
211			};
212
213			spi2: spi@20090000 {
214				compatible = "nxp,lpc3220-spi";
215				reg = <0x20090000 0x1000>;
216				clocks = <&clk LPC32XX_CLK_SPI2>;
217				#address-cells = <1>;
218				#size-cells = <0>;
219				status = "disabled";
220			};
221
222			i2s0: i2s@20094000 {
223				compatible = "nxp,lpc3220-i2s";
224				reg = <0x20094000 0x1000>;
225				status = "disabled";
226			};
227
228			sd: sd@20098000 {
229				compatible = "arm,pl18x", "arm,primecell";
230				reg = <0x20098000 0x1000>;
231				interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
232					     <13 IRQ_TYPE_LEVEL_HIGH>;
233				clocks = <&clk LPC32XX_CLK_SD>;
234				clock-names = "apb_pclk";
235				status = "disabled";
236			};
237
238			i2s1: i2s@2009c000 {
239				compatible = "nxp,lpc3220-i2s";
240				reg = <0x2009c000 0x1000>;
241				status = "disabled";
242			};
243
244			/* UART5 first since it is the default console, ttyS0 */
245			uart5: serial@40090000 {
246				/* actually, ns16550a w/ 64 byte fifos! */
247				compatible = "nxp,lpc3220-uart";
248				reg = <0x40090000 0x1000>;
249				interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
250				reg-shift = <2>;
251				clocks = <&clk LPC32XX_CLK_UART5>;
252				status = "disabled";
253			};
254
255			uart3: serial@40080000 {
256				compatible = "nxp,lpc3220-uart";
257				reg = <0x40080000 0x1000>;
258				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
259				reg-shift = <2>;
260				clocks = <&clk LPC32XX_CLK_UART3>;
261				status = "disabled";
262			};
263
264			uart4: serial@40088000 {
265				compatible = "nxp,lpc3220-uart";
266				reg = <0x40088000 0x1000>;
267				interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
268				reg-shift = <2>;
269				clocks = <&clk LPC32XX_CLK_UART4>;
270				status = "disabled";
271			};
272
273			uart6: serial@40098000 {
274				compatible = "nxp,lpc3220-uart";
275				reg = <0x40098000 0x1000>;
276				interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
277				reg-shift = <2>;
278				clocks = <&clk LPC32XX_CLK_UART6>;
279				status = "disabled";
280			};
281
282			i2c1: i2c@400a0000 {
283				compatible = "nxp,pnx-i2c";
284				reg = <0x400a0000 0x100>;
285				interrupt-parent = <&sic1>;
286				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
287				#address-cells = <1>;
288				#size-cells = <0>;
289				pnx,timeout = <0x64>;
290				clocks = <&clk LPC32XX_CLK_I2C1>;
291			};
292
293			i2c2: i2c@400a8000 {
294				compatible = "nxp,pnx-i2c";
295				reg = <0x400a8000 0x100>;
296				interrupt-parent = <&sic1>;
297				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
298				#address-cells = <1>;
299				#size-cells = <0>;
300				pnx,timeout = <0x64>;
301				clocks = <&clk LPC32XX_CLK_I2C2>;
302			};
303
304			mpwm: mpwm@400e8000 {
305				compatible = "nxp,lpc3220-motor-pwm";
306				reg = <0x400e8000 0x78>;
307				status = "disabled";
308				#pwm-cells = <2>;
309			};
310		};
311
312		fab {
313			#address-cells = <1>;
314			#size-cells = <1>;
315			compatible = "simple-bus";
316			ranges = <0x20000000 0x20000000 0x30000000>;
317
318			/* System Control Block */
319			scb {
320				compatible = "simple-bus";
321				ranges = <0x0 0x040004000 0x00001000>;
322				#address-cells = <1>;
323				#size-cells = <1>;
324
325				clk: clock-controller@0 {
326					compatible = "nxp,lpc3220-clk";
327					reg = <0x00 0x114>;
328					#clock-cells = <1>;
329
330					clocks = <&xtal_32k>, <&xtal>;
331					clock-names = "xtal_32k", "xtal";
332
333					assigned-clocks = <&clk LPC32XX_CLK_HCLK_PLL>;
334					assigned-clock-rates = <208000000>;
335				};
336			};
337
338			mic: interrupt-controller@40008000 {
339				compatible = "nxp,lpc3220-mic";
340				reg = <0x40008000 0x4000>;
341				interrupt-controller;
342				#interrupt-cells = <2>;
343			};
344
345			sic1: interrupt-controller@4000c000 {
346				compatible = "nxp,lpc3220-sic";
347				reg = <0x4000c000 0x4000>;
348				interrupt-controller;
349				#interrupt-cells = <2>;
350
351				interrupt-parent = <&mic>;
352				interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
353					     <30 IRQ_TYPE_LEVEL_LOW>;
354				};
355
356			sic2: interrupt-controller@40010000 {
357				compatible = "nxp,lpc3220-sic";
358				reg = <0x40010000 0x4000>;
359				interrupt-controller;
360				#interrupt-cells = <2>;
361
362				interrupt-parent = <&mic>;
363				interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
364					     <31 IRQ_TYPE_LEVEL_LOW>;
365			};
366
367			uart1: serial@40014000 {
368				compatible = "nxp,lpc3220-hsuart";
369				reg = <0x40014000 0x1000>;
370				interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
371				status = "disabled";
372			};
373
374			uart2: serial@40018000 {
375				compatible = "nxp,lpc3220-hsuart";
376				reg = <0x40018000 0x1000>;
377				interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
378				status = "disabled";
379			};
380
381			uart7: serial@4001c000 {
382				compatible = "nxp,lpc3220-hsuart";
383				reg = <0x4001c000 0x1000>;
384				interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
385				status = "disabled";
386			};
387
388			rtc: rtc@40024000 {
389				compatible = "nxp,lpc3220-rtc";
390				reg = <0x40024000 0x1000>;
391				interrupt-parent = <&sic1>;
392				interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
393				clocks = <&clk LPC32XX_CLK_RTC>;
394			};
395
396			gpio: gpio@40028000 {
397				compatible = "nxp,lpc3220-gpio";
398				reg = <0x40028000 0x1000>;
399				gpio-controller;
400				#gpio-cells = <3>; /* bank, pin, flags */
401			};
402
403			timer4: timer@4002c000 {
404				compatible = "nxp,lpc3220-timer";
405				reg = <0x4002c000 0x1000>;
406				interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
407				clocks = <&clk LPC32XX_CLK_TIMER4>;
408				clock-names = "timerclk";
409				status = "disabled";
410			};
411
412			timer5: timer@40030000 {
413				compatible = "nxp,lpc3220-timer";
414				reg = <0x40030000 0x1000>;
415				interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
416				clocks = <&clk LPC32XX_CLK_TIMER5>;
417				clock-names = "timerclk";
418				status = "disabled";
419			};
420
421			watchdog: watchdog@4003c000 {
422				compatible = "nxp,pnx4008-wdt";
423				reg = <0x4003c000 0x1000>;
424				clocks = <&clk LPC32XX_CLK_WDOG>;
425			};
426
427			timer0: timer@40044000 {
428				compatible = "nxp,lpc3220-timer";
429				reg = <0x40044000 0x1000>;
430				clocks = <&clk LPC32XX_CLK_TIMER0>;
431				clock-names = "timerclk";
432				interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
433			};
434
435			/*
436			 * TSC vs. ADC: Since those two share the same
437			 * hardware, you need to choose from one of the
438			 * following two and do 'status = "okay";' for one of
439			 * them
440			 */
441
442			adc: adc@40048000 {
443				compatible = "nxp,lpc3220-adc";
444				reg = <0x40048000 0x1000>;
445				interrupt-parent = <&sic1>;
446				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
447				clocks = <&clk LPC32XX_CLK_ADC>;
448				status = "disabled";
449			};
450
451			tsc: tsc@40048000 {
452				compatible = "nxp,lpc3220-tsc";
453				reg = <0x40048000 0x1000>;
454				interrupt-parent = <&sic1>;
455				interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
456				clocks = <&clk LPC32XX_CLK_ADC>;
457				status = "disabled";
458			};
459
460			timer1: timer@4004c000 {
461				compatible = "nxp,lpc3220-timer";
462				reg = <0x4004c000 0x1000>;
463				interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
464				clocks = <&clk LPC32XX_CLK_TIMER1>;
465				clock-names = "timerclk";
466			};
467
468			key: key@40050000 {
469				compatible = "nxp,lpc3220-key";
470				reg = <0x40050000 0x1000>;
471				clocks = <&clk LPC32XX_CLK_KEY>;
472				interrupt-parent = <&sic1>;
473				interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
474				status = "disabled";
475			};
476
477			timer2: timer@40058000 {
478				compatible = "nxp,lpc3220-timer";
479				reg = <0x40058000 0x1000>;
480				interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
481				clocks = <&clk LPC32XX_CLK_TIMER2>;
482				clock-names = "timerclk";
483				status = "disabled";
484			};
485
486			pwm1: pwm@4005c000 {
487				compatible = "nxp,lpc3220-pwm";
488				reg = <0x4005c000 0x4>;
489				clocks = <&clk LPC32XX_CLK_PWM1>;
490				assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
491				assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
492				status = "disabled";
493			};
494
495			pwm2: pwm@4005c004 {
496				compatible = "nxp,lpc3220-pwm";
497				reg = <0x4005c004 0x4>;
498				clocks = <&clk LPC32XX_CLK_PWM2>;
499				assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
500				assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
501				status = "disabled";
502			};
503
504			timer3: timer@40060000 {
505				compatible = "nxp,lpc3220-timer";
506				reg = <0x40060000 0x1000>;
507				interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
508				clocks = <&clk LPC32XX_CLK_TIMER3>;
509				clock-names = "timerclk";
510				status = "disabled";
511			};
512		};
513	};
514};
515