1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright 2015 Freescale Semiconductor, Inc. 4// Copyright 2016 Toradex AG 5 6#include <dt-bindings/clock/imx7d-clock.h> 7#include <dt-bindings/power/imx7-power.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/reset/imx7-reset.h> 12#include "imx7d-pinfunc.h" 13 14/ { 15 #address-cells = <1>; 16 #size-cells = <1>; 17 /* 18 * The decompressor and also some bootloaders rely on a 19 * pre-existing /chosen node to be available to insert the 20 * command line and merge other ATAGS info. 21 */ 22 chosen {}; 23 24 aliases { 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 gpio5 = &gpio6; 31 gpio6 = &gpio7; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 mmc0 = &usdhc1; 37 mmc1 = &usdhc2; 38 mmc2 = &usdhc3; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 serial5 = &uart6; 45 serial6 = &uart7; 46 spi0 = &ecspi1; 47 spi1 = &ecspi2; 48 spi2 = &ecspi3; 49 spi3 = &ecspi4; 50 }; 51 52 cpus { 53 #address-cells = <1>; 54 #size-cells = <0>; 55 56 idle-states { 57 entry-method = "psci"; 58 59 cpu_sleep_wait: cpu-sleep-wait { 60 compatible = "arm,idle-state"; 61 arm,psci-suspend-param = <0x0010000>; 62 local-timer-stop; 63 entry-latency-us = <100>; 64 exit-latency-us = <50>; 65 min-residency-us = <1000>; 66 }; 67 }; 68 69 cpu0: cpu@0 { 70 compatible = "arm,cortex-a7"; 71 device_type = "cpu"; 72 reg = <0>; 73 clock-frequency = <792000000>; 74 clock-latency = <61036>; /* two CLK32 periods */ 75 clocks = <&clks IMX7D_CLK_ARM>; 76 cpu-idle-states = <&cpu_sleep_wait>; 77 }; 78 }; 79 80 ckil: clock-cki { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <32768>; 84 clock-output-names = "ckil"; 85 }; 86 87 osc: clock-osc { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <24000000>; 91 clock-output-names = "osc"; 92 }; 93 94 usbphynop1: usbphynop1 { 95 compatible = "usb-nop-xceiv"; 96 clocks = <&clks IMX7D_USB_PHY1_CLK>; 97 clock-names = "main_clk"; 98 #phy-cells = <0>; 99 }; 100 101 usbphynop3: usbphynop3 { 102 compatible = "usb-nop-xceiv"; 103 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>; 104 clock-names = "main_clk"; 105 #phy-cells = <0>; 106 }; 107 108 pmu { 109 compatible = "arm,cortex-a7-pmu"; 110 interrupt-parent = <&gpc>; 111 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 112 interrupt-affinity = <&cpu0>; 113 }; 114 115 replicator { 116 /* 117 * non-configurable replicators don't show up on the 118 * AMBA bus. As such no need to add "arm,primecell" 119 */ 120 compatible = "arm,coresight-static-replicator"; 121 122 out-ports { 123 #address-cells = <1>; 124 #size-cells = <0>; 125 /* replicator output ports */ 126 port@0 { 127 reg = <0>; 128 replicator_out_port0: endpoint { 129 remote-endpoint = <&tpiu_in_port>; 130 }; 131 }; 132 133 port@1 { 134 reg = <1>; 135 replicator_out_port1: endpoint { 136 remote-endpoint = <&etr_in_port>; 137 }; 138 }; 139 }; 140 141 in-ports { 142 port { 143 replicator_in_port0: endpoint { 144 remote-endpoint = <&etf_out_port>; 145 }; 146 }; 147 }; 148 }; 149 150 tempmon: tempmon { 151 compatible = "fsl,imx7d-tempmon"; 152 interrupt-parent = <&gpc>; 153 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 154 fsl,tempmon = <&anatop>; 155 nvmem-cells = <&tempmon_calib>, 156 <&tempmon_temp_grade>; 157 nvmem-cell-names = "calib", "temp_grade"; 158 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; 159 }; 160 161 timer { 162 compatible = "arm,armv7-timer"; 163 interrupt-parent = <&intc>; 164 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 165 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 166 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 167 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 168 }; 169 170 soc { 171 #address-cells = <1>; 172 #size-cells = <1>; 173 compatible = "simple-bus"; 174 interrupt-parent = <&gpc>; 175 ranges; 176 177 funnel@30041000 { 178 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 179 reg = <0x30041000 0x1000>; 180 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 181 clock-names = "apb_pclk"; 182 183 ca_funnel_in_ports: in-ports { 184 port { 185 ca_funnel_in_port0: endpoint { 186 remote-endpoint = <&etm0_out_port>; 187 }; 188 }; 189 190 /* the other input ports are not connect to anything */ 191 }; 192 193 out-ports { 194 port { 195 ca_funnel_out_port0: endpoint { 196 remote-endpoint = <&hugo_funnel_in_port0>; 197 }; 198 }; 199 200 }; 201 }; 202 203 etm@3007c000 { 204 compatible = "arm,coresight-etm3x", "arm,primecell"; 205 reg = <0x3007c000 0x1000>; 206 cpu = <&cpu0>; 207 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 208 clock-names = "apb_pclk"; 209 210 out-ports { 211 port { 212 etm0_out_port: endpoint { 213 remote-endpoint = <&ca_funnel_in_port0>; 214 }; 215 }; 216 }; 217 }; 218 219 funnel@30083000 { 220 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 221 reg = <0x30083000 0x1000>; 222 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 223 clock-names = "apb_pclk"; 224 225 in-ports { 226 #address-cells = <1>; 227 #size-cells = <0>; 228 229 port@0 { 230 reg = <0>; 231 hugo_funnel_in_port0: endpoint { 232 remote-endpoint = <&ca_funnel_out_port0>; 233 }; 234 }; 235 236 port@1 { 237 reg = <1>; 238 hugo_funnel_in_port1: endpoint { 239 /* M4 input */ 240 }; 241 }; 242 /* the other input ports are not connect to anything */ 243 }; 244 245 out-ports { 246 port { 247 hugo_funnel_out_port0: endpoint { 248 remote-endpoint = <&etf_in_port>; 249 }; 250 }; 251 }; 252 }; 253 254 etf@30084000 { 255 compatible = "arm,coresight-tmc", "arm,primecell"; 256 reg = <0x30084000 0x1000>; 257 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 258 clock-names = "apb_pclk"; 259 260 in-ports { 261 port { 262 etf_in_port: endpoint { 263 remote-endpoint = <&hugo_funnel_out_port0>; 264 }; 265 }; 266 }; 267 268 out-ports { 269 port { 270 etf_out_port: endpoint { 271 remote-endpoint = <&replicator_in_port0>; 272 }; 273 }; 274 }; 275 }; 276 277 etr@30086000 { 278 compatible = "arm,coresight-tmc", "arm,primecell"; 279 reg = <0x30086000 0x1000>; 280 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 281 clock-names = "apb_pclk"; 282 283 in-ports { 284 port { 285 etr_in_port: endpoint { 286 remote-endpoint = <&replicator_out_port1>; 287 }; 288 }; 289 }; 290 }; 291 292 tpiu@30087000 { 293 compatible = "arm,coresight-tpiu", "arm,primecell"; 294 reg = <0x30087000 0x1000>; 295 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>; 296 clock-names = "apb_pclk"; 297 298 in-ports { 299 port { 300 tpiu_in_port: endpoint { 301 remote-endpoint = <&replicator_out_port0>; 302 }; 303 }; 304 }; 305 }; 306 307 intc: interrupt-controller@31001000 { 308 compatible = "arm,cortex-a7-gic"; 309 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 310 #interrupt-cells = <3>; 311 interrupt-controller; 312 interrupt-parent = <&intc>; 313 reg = <0x31001000 0x1000>, 314 <0x31002000 0x2000>, 315 <0x31004000 0x2000>, 316 <0x31006000 0x2000>; 317 }; 318 319 aips1: aips-bus@30000000 { 320 compatible = "fsl,aips-bus", "simple-bus"; 321 #address-cells = <1>; 322 #size-cells = <1>; 323 reg = <0x30000000 0x400000>; 324 ranges; 325 326 gpio1: gpio@30200000 { 327 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 328 reg = <0x30200000 0x10000>; 329 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, /* GPIO1_INT15_0 */ 330 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; /* GPIO1_INT31_16 */ 331 gpio-controller; 332 #gpio-cells = <2>; 333 interrupt-controller; 334 #interrupt-cells = <2>; 335 gpio-ranges = <&iomuxc_lpsr 0 0 8>, <&iomuxc 8 5 8>; 336 }; 337 338 gpio2: gpio@30210000 { 339 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 340 reg = <0x30210000 0x10000>; 341 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 343 gpio-controller; 344 #gpio-cells = <2>; 345 interrupt-controller; 346 #interrupt-cells = <2>; 347 gpio-ranges = <&iomuxc 0 13 32>; 348 }; 349 350 gpio3: gpio@30220000 { 351 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 352 reg = <0x30220000 0x10000>; 353 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 355 gpio-controller; 356 #gpio-cells = <2>; 357 interrupt-controller; 358 #interrupt-cells = <2>; 359 gpio-ranges = <&iomuxc 0 45 29>; 360 }; 361 362 gpio4: gpio@30230000 { 363 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 364 reg = <0x30230000 0x10000>; 365 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 367 gpio-controller; 368 #gpio-cells = <2>; 369 interrupt-controller; 370 #interrupt-cells = <2>; 371 gpio-ranges = <&iomuxc 0 74 24>; 372 }; 373 374 gpio5: gpio@30240000 { 375 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 376 reg = <0x30240000 0x10000>; 377 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 379 gpio-controller; 380 #gpio-cells = <2>; 381 interrupt-controller; 382 #interrupt-cells = <2>; 383 gpio-ranges = <&iomuxc 0 98 18>; 384 }; 385 386 gpio6: gpio@30250000 { 387 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 388 reg = <0x30250000 0x10000>; 389 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 391 gpio-controller; 392 #gpio-cells = <2>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 gpio-ranges = <&iomuxc 0 116 23>; 396 }; 397 398 gpio7: gpio@30260000 { 399 compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio"; 400 reg = <0x30260000 0x10000>; 401 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 403 gpio-controller; 404 #gpio-cells = <2>; 405 interrupt-controller; 406 #interrupt-cells = <2>; 407 gpio-ranges = <&iomuxc 0 139 16>; 408 }; 409 410 wdog1: wdog@30280000 { 411 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 412 reg = <0x30280000 0x10000>; 413 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 414 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>; 415 }; 416 417 wdog2: wdog@30290000 { 418 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 419 reg = <0x30290000 0x10000>; 420 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clks IMX7D_WDOG2_ROOT_CLK>; 422 status = "disabled"; 423 }; 424 425 wdog3: wdog@302a0000 { 426 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 427 reg = <0x302a0000 0x10000>; 428 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&clks IMX7D_WDOG3_ROOT_CLK>; 430 status = "disabled"; 431 }; 432 433 wdog4: wdog@302b0000 { 434 compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; 435 reg = <0x302b0000 0x10000>; 436 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&clks IMX7D_WDOG4_ROOT_CLK>; 438 status = "disabled"; 439 }; 440 441 iomuxc_lpsr: iomuxc-lpsr@302c0000 { 442 compatible = "fsl,imx7d-iomuxc-lpsr"; 443 reg = <0x302c0000 0x10000>; 444 fsl,input-sel = <&iomuxc>; 445 }; 446 447 gpt1: gpt@302d0000 { 448 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 449 reg = <0x302d0000 0x10000>; 450 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 451 clocks = <&clks IMX7D_GPT1_ROOT_CLK>, 452 <&clks IMX7D_GPT1_ROOT_CLK>; 453 clock-names = "ipg", "per"; 454 }; 455 456 gpt2: gpt@302e0000 { 457 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 458 reg = <0x302e0000 0x10000>; 459 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&clks IMX7D_GPT2_ROOT_CLK>, 461 <&clks IMX7D_GPT2_ROOT_CLK>; 462 clock-names = "ipg", "per"; 463 status = "disabled"; 464 }; 465 466 gpt3: gpt@302f0000 { 467 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 468 reg = <0x302f0000 0x10000>; 469 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&clks IMX7D_GPT3_ROOT_CLK>, 471 <&clks IMX7D_GPT3_ROOT_CLK>; 472 clock-names = "ipg", "per"; 473 status = "disabled"; 474 }; 475 476 gpt4: gpt@30300000 { 477 compatible = "fsl,imx7d-gpt", "fsl,imx6sx-gpt"; 478 reg = <0x30300000 0x10000>; 479 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&clks IMX7D_GPT4_ROOT_CLK>, 481 <&clks IMX7D_GPT4_ROOT_CLK>; 482 clock-names = "ipg", "per"; 483 status = "disabled"; 484 }; 485 486 kpp: kpp@30320000 { 487 compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; 488 reg = <0x30320000 0x10000>; 489 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&clks IMX7D_KPP_ROOT_CLK>; 491 status = "disabled"; 492 }; 493 494 iomuxc: iomuxc@30330000 { 495 compatible = "fsl,imx7d-iomuxc"; 496 reg = <0x30330000 0x10000>; 497 }; 498 499 gpr: iomuxc-gpr@30340000 { 500 compatible = "fsl,imx7d-iomuxc-gpr", 501 "fsl,imx6q-iomuxc-gpr", "syscon", 502 "simple-mfd"; 503 reg = <0x30340000 0x10000>; 504 505 mux: mux-controller { 506 compatible = "mmio-mux"; 507 #mux-control-cells = <0>; 508 mux-reg-masks = <0x14 0x00000010>; 509 }; 510 511 video_mux: csi-mux { 512 compatible = "video-mux"; 513 mux-controls = <&mux 0>; 514 #address-cells = <1>; 515 #size-cells = <0>; 516 status = "disabled"; 517 518 port@0 { 519 reg = <0>; 520 }; 521 522 port@1 { 523 reg = <1>; 524 525 csi_mux_from_mipi_vc0: endpoint { 526 remote-endpoint = <&mipi_vc0_to_csi_mux>; 527 }; 528 }; 529 530 port@2 { 531 reg = <2>; 532 533 csi_mux_to_csi: endpoint { 534 remote-endpoint = <&csi_from_csi_mux>; 535 }; 536 }; 537 }; 538 }; 539 540 ocotp: ocotp-ctrl@30350000 { 541 #address-cells = <1>; 542 #size-cells = <1>; 543 compatible = "fsl,imx7d-ocotp", "syscon"; 544 reg = <0x30350000 0x10000>; 545 clocks = <&clks IMX7D_OCOTP_CLK>; 546 547 tempmon_calib: calib@3c { 548 reg = <0x3c 0x4>; 549 }; 550 551 tempmon_temp_grade: temp-grade@10 { 552 reg = <0x10 0x4>; 553 }; 554 555 cpu_speed_grade: speed-grade@10 { 556 reg = <0x10 0x4>; 557 }; 558 }; 559 560 anatop: anatop@30360000 { 561 compatible = "fsl,imx7d-anatop", "fsl,imx6q-anatop", 562 "syscon", "simple-bus"; 563 reg = <0x30360000 0x10000>; 564 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 566 567 reg_1p0d: regulator-vdd1p0d { 568 compatible = "fsl,anatop-regulator"; 569 regulator-name = "vdd1p0d"; 570 regulator-min-microvolt = <800000>; 571 regulator-max-microvolt = <1200000>; 572 anatop-reg-offset = <0x210>; 573 anatop-vol-bit-shift = <8>; 574 anatop-vol-bit-width = <5>; 575 anatop-min-bit-val = <8>; 576 anatop-min-voltage = <800000>; 577 anatop-max-voltage = <1200000>; 578 anatop-enable-bit = <0>; 579 }; 580 581 reg_1p2: regulator-vdd1p2 { 582 compatible = "fsl,anatop-regulator"; 583 regulator-name = "vdd1p2"; 584 regulator-min-microvolt = <1100000>; 585 regulator-max-microvolt = <1300000>; 586 anatop-reg-offset = <0x220>; 587 anatop-vol-bit-shift = <8>; 588 anatop-vol-bit-width = <5>; 589 anatop-min-bit-val = <0x14>; 590 anatop-min-voltage = <1100000>; 591 anatop-max-voltage = <1300000>; 592 anatop-enable-bit = <0>; 593 }; 594 }; 595 596 snvs: snvs@30370000 { 597 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 598 reg = <0x30370000 0x10000>; 599 600 snvs_rtc: snvs-rtc-lp { 601 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 602 regmap = <&snvs>; 603 offset = <0x34>; 604 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&clks IMX7D_SNVS_CLK>; 607 clock-names = "snvs-rtc"; 608 }; 609 610 snvs_pwrkey: snvs-powerkey { 611 compatible = "fsl,sec-v4.0-pwrkey"; 612 regmap = <&snvs>; 613 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 614 linux,keycode = <KEY_POWER>; 615 wakeup-source; 616 status = "disabled"; 617 }; 618 }; 619 620 clks: ccm@30380000 { 621 compatible = "fsl,imx7d-ccm"; 622 reg = <0x30380000 0x10000>; 623 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 625 #clock-cells = <1>; 626 clocks = <&ckil>, <&osc>; 627 clock-names = "ckil", "osc"; 628 }; 629 630 src: src@30390000 { 631 compatible = "fsl,imx7d-src", "syscon"; 632 reg = <0x30390000 0x10000>; 633 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 634 #reset-cells = <1>; 635 }; 636 637 gpc: gpc@303a0000 { 638 compatible = "fsl,imx7d-gpc"; 639 reg = <0x303a0000 0x10000>; 640 interrupt-controller; 641 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 642 #interrupt-cells = <3>; 643 interrupt-parent = <&intc>; 644 #power-domain-cells = <1>; 645 646 pgc { 647 #address-cells = <1>; 648 #size-cells = <0>; 649 650 pgc_mipi_phy: power-domain@0 { 651 #power-domain-cells = <0>; 652 reg = <0>; 653 power-supply = <®_1p0d>; 654 }; 655 656 pgc_pcie_phy: power-domain@1 { 657 #power-domain-cells = <0>; 658 reg = <1>; 659 power-supply = <®_1p0d>; 660 }; 661 }; 662 }; 663 }; 664 665 aips2: aips-bus@30400000 { 666 compatible = "fsl,aips-bus", "simple-bus"; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 reg = <0x30400000 0x400000>; 670 ranges; 671 672 adc1: adc@30610000 { 673 compatible = "fsl,imx7d-adc"; 674 reg = <0x30610000 0x10000>; 675 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 677 clock-names = "adc"; 678 #io-channel-cells = <1>; 679 status = "disabled"; 680 }; 681 682 adc2: adc@30620000 { 683 compatible = "fsl,imx7d-adc"; 684 reg = <0x30620000 0x10000>; 685 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&clks IMX7D_ADC_ROOT_CLK>; 687 clock-names = "adc"; 688 #io-channel-cells = <1>; 689 status = "disabled"; 690 }; 691 692 ecspi4: spi@30630000 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 696 reg = <0x30630000 0x10000>; 697 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&clks IMX7D_ECSPI4_ROOT_CLK>, 699 <&clks IMX7D_ECSPI4_ROOT_CLK>; 700 clock-names = "ipg", "per"; 701 status = "disabled"; 702 }; 703 704 pwm1: pwm@30660000 { 705 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 706 reg = <0x30660000 0x10000>; 707 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&clks IMX7D_PWM1_ROOT_CLK>, 709 <&clks IMX7D_PWM1_ROOT_CLK>; 710 clock-names = "ipg", "per"; 711 #pwm-cells = <3>; 712 status = "disabled"; 713 }; 714 715 pwm2: pwm@30670000 { 716 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 717 reg = <0x30670000 0x10000>; 718 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 719 clocks = <&clks IMX7D_PWM2_ROOT_CLK>, 720 <&clks IMX7D_PWM2_ROOT_CLK>; 721 clock-names = "ipg", "per"; 722 #pwm-cells = <3>; 723 status = "disabled"; 724 }; 725 726 pwm3: pwm@30680000 { 727 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 728 reg = <0x30680000 0x10000>; 729 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&clks IMX7D_PWM3_ROOT_CLK>, 731 <&clks IMX7D_PWM3_ROOT_CLK>; 732 clock-names = "ipg", "per"; 733 #pwm-cells = <3>; 734 status = "disabled"; 735 }; 736 737 pwm4: pwm@30690000 { 738 compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; 739 reg = <0x30690000 0x10000>; 740 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&clks IMX7D_PWM4_ROOT_CLK>, 742 <&clks IMX7D_PWM4_ROOT_CLK>; 743 clock-names = "ipg", "per"; 744 #pwm-cells = <3>; 745 status = "disabled"; 746 }; 747 748 csi: csi@30710000 { 749 compatible = "fsl,imx7-csi"; 750 reg = <0x30710000 0x10000>; 751 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 752 clocks = <&clks IMX7D_CLK_DUMMY>, 753 <&clks IMX7D_CSI_MCLK_ROOT_CLK>, 754 <&clks IMX7D_CLK_DUMMY>; 755 clock-names = "axi", "mclk", "dcic"; 756 status = "disabled"; 757 758 port { 759 csi_from_csi_mux: endpoint { 760 remote-endpoint = <&csi_mux_to_csi>; 761 }; 762 }; 763 }; 764 765 lcdif: lcdif@30730000 { 766 compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; 767 reg = <0x30730000 0x10000>; 768 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>, 770 <&clks IMX7D_LCDIF_PIXEL_ROOT_CLK>; 771 clock-names = "pix", "axi"; 772 status = "disabled"; 773 }; 774 775 mipi_csi: mipi-csi@30750000 { 776 compatible = "fsl,imx7-mipi-csi2"; 777 reg = <0x30750000 0x10000>; 778 #address-cells = <1>; 779 #size-cells = <0>; 780 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 782 <&clks IMX7D_MIPI_CSI_ROOT_CLK>, 783 <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; 784 clock-names = "pclk", "wrap", "phy"; 785 power-domains = <&pgc_mipi_phy>; 786 phy-supply = <®_1p0d>; 787 resets = <&src IMX7_RESET_MIPI_PHY_MRST>; 788 reset-names = "mrst"; 789 status = "disabled"; 790 791 port@0 { 792 reg = <0>; 793 }; 794 795 port@1 { 796 reg = <1>; 797 798 mipi_vc0_to_csi_mux: endpoint { 799 remote-endpoint = <&csi_mux_from_mipi_vc0>; 800 }; 801 }; 802 }; 803 }; 804 805 aips3: aips-bus@30800000 { 806 compatible = "fsl,aips-bus", "simple-bus"; 807 #address-cells = <1>; 808 #size-cells = <1>; 809 reg = <0x30800000 0x400000>; 810 ranges; 811 812 spba-bus@30800000 { 813 compatible = "fsl,spba-bus", "simple-bus"; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 reg = <0x30800000 0x100000>; 817 ranges; 818 819 ecspi1: spi@30820000 { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 823 reg = <0x30820000 0x10000>; 824 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, 826 <&clks IMX7D_ECSPI1_ROOT_CLK>; 827 clock-names = "ipg", "per"; 828 status = "disabled"; 829 }; 830 831 ecspi2: spi@30830000 { 832 #address-cells = <1>; 833 #size-cells = <0>; 834 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 835 reg = <0x30830000 0x10000>; 836 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, 838 <&clks IMX7D_ECSPI2_ROOT_CLK>; 839 clock-names = "ipg", "per"; 840 status = "disabled"; 841 }; 842 843 ecspi3: spi@30840000 { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; 847 reg = <0x30840000 0x10000>; 848 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 849 clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, 850 <&clks IMX7D_ECSPI3_ROOT_CLK>; 851 clock-names = "ipg", "per"; 852 status = "disabled"; 853 }; 854 855 uart1: serial@30860000 { 856 compatible = "fsl,imx7d-uart", 857 "fsl,imx6q-uart"; 858 reg = <0x30860000 0x10000>; 859 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 860 clocks = <&clks IMX7D_UART1_ROOT_CLK>, 861 <&clks IMX7D_UART1_ROOT_CLK>; 862 clock-names = "ipg", "per"; 863 status = "disabled"; 864 }; 865 866 uart2: serial@30890000 { 867 compatible = "fsl,imx7d-uart", 868 "fsl,imx6q-uart"; 869 reg = <0x30890000 0x10000>; 870 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&clks IMX7D_UART2_ROOT_CLK>, 872 <&clks IMX7D_UART2_ROOT_CLK>; 873 clock-names = "ipg", "per"; 874 status = "disabled"; 875 }; 876 877 uart3: serial@30880000 { 878 compatible = "fsl,imx7d-uart", 879 "fsl,imx6q-uart"; 880 reg = <0x30880000 0x10000>; 881 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&clks IMX7D_UART3_ROOT_CLK>, 883 <&clks IMX7D_UART3_ROOT_CLK>; 884 clock-names = "ipg", "per"; 885 status = "disabled"; 886 }; 887 888 sai1: sai@308a0000 { 889 #sound-dai-cells = <0>; 890 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 891 reg = <0x308a0000 0x10000>; 892 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&clks IMX7D_SAI1_IPG_CLK>, 894 <&clks IMX7D_SAI1_ROOT_CLK>, 895 <&clks IMX7D_CLK_DUMMY>, 896 <&clks IMX7D_CLK_DUMMY>; 897 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 898 dma-names = "rx", "tx"; 899 dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; 900 status = "disabled"; 901 }; 902 903 sai2: sai@308b0000 { 904 #sound-dai-cells = <0>; 905 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 906 reg = <0x308b0000 0x10000>; 907 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&clks IMX7D_SAI2_IPG_CLK>, 909 <&clks IMX7D_SAI2_ROOT_CLK>, 910 <&clks IMX7D_CLK_DUMMY>, 911 <&clks IMX7D_CLK_DUMMY>; 912 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 913 dma-names = "rx", "tx"; 914 dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; 915 status = "disabled"; 916 }; 917 918 sai3: sai@308c0000 { 919 #sound-dai-cells = <0>; 920 compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; 921 reg = <0x308c0000 0x10000>; 922 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&clks IMX7D_SAI3_IPG_CLK>, 924 <&clks IMX7D_SAI3_ROOT_CLK>, 925 <&clks IMX7D_CLK_DUMMY>, 926 <&clks IMX7D_CLK_DUMMY>; 927 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 928 dma-names = "rx", "tx"; 929 dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; 930 status = "disabled"; 931 }; 932 }; 933 934 crypto: caam@30900000 { 935 compatible = "fsl,sec-v4.0"; 936 #address-cells = <1>; 937 #size-cells = <1>; 938 reg = <0x30900000 0x40000>; 939 ranges = <0 0x30900000 0x40000>; 940 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&clks IMX7D_CAAM_CLK>, 942 <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; 943 clock-names = "ipg", "aclk"; 944 945 sec_jr0: jr0@1000 { 946 compatible = "fsl,sec-v4.0-job-ring"; 947 reg = <0x1000 0x1000>; 948 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 949 }; 950 951 sec_jr1: jr1@2000 { 952 compatible = "fsl,sec-v4.0-job-ring"; 953 reg = <0x2000 0x1000>; 954 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 955 }; 956 957 sec_jr2: jr1@3000 { 958 compatible = "fsl,sec-v4.0-job-ring"; 959 reg = <0x3000 0x1000>; 960 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 961 }; 962 }; 963 964 flexcan1: can@30a00000 { 965 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 966 reg = <0x30a00000 0x10000>; 967 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 968 clocks = <&clks IMX7D_CLK_DUMMY>, 969 <&clks IMX7D_CAN1_ROOT_CLK>; 970 clock-names = "ipg", "per"; 971 fsl,stop-mode = <&gpr 0x10 1 0x10 17>; 972 status = "disabled"; 973 }; 974 975 flexcan2: can@30a10000 { 976 compatible = "fsl,imx7d-flexcan", "fsl,imx6q-flexcan"; 977 reg = <0x30a10000 0x10000>; 978 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&clks IMX7D_CLK_DUMMY>, 980 <&clks IMX7D_CAN2_ROOT_CLK>; 981 clock-names = "ipg", "per"; 982 fsl,stop-mode = <&gpr 0x10 2 0x10 18>; 983 status = "disabled"; 984 }; 985 986 i2c1: i2c@30a20000 { 987 #address-cells = <1>; 988 #size-cells = <0>; 989 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 990 reg = <0x30a20000 0x10000>; 991 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&clks IMX7D_I2C1_ROOT_CLK>; 993 status = "disabled"; 994 }; 995 996 i2c2: i2c@30a30000 { 997 #address-cells = <1>; 998 #size-cells = <0>; 999 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1000 reg = <0x30a30000 0x10000>; 1001 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&clks IMX7D_I2C2_ROOT_CLK>; 1003 status = "disabled"; 1004 }; 1005 1006 i2c3: i2c@30a40000 { 1007 #address-cells = <1>; 1008 #size-cells = <0>; 1009 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1010 reg = <0x30a40000 0x10000>; 1011 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&clks IMX7D_I2C3_ROOT_CLK>; 1013 status = "disabled"; 1014 }; 1015 1016 i2c4: i2c@30a50000 { 1017 #address-cells = <1>; 1018 #size-cells = <0>; 1019 compatible = "fsl,imx7d-i2c", "fsl,imx21-i2c"; 1020 reg = <0x30a50000 0x10000>; 1021 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1022 clocks = <&clks IMX7D_I2C4_ROOT_CLK>; 1023 status = "disabled"; 1024 }; 1025 1026 uart4: serial@30a60000 { 1027 compatible = "fsl,imx7d-uart", 1028 "fsl,imx6q-uart"; 1029 reg = <0x30a60000 0x10000>; 1030 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&clks IMX7D_UART4_ROOT_CLK>, 1032 <&clks IMX7D_UART4_ROOT_CLK>; 1033 clock-names = "ipg", "per"; 1034 status = "disabled"; 1035 }; 1036 1037 uart5: serial@30a70000 { 1038 compatible = "fsl,imx7d-uart", 1039 "fsl,imx6q-uart"; 1040 reg = <0x30a70000 0x10000>; 1041 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&clks IMX7D_UART5_ROOT_CLK>, 1043 <&clks IMX7D_UART5_ROOT_CLK>; 1044 clock-names = "ipg", "per"; 1045 status = "disabled"; 1046 }; 1047 1048 uart6: serial@30a80000 { 1049 compatible = "fsl,imx7d-uart", 1050 "fsl,imx6q-uart"; 1051 reg = <0x30a80000 0x10000>; 1052 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&clks IMX7D_UART6_ROOT_CLK>, 1054 <&clks IMX7D_UART6_ROOT_CLK>; 1055 clock-names = "ipg", "per"; 1056 status = "disabled"; 1057 }; 1058 1059 uart7: serial@30a90000 { 1060 compatible = "fsl,imx7d-uart", 1061 "fsl,imx6q-uart"; 1062 reg = <0x30a90000 0x10000>; 1063 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&clks IMX7D_UART7_ROOT_CLK>, 1065 <&clks IMX7D_UART7_ROOT_CLK>; 1066 clock-names = "ipg", "per"; 1067 status = "disabled"; 1068 }; 1069 1070 mu0a: mailbox@30aa0000 { 1071 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1072 reg = <0x30aa0000 0x10000>; 1073 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1074 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1075 #mbox-cells = <2>; 1076 status = "disabled"; 1077 }; 1078 1079 mu0b: mailbox@30ab0000 { 1080 compatible = "fsl,imx7s-mu", "fsl,imx6sx-mu"; 1081 reg = <0x30ab0000 0x10000>; 1082 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&clks IMX7D_MU_ROOT_CLK>; 1084 #mbox-cells = <2>; 1085 fsl,mu-side-b; 1086 status = "disabled"; 1087 }; 1088 1089 usbotg1: usb@30b10000 { 1090 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1091 reg = <0x30b10000 0x200>; 1092 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1094 fsl,usbphy = <&usbphynop1>; 1095 fsl,usbmisc = <&usbmisc1 0>; 1096 phy-clkgate-delay-us = <400>; 1097 status = "disabled"; 1098 }; 1099 1100 usbh: usb@30b30000 { 1101 compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; 1102 reg = <0x30b30000 0x200>; 1103 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1104 clocks = <&clks IMX7D_USB_CTRL_CLK>; 1105 fsl,usbphy = <&usbphynop3>; 1106 fsl,usbmisc = <&usbmisc3 0>; 1107 phy_type = "hsic"; 1108 dr_mode = "host"; 1109 phy-clkgate-delay-us = <400>; 1110 status = "disabled"; 1111 }; 1112 1113 usbmisc1: usbmisc@30b10200 { 1114 #index-cells = <1>; 1115 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1116 reg = <0x30b10200 0x200>; 1117 }; 1118 1119 usbmisc3: usbmisc@30b30200 { 1120 #index-cells = <1>; 1121 compatible = "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1122 reg = <0x30b30200 0x200>; 1123 }; 1124 1125 usdhc1: usdhc@30b40000 { 1126 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1127 reg = <0x30b40000 0x10000>; 1128 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1130 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1131 <&clks IMX7D_USDHC1_ROOT_CLK>; 1132 clock-names = "ipg", "ahb", "per"; 1133 bus-width = <4>; 1134 status = "disabled"; 1135 }; 1136 1137 usdhc2: usdhc@30b50000 { 1138 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1139 reg = <0x30b50000 0x10000>; 1140 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1142 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1143 <&clks IMX7D_USDHC2_ROOT_CLK>; 1144 clock-names = "ipg", "ahb", "per"; 1145 bus-width = <4>; 1146 status = "disabled"; 1147 }; 1148 1149 usdhc3: usdhc@30b60000 { 1150 compatible = "fsl,imx7d-usdhc", "fsl,imx6sl-usdhc"; 1151 reg = <0x30b60000 0x10000>; 1152 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1153 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1154 <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, 1155 <&clks IMX7D_USDHC3_ROOT_CLK>; 1156 clock-names = "ipg", "ahb", "per"; 1157 bus-width = <4>; 1158 status = "disabled"; 1159 }; 1160 1161 sdma: sdma@30bd0000 { 1162 compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; 1163 reg = <0x30bd0000 0x10000>; 1164 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&clks IMX7D_IPG_ROOT_CLK>, 1166 <&clks IMX7D_SDMA_CORE_CLK>; 1167 clock-names = "ipg", "ahb"; 1168 #dma-cells = <3>; 1169 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1170 }; 1171 1172 fec1: ethernet@30be0000 { 1173 compatible = "fsl,imx7d-fec", "fsl,imx6sx-fec"; 1174 reg = <0x30be0000 0x10000>; 1175 interrupt-names = "int0", "int1", "int2", "pps"; 1176 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1180 clocks = <&clks IMX7D_ENET1_IPG_ROOT_CLK>, 1181 <&clks IMX7D_ENET_AXI_ROOT_CLK>, 1182 <&clks IMX7D_ENET1_TIME_ROOT_CLK>, 1183 <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, 1184 <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; 1185 clock-names = "ipg", "ahb", "ptp", 1186 "enet_clk_ref", "enet_out"; 1187 fsl,num-tx-queues = <3>; 1188 fsl,num-rx-queues = <3>; 1189 status = "disabled"; 1190 }; 1191 }; 1192 1193 dma_apbh: dma-apbh@33000000 { 1194 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; 1195 reg = <0x33000000 0x2000>; 1196 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1200 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 1201 #dma-cells = <1>; 1202 dma-channels = <4>; 1203 clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1204 }; 1205 1206 gpmi: gpmi-nand@33002000{ 1207 compatible = "fsl,imx7d-gpmi-nand"; 1208 #address-cells = <1>; 1209 #size-cells = <1>; 1210 reg = <0x33002000 0x2000>, <0x33004000 0x4000>; 1211 reg-names = "gpmi-nand", "bch"; 1212 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1213 interrupt-names = "bch"; 1214 clocks = <&clks IMX7D_NAND_RAWNAND_CLK>, 1215 <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; 1216 clock-names = "gpmi_io", "gpmi_bch_apb"; 1217 dmas = <&dma_apbh 0>; 1218 dma-names = "rx-tx"; 1219 status = "disabled"; 1220 assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>; 1221 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>; 1222 }; 1223 }; 1224}; 1225
