1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Copyright 2016 Boundary Devices, Inc.
4 */
5
6/dts-v1/;
7
8#include "imx7d.dtsi"
9
10/ {
11	model = "Boundary Devices i.MX7 Nitrogen7 Board";
12	compatible = "boundary,imx7d-nitrogen7", "fsl,imx7d";
13
14	memory@80000000 {
15		device_type = "memory";
16		reg = <0x80000000 0x40000000>;
17	};
18
19	backlight-j9 {
20		compatible = "gpio-backlight";
21		pinctrl-names = "default";
22		pinctrl-0 = <&pinctrl_backlight_j9>;
23		gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
24		default-on;
25	};
26
27	backlight_lcd: backlight-j20 {
28		compatible = "pwm-backlight";
29		pwms = <&pwm1 0 5000000 0>;
30		brightness-levels = <0 4 8 16 32 64 128 255>;
31		default-brightness-level = <6>;
32		status = "okay";
33	};
34
35	panel-lcd {
36		compatible = "okaya,rs800480t-7x0gp";
37		backlight = <&backlight_lcd>;
38
39		port {
40			panel_in: endpoint {
41				remote-endpoint = <&lcdif_out>;
42			};
43		};
44	};
45
46	reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
47		compatible = "regulator-fixed";
48		regulator-name = "usb_otg1_vbus";
49		regulator-min-microvolt = <5000000>;
50		regulator-max-microvolt = <5000000>;
51		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
52		enable-active-high;
53	};
54
55	reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
56		compatible = "regulator-fixed";
57		regulator-name = "usb_otg2_vbus";
58		regulator-min-microvolt = <5000000>;
59		regulator-max-microvolt = <5000000>;
60		gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
61		enable-active-high;
62	};
63
64	reg_can2_3v3: regulator-can2-3v3 {
65		compatible = "regulator-fixed";
66		regulator-name = "can2-3v3";
67		regulator-min-microvolt = <3300000>;
68		regulator-max-microvolt = <3300000>;
69		gpio = <&gpio2 14 GPIO_ACTIVE_LOW>;
70	};
71
72	reg_vref_1v8: regulator-vref-1v8 {
73		compatible = "regulator-fixed";
74		regulator-name = "vref-1v8";
75		regulator-min-microvolt = <1800000>;
76		regulator-max-microvolt = <1800000>;
77	};
78
79	reg_vref_3v3: regulator-vref-3v3 {
80		compatible = "regulator-fixed";
81		regulator-name = "vref-3v3";
82		regulator-min-microvolt = <3300000>;
83		regulator-max-microvolt = <3300000>;
84	};
85
86	reg_wlan: regulator-wlan {
87		compatible = "regulator-fixed";
88		regulator-min-microvolt = <3300000>;
89		regulator-max-microvolt = <3300000>;
90		regulator-name = "reg_wlan";
91		startup-delay-us = <70000>;
92		gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
93		enable-active-high;
94	};
95
96	usdhc2_pwrseq: usdhc2_pwrseq {
97		compatible = "mmc-pwrseq-simple";
98		clocks = <&clks IMX7D_CLKO2_ROOT_DIV>;
99		clock-names = "ext_clock";
100	};
101};
102
103&adc1 {
104	vref-supply = <&reg_vref_1v8>;
105	status = "okay";
106};
107
108&adc2 {
109	vref-supply = <&reg_vref_1v8>;
110	status = "okay";
111};
112
113&clks {
114	assigned-clocks = <&clks IMX7D_CLKO2_ROOT_SRC>,
115			  <&clks IMX7D_CLKO2_ROOT_DIV>;
116	assigned-clock-parents = <&clks IMX7D_CKIL>;
117	assigned-clock-rates = <0>, <32768>;
118};
119
120&cpu0 {
121	cpu-supply = <&sw1a_reg>;
122};
123
124&fec1 {
125	pinctrl-names = "default";
126	pinctrl-0 = <&pinctrl_enet1>;
127	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
128			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
129	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
130	assigned-clock-rates = <0>, <100000000>;
131	phy-mode = "rgmii";
132	phy-handle = <&ethphy0>;
133	fsl,magic-packet;
134	status = "okay";
135
136	mdio {
137		#address-cells = <1>;
138		#size-cells = <0>;
139
140		ethphy0: ethernet-phy@4 {
141			reg = <4>;
142		};
143	};
144};
145
146&flexcan2 {
147	pinctrl-names = "default";
148	pinctrl-0 = <&pinctrl_flexcan2>;
149	xceiver-supply = <&reg_can2_3v3>;
150	status = "okay";
151};
152
153&i2c1 {
154	pinctrl-names = "default";
155	pinctrl-0 = <&pinctrl_i2c1>;
156	status = "okay";
157
158	pmic: pfuze3000@8 {
159		compatible = "fsl,pfuze3000";
160		reg = <0x08>;
161
162		regulators {
163			sw1a_reg: sw1a {
164				regulator-min-microvolt = <700000>;
165				regulator-max-microvolt = <1475000>;
166				regulator-boot-on;
167				regulator-always-on;
168				regulator-ramp-delay = <6250>;
169			};
170
171			/* use sw1c_reg to align with pfuze100/pfuze200 */
172			sw1c_reg: sw1b {
173				regulator-min-microvolt = <700000>;
174				regulator-max-microvolt = <1475000>;
175				regulator-boot-on;
176				regulator-always-on;
177				regulator-ramp-delay = <6250>;
178			};
179
180			sw2_reg: sw2 {
181				regulator-min-microvolt = <1500000>;
182				regulator-max-microvolt = <1850000>;
183				regulator-boot-on;
184				regulator-always-on;
185			};
186
187			sw3a_reg: sw3 {
188				regulator-min-microvolt = <900000>;
189				regulator-max-microvolt = <1650000>;
190				regulator-boot-on;
191				regulator-always-on;
192			};
193
194			swbst_reg: swbst {
195				regulator-min-microvolt = <5000000>;
196				regulator-max-microvolt = <5150000>;
197			};
198
199			snvs_reg: vsnvs {
200				regulator-min-microvolt = <1000000>;
201				regulator-max-microvolt = <3000000>;
202				regulator-boot-on;
203				regulator-always-on;
204			};
205
206			vref_reg: vrefddr {
207				regulator-boot-on;
208				regulator-always-on;
209			};
210
211			vgen1_reg: vldo1 {
212				regulator-min-microvolt = <1800000>;
213				regulator-max-microvolt = <3300000>;
214				regulator-always-on;
215			};
216
217			vgen2_reg: vldo2 {
218				regulator-min-microvolt = <800000>;
219				regulator-max-microvolt = <1550000>;
220				regulator-always-on;
221			};
222
223			vgen3_reg: vccsd {
224				regulator-min-microvolt = <2850000>;
225				regulator-max-microvolt = <3300000>;
226				regulator-always-on;
227			};
228
229			vgen4_reg: v33 {
230				regulator-min-microvolt = <2850000>;
231				regulator-max-microvolt = <3300000>;
232				regulator-always-on;
233			};
234
235			vgen5_reg: vldo3 {
236				regulator-min-microvolt = <1800000>;
237				regulator-max-microvolt = <3300000>;
238				regulator-always-on;
239			};
240
241			vgen6_reg: vldo4 {
242				regulator-min-microvolt = <1800000>;
243				regulator-max-microvolt = <3300000>;
244				regulator-always-on;
245			};
246		};
247	};
248};
249
250&i2c2 {
251	pinctrl-names = "default";
252	pinctrl-0 = <&pinctrl_i2c2>;
253	status = "okay";
254
255	rtc@68 {
256		compatible = "microcrystal,rv4162";
257		pinctrl-names = "default";
258		pinctrl-0 = <&pinctrl_i2c2_rv4162>;
259		reg = <0x68>;
260		interrupts-extended = <&gpio2 15 IRQ_TYPE_LEVEL_LOW>;
261	};
262};
263
264&i2c3 {
265	pinctrl-names = "default";
266	pinctrl-0 = <&pinctrl_i2c3>;
267	status = "okay";
268
269	touch@48 {
270		compatible = "ti,tsc2004";
271		reg = <0x48>;
272		pinctrl-names = "default";
273		pinctrl-0 = <&pinctrl_i2c3_tsc2004>;
274		interrupts-extended = <&gpio3 4 IRQ_TYPE_EDGE_FALLING>;
275		wakeup-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
276	};
277};
278
279&i2c4 {
280	pinctrl-names = "default";
281	pinctrl-0 = <&pinctrl_i2c4>;
282	status = "okay";
283
284	codec: wm8960@1a {
285		compatible = "wlf,wm8960";
286		reg = <0x1a>;
287		clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
288		clock-names = "mclk";
289		wlf,shared-lrclk;
290	};
291};
292
293&lcdif {
294	status = "okay";
295
296	port {
297		lcdif_out: endpoint {
298			remote-endpoint = <&panel_in>;
299		};
300	};
301};
302
303&pwm1 {
304	pinctrl-names = "default";
305	pinctrl-0 = <&pinctrl_pwm1>;
306	status = "okay";
307};
308
309&pwm2 {
310	pinctrl-names = "default";
311	pinctrl-0 = <&pinctrl_pwm2>;
312	status = "okay";
313};
314
315&uart1 {
316	pinctrl-names = "default";
317	pinctrl-0 = <&pinctrl_uart1>;
318	assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>;
319	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
320	status = "okay";
321};
322
323&uart2 {
324	pinctrl-names = "default";
325	pinctrl-0 = <&pinctrl_uart2>;
326	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
327	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
328	status = "okay";
329};
330
331&uart3 {
332	pinctrl-names = "default";
333	pinctrl-0 = <&pinctrl_uart3>;
334	assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>;
335	assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>;
336	status = "okay";
337};
338
339&uart6 {
340	pinctrl-names = "default";
341	pinctrl-0 = <&pinctrl_uart6>;
342	assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>;
343	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
344	uart-has-rtscts;
345	status = "okay";
346};
347
348&usbotg1 {
349	vbus-supply = <&reg_usb_otg1_vbus>;
350	pinctrl-names = "default";
351	pinctrl-0 = <&pinctrl_usbotg1>;
352	status = "okay";
353};
354
355&usbotg2 {
356	vbus-supply = <&reg_usb_otg2_vbus>;
357	pinctrl-names = "default";
358	pinctrl-0 = <&pinctrl_usbotg2>;
359	dr_mode = "host";
360	status = "okay";
361};
362
363&usdhc1 {
364	pinctrl-names = "default";
365	pinctrl-0 = <&pinctrl_usdhc1>;
366	cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
367	vmmc-supply = <&vgen3_reg>;
368	bus-width = <4>;
369	fsl,tuning-step = <2>;
370	wakeup-source;
371	keep-power-in-suspend;
372	status = "okay";
373};
374
375&usdhc2 {
376	#address-cells = <1>;
377	#size-cells = <0>;
378	pinctrl-names = "default";
379	pinctrl-0 = <&pinctrl_usdhc2>;
380	bus-width = <4>;
381	non-removable;
382	vmmc-supply = <&reg_wlan>;
383	mmc-pwrseq = <&usdhc2_pwrseq>;
384	cap-power-off-card;
385	keep-power-in-suspend;
386	status = "okay";
387
388	wlcore: wlcore@2 {
389		compatible = "ti,wl1271";
390		reg = <2>;
391		interrupt-parent = <&gpio4>;
392		interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
393		ref-clock-frequency = <38400000>;
394	};
395};
396
397&usdhc3 {
398	pinctrl-names = "default";
399	pinctrl-0 = <&pinctrl_usdhc3>;
400	assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
401	assigned-clock-rates = <400000000>;
402	bus-width = <8>;
403	fsl,tuning-step = <2>;
404	non-removable;
405	status = "okay";
406};
407
408&wdog1 {
409	pinctrl-names = "default";
410	pinctrl-0 = <&pinctrl_wdog1>;
411	status = "okay";
412};
413
414&iomuxc {
415	pinctrl-names = "default";
416	pinctrl-0 = <&pinctrl_hog_1 &pinctrl_j2>;
417
418	pinctrl_hog_1: hoggrp-1 {
419		fsl,pins = <
420			MX7D_PAD_SD3_RESET_B__GPIO6_IO11	0x5d
421			MX7D_PAD_GPIO1_IO13__GPIO1_IO13		0x7d
422			MX7D_PAD_ECSPI2_MISO__GPIO4_IO22	0x7d
423		>;
424	};
425
426	pinctrl_enet1: enet1grp {
427		fsl,pins = <
428			MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x3
429			MX7D_PAD_GPIO1_IO11__ENET1_MDC			0x3
430			MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1		0x3
431			MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC	0x71
432			MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0	0x71
433			MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1	0x71
434			MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2	0x71
435			MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3	0x71
436			MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL	0x71
437			MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC	0x71
438			MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0	0x11
439			MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1	0x11
440			MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2	0x11
441			MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3	0x71
442			MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	0x11
443			MX7D_PAD_SD3_STROBE__GPIO6_IO10			0x75
444		>;
445	};
446
447	pinctrl_flexcan2: flexcan2grp {
448		fsl,pins = <
449			MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX	0x7d
450			MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX	0x7d
451			MX7D_PAD_EPDC_DATA14__GPIO2_IO14	0x7d
452		>;
453	};
454
455	pinctrl_i2c1: i2c1grp {
456		fsl,pins = <
457			MX7D_PAD_I2C1_SDA__I2C1_SDA		0x4000007f
458			MX7D_PAD_I2C1_SCL__I2C1_SCL		0x4000007f
459		>;
460	};
461
462	pinctrl_i2c2: i2c2grp {
463		fsl,pins = <
464			MX7D_PAD_I2C2_SDA__I2C2_SDA		0x4000007f
465			MX7D_PAD_I2C2_SCL__I2C2_SCL		0x4000007f
466		>;
467	};
468
469	pinctrl_i2c2_rv4162: i2c2-rv4162grp {
470		fsl,pins = <
471			MX7D_PAD_EPDC_DATA15__GPIO2_IO15	0x7d
472		>;
473	};
474
475	pinctrl_i2c3: i2c3grp {
476		fsl,pins = <
477			MX7D_PAD_I2C3_SDA__I2C3_SDA		0x4000007f
478			MX7D_PAD_I2C3_SCL__I2C3_SCL		0x4000007f
479		>;
480	};
481
482	pinctrl_i2c3_tsc2004: i2c3tsc2004grp {
483		fsl,pins = <
484			MX7D_PAD_LCD_RESET__GPIO3_IO4		0x79
485			MX7D_PAD_SD2_WP__GPIO5_IO10		0x7d
486		>;
487	};
488
489	pinctrl_i2c4: i2c4grp {
490		fsl,pins = <
491			MX7D_PAD_I2C4_SDA__I2C4_SDA		0x4000007f
492			MX7D_PAD_I2C4_SCL__I2C4_SCL		0x4000007f
493		>;
494	};
495
496	pinctrl_j2: j2grp {
497		fsl,pins = <
498			MX7D_PAD_SAI1_TX_DATA__GPIO6_IO15	0x7d
499			MX7D_PAD_EPDC_BDR0__GPIO2_IO28		0x7d
500			MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12	0x7d
501			MX7D_PAD_EPDC_BDR1__GPIO2_IO29		0x7d
502			MX7D_PAD_SD1_WP__GPIO5_IO1		0x7d
503			MX7D_PAD_EPDC_SDSHR__GPIO2_IO19		0x7d
504			MX7D_PAD_SD1_RESET_B__GPIO5_IO2		0x7d
505			MX7D_PAD_SD2_RESET_B__GPIO5_IO11	0x7d
506			MX7D_PAD_EPDC_DATA07__GPIO2_IO7		0x7d
507			MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x7d
508			MX7D_PAD_EPDC_DATA09__GPIO2_IO9		0x7d
509			MX7D_PAD_EPDC_DATA10__GPIO2_IO10	0x7d
510			MX7D_PAD_EPDC_DATA11__GPIO2_IO11	0x7d
511			MX7D_PAD_EPDC_DATA12__GPIO2_IO12	0x7d
512			MX7D_PAD_SAI1_TX_SYNC__GPIO6_IO14	0x7d
513			MX7D_PAD_EPDC_DATA13__GPIO2_IO13	0x7d
514			MX7D_PAD_SAI1_TX_BCLK__GPIO6_IO13	0x7d
515			MX7D_PAD_SD2_CD_B__GPIO5_IO9		0x7d
516			MX7D_PAD_EPDC_GDCLK__GPIO2_IO24		0x7d
517			MX7D_PAD_SAI2_RX_DATA__GPIO6_IO21	0x7d
518			MX7D_PAD_EPDC_GDOE__GPIO2_IO25		0x7d
519			MX7D_PAD_EPDC_GDRL__GPIO2_IO26		0x7d
520			MX7D_PAD_SAI2_TX_DATA__GPIO6_IO22	0x7d
521			MX7D_PAD_EPDC_SDCE0__GPIO2_IO20		0x7d
522			MX7D_PAD_SAI2_TX_BCLK__GPIO6_IO20	0x7d
523			MX7D_PAD_EPDC_SDCE1__GPIO2_IO21		0x7d
524			MX7D_PAD_SAI2_TX_SYNC__GPIO6_IO19	0x7d
525			MX7D_PAD_EPDC_SDCE2__GPIO2_IO22		0x7d
526			MX7D_PAD_EPDC_SDCE3__GPIO2_IO23		0x7d
527			MX7D_PAD_EPDC_GDSP__GPIO2_IO27		0x7d
528			MX7D_PAD_EPDC_SDCLK__GPIO2_IO16		0x7d
529			MX7D_PAD_EPDC_SDLE__GPIO2_IO17		0x7d
530			MX7D_PAD_EPDC_SDOE__GPIO2_IO18		0x7d
531			MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30	0x7d
532			MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31	0x7d
533		>;
534	};
535
536	pinctrl_lcdif_dat: lcdifdatgrp {
537		fsl,pins = <
538			MX7D_PAD_LCD_DATA00__LCD_DATA0		0x79
539			MX7D_PAD_LCD_DATA01__LCD_DATA1		0x79
540			MX7D_PAD_LCD_DATA02__LCD_DATA2		0x79
541			MX7D_PAD_LCD_DATA03__LCD_DATA3		0x79
542			MX7D_PAD_LCD_DATA04__LCD_DATA4		0x79
543			MX7D_PAD_LCD_DATA05__LCD_DATA5		0x79
544			MX7D_PAD_LCD_DATA06__LCD_DATA6		0x79
545			MX7D_PAD_LCD_DATA07__LCD_DATA7		0x79
546			MX7D_PAD_LCD_DATA08__LCD_DATA8		0x79
547			MX7D_PAD_LCD_DATA09__LCD_DATA9		0x79
548			MX7D_PAD_LCD_DATA10__LCD_DATA10		0x79
549			MX7D_PAD_LCD_DATA11__LCD_DATA11		0x79
550			MX7D_PAD_LCD_DATA12__LCD_DATA12		0x79
551			MX7D_PAD_LCD_DATA13__LCD_DATA13		0x79
552			MX7D_PAD_LCD_DATA14__LCD_DATA14		0x79
553			MX7D_PAD_LCD_DATA15__LCD_DATA15		0x79
554			MX7D_PAD_LCD_DATA16__LCD_DATA16		0x79
555			MX7D_PAD_LCD_DATA17__LCD_DATA17		0x79
556			MX7D_PAD_LCD_DATA18__LCD_DATA18		0x79
557			MX7D_PAD_LCD_DATA19__LCD_DATA19		0x79
558			MX7D_PAD_LCD_DATA20__LCD_DATA20		0x79
559			MX7D_PAD_LCD_DATA21__LCD_DATA21		0x79
560			MX7D_PAD_LCD_DATA22__LCD_DATA22		0x79
561			MX7D_PAD_LCD_DATA23__LCD_DATA23		0x79
562		>;
563	};
564
565	pinctrl_lcdif_ctrl: lcdifctrlgrp {
566		fsl,pins = <
567			MX7D_PAD_LCD_CLK__LCD_CLK		0x79
568			MX7D_PAD_LCD_ENABLE__LCD_ENABLE		0x79
569			MX7D_PAD_LCD_VSYNC__LCD_VSYNC		0x79
570			MX7D_PAD_LCD_HSYNC__LCD_HSYNC		0x79
571		>;
572	};
573
574	pinctrl_pwm2: pwm2grp {
575		fsl,pins = <
576			MX7D_PAD_GPIO1_IO09__PWM2_OUT		0x7d
577		>;
578	};
579
580	pinctrl_uart1: uart1grp {
581		fsl,pins = <
582			MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX	0x79
583			MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX	0x79
584		>;
585	};
586
587	pinctrl_uart2: uart2grp {
588		fsl,pins = <
589			MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX	0x79
590			MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX	0x79
591		>;
592	};
593
594	pinctrl_uart3: uart3grp {
595		fsl,pins = <
596			MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX	0x79
597			MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX	0x79
598			MX7D_PAD_EPDC_DATA04__GPIO2_IO4		0x7d
599		>;
600	};
601
602	pinctrl_uart6: uart6grp {
603		fsl,pins = <
604			MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX	0x79
605			MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX	0x79
606			MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS	0x79
607			MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS	0x79
608		>;
609	};
610
611	pinctrl_usbotg2: usbotg2grp {
612		fsl,pins = <
613			MX7D_PAD_UART3_RTS_B__USB_OTG2_OC	0x7d
614			MX7D_PAD_UART3_CTS_B__GPIO4_IO7		0x14
615		>;
616	};
617
618	pinctrl_usdhc1: usdhc1grp {
619		fsl,pins = <
620			MX7D_PAD_SD1_CMD__SD1_CMD		0x59
621			MX7D_PAD_SD1_CLK__SD1_CLK		0x19
622			MX7D_PAD_SD1_DATA0__SD1_DATA0		0x59
623			MX7D_PAD_SD1_DATA1__SD1_DATA1		0x59
624			MX7D_PAD_SD1_DATA2__SD1_DATA2		0x59
625			MX7D_PAD_SD1_DATA3__SD1_DATA3		0x59
626			MX7D_PAD_GPIO1_IO08__SD1_VSELECT	0x75
627			MX7D_PAD_SD1_CD_B__GPIO5_IO0		0x75
628		>;
629	};
630
631	pinctrl_usdhc2: usdhc2grp {
632		fsl,pins = <
633			MX7D_PAD_SD2_CMD__SD2_CMD		0x59
634			MX7D_PAD_SD2_CLK__SD2_CLK		0x19
635			MX7D_PAD_SD2_DATA0__SD2_DATA0		0x59
636			MX7D_PAD_SD2_DATA1__SD2_DATA1		0x59
637			MX7D_PAD_SD2_DATA2__SD2_DATA2		0x59
638			MX7D_PAD_SD2_DATA3__SD2_DATA3		0x59
639			MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20	0x59
640			MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21	0x59
641		>;
642	};
643
644	pinctrl_usdhc3: usdhc3grp {
645		fsl,pins = <
646			MX7D_PAD_SD3_CMD__SD3_CMD		0x59
647			MX7D_PAD_SD3_CLK__SD3_CLK		0x19
648			MX7D_PAD_SD3_DATA0__SD3_DATA0		0x59
649			MX7D_PAD_SD3_DATA1__SD3_DATA1		0x59
650			MX7D_PAD_SD3_DATA2__SD3_DATA2		0x59
651			MX7D_PAD_SD3_DATA3__SD3_DATA3		0x59
652			MX7D_PAD_SD3_DATA4__SD3_DATA4		0x59
653			MX7D_PAD_SD3_DATA5__SD3_DATA5		0x59
654			MX7D_PAD_SD3_DATA6__SD3_DATA6		0x59
655			MX7D_PAD_SD3_DATA7__SD3_DATA7		0x59
656		>;
657	};
658};
659
660&iomuxc_lpsr {
661	pinctrl-names = "default";
662	pinctrl-0 = <&pinctrl_hog_2>;
663
664	pinctrl_hog_2: hoggrp-2 {
665		fsl,pins = <
666			MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2	0x7d
667			MX7D_PAD_LPSR_GPIO1_IO03__CCM_CLKO2	0x7d
668		>;
669	};
670
671	pinctrl_backlight_j9: backlightj9grp {
672		fsl,pins = <
673			MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7	0x7d
674		>;
675	};
676
677	pinctrl_pwm1: pwm1grp {
678		fsl,pins = <
679			MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT	0x7d
680		>;
681	};
682
683	pinctrl_usbotg1: usbotg1grp {
684		fsl,pins = <
685			MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC	0x7d
686			MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5	0x14
687		>;
688	};
689
690	pinctrl_wdog1: wdog1grp {
691		fsl,pins = <
692			MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B	0x75
693		>;
694	};
695};
696