1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright 2018 Toradex AG 4 */ 5 6#include "imx6ull.dtsi" 7 8/ { 9 aliases { 10 ethernet0 = &fec2; 11 ethernet1 = &fec1; 12 }; 13 14 bl: backlight { 15 compatible = "pwm-backlight"; 16 pinctrl-names = "default"; 17 pinctrl-0 = <&pinctrl_gpio_bl_on>; 18 enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; 19 status = "disabled"; 20 }; 21 22 reg_module_3v3: regulator-module-3v3 { 23 compatible = "regulator-fixed"; 24 regulator-always-on; 25 regulator-name = "+V3.3"; 26 regulator-min-microvolt = <3300000>; 27 regulator-max-microvolt = <3300000>; 28 }; 29 30 reg_module_3v3_avdd: regulator-module-3v3-avdd { 31 compatible = "regulator-fixed"; 32 regulator-always-on; 33 regulator-name = "+V3.3_AVDD_AUDIO"; 34 regulator-min-microvolt = <3300000>; 35 regulator-max-microvolt = <3300000>; 36 }; 37 38 reg_sd1_vmmc: regulator-sd1-vmmc { 39 compatible = "regulator-gpio"; 40 gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; 41 pinctrl-names = "default"; 42 pinctrl-0 = <&pinctrl_snvs_reg_sd>; 43 regulator-always-on; 44 regulator-name = "+V3.3_1.8_SD"; 45 regulator-min-microvolt = <1800000>; 46 regulator-max-microvolt = <3300000>; 47 states = <1800000 0x1 3300000 0x0>; 48 vin-supply = <®_module_3v3>; 49 }; 50}; 51 52&adc1 { 53 num-channels = <10>; 54 vref-supply = <®_module_3v3_avdd>; 55}; 56 57/* Colibri SPI */ 58&ecspi1 { 59 cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; 62}; 63 64&fec2 { 65 pinctrl-names = "default"; 66 pinctrl-0 = <&pinctrl_enet2>; 67 phy-mode = "rmii"; 68 phy-handle = <ðphy1>; 69 status = "okay"; 70 71 mdio { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 75 ethphy1: ethernet-phy@2 { 76 compatible = "ethernet-phy-ieee802.3-c22"; 77 max-speed = <100>; 78 reg = <2>; 79 }; 80 }; 81}; 82 83&gpmi { 84 pinctrl-names = "default"; 85 pinctrl-0 = <&pinctrl_gpmi_nand>; 86 nand-on-flash-bbt; 87 nand-ecc-mode = "hw"; 88 nand-ecc-strength = <8>; 89 nand-ecc-step-size = <512>; 90 status = "okay"; 91}; 92 93&i2c1 { 94 pinctrl-names = "default", "gpio"; 95 pinctrl-0 = <&pinctrl_i2c1>; 96 pinctrl-1 = <&pinctrl_i2c1_gpio>; 97 sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 98 scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 99}; 100 101&i2c2 { 102 pinctrl-names = "default", "gpio"; 103 pinctrl-0 = <&pinctrl_i2c2>; 104 pinctrl-1 = <&pinctrl_i2c2_gpio>; 105 sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 106 scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 107 status = "okay"; 108 109 ad7879@2c { 110 compatible = "adi,ad7879-1"; 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pinctrl_snvs_ad7879_int>; 113 reg = <0x2c>; 114 interrupt-parent = <&gpio5>; 115 interrupts = <7 IRQ_TYPE_EDGE_FALLING>; 116 touchscreen-max-pressure = <4096>; 117 adi,resistance-plate-x = <120>; 118 adi,first-conversion-delay = /bits/ 8 <3>; 119 adi,acquisition-time = /bits/ 8 <1>; 120 adi,median-filter-size = /bits/ 8 <2>; 121 adi,averaging = /bits/ 8 <1>; 122 adi,conversion-interval = /bits/ 8 <255>; 123 }; 124}; 125 126&lcdif { 127 pinctrl-names = "default"; 128 pinctrl-0 = <&pinctrl_lcdif_dat 129 &pinctrl_lcdif_ctrl>; 130}; 131 132&pwm4 { 133 pinctrl-names = "default"; 134 pinctrl-0 = <&pinctrl_pwm4>; 135 #pwm-cells = <3>; 136}; 137 138&pwm5 { 139 pinctrl-names = "default"; 140 pinctrl-0 = <&pinctrl_pwm5>; 141 #pwm-cells = <3>; 142}; 143 144&pwm6 { 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_pwm6>; 147 #pwm-cells = <3>; 148}; 149 150&pwm7 { 151 pinctrl-names = "default"; 152 pinctrl-0 = <&pinctrl_pwm7>; 153 #pwm-cells = <3>; 154}; 155 156&sdma { 157 status = "okay"; 158}; 159 160&snvs_pwrkey { 161 status = "disabled"; 162}; 163 164&uart1 { 165 pinctrl-names = "default"; 166 pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; 167 uart-has-rtscts; 168 fsl,dte-mode; 169}; 170 171&uart2 { 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_uart2>; 174 uart-has-rtscts; 175 fsl,dte-mode; 176}; 177 178&uart5 { 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_uart5>; 181 fsl,dte-mode; 182}; 183 184&usbotg1 { 185 dr_mode = "otg"; 186 srp-disable; 187 hnp-disable; 188 adp-disable; 189}; 190 191&usbotg2 { 192 dr_mode = "host"; 193}; 194 195&usdhc1 { 196 assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; 197 assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; 198 assigned-clock-rates = <0>, <198000000>; 199}; 200 201&iomuxc { 202 pinctrl_can_int: canint-grp { 203 fsl,pins = < 204 MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */ 205 >; 206 }; 207 208 pinctrl_enet2: enet2-grp { 209 fsl,pins = < 210 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 211 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 212 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 213 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 214 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 215 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 216 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 217 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 218 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 219 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 220 >; 221 }; 222 223 pinctrl_ecspi1_cs: ecspi1-cs-grp { 224 fsl,pins = < 225 MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0 226 >; 227 }; 228 229 pinctrl_ecspi1: ecspi1-grp { 230 fsl,pins = < 231 MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 232 MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 233 MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 234 >; 235 }; 236 237 pinctrl_flexcan2: flexcan2-grp { 238 fsl,pins = < 239 MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 240 MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 241 >; 242 }; 243 244 pinctrl_gpio_bl_on: gpio-bl-on-grp { 245 fsl,pins = < 246 MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0 247 >; 248 }; 249 250 pinctrl_gpio1: gpio1-grp { 251 fsl,pins = < 252 MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */ 253 MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */ 254 MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */ 255 MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */ 256 MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */ 257 MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */ 258 MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */ 259 MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */ 260 MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */ 261 MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */ 262 >; 263 }; 264 265 pinctrl_gpio2: gpio2-grp { /* Camera */ 266 fsl,pins = < 267 MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */ 268 MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */ 269 MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */ 270 MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */ 271 MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */ 272 >; 273 }; 274 275 pinctrl_gpio3: gpio3-grp { /* CAN2 */ 276 fsl,pins = < 277 MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */ 278 MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */ 279 >; 280 }; 281 282 pinctrl_gpio4: gpio4-grp { 283 fsl,pins = < 284 MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */ 285 >; 286 }; 287 288 pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ 289 fsl,pins = < 290 MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */ 291 >; 292 }; 293 294 pinctrl_gpio6: gpio6-grp { /* Wifi pins */ 295 fsl,pins = < 296 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */ 297 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */ 298 MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */ 299 MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */ 300 MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */ 301 MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */ 302 MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */ 303 >; 304 }; 305 306 pinctrl_gpmi_nand: gpmi-nand-grp { 307 fsl,pins = < 308 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 309 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 310 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 311 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 312 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 313 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 314 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 315 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 316 MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 317 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 318 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 319 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 320 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 321 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 322 >; 323 }; 324 325 pinctrl_i2c1: i2c1-grp { 326 fsl,pins = < 327 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 328 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 329 >; 330 }; 331 332 pinctrl_i2c1_gpio: i2c1-gpio-grp { 333 fsl,pins = < 334 MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 335 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 336 >; 337 }; 338 339 pinctrl_i2c2: i2c2-grp { 340 fsl,pins = < 341 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 342 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 343 >; 344 }; 345 346 pinctrl_i2c2_gpio: i2c2-gpio-grp { 347 fsl,pins = < 348 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 349 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 350 >; 351 }; 352 353 pinctrl_lcdif_dat: lcdif-dat-grp { 354 fsl,pins = < 355 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 356 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 357 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 358 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 359 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 360 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 361 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 362 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 363 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 364 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 365 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 366 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 367 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 368 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 369 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 370 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 371 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 372 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 373 >; 374 }; 375 376 pinctrl_lcdif_ctrl: lcdif-ctrl-grp { 377 fsl,pins = < 378 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 379 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 380 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 381 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 382 >; 383 }; 384 385 pinctrl_pwm4: pwm4-grp { 386 fsl,pins = < 387 MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 388 >; 389 }; 390 391 pinctrl_pwm5: pwm5-grp { 392 fsl,pins = < 393 MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 394 >; 395 }; 396 397 pinctrl_pwm6: pwm6-grp { 398 fsl,pins = < 399 MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 400 >; 401 }; 402 403 pinctrl_pwm7: pwm7-grp { 404 fsl,pins = < 405 MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 406 >; 407 }; 408 409 pinctrl_uart1: uart1-grp { 410 fsl,pins = < 411 MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 412 MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 413 MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 414 MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 415 >; 416 }; 417 418 pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ 419 fsl,pins = < 420 MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */ 421 MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */ 422 MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */ 423 MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */ 424 >; 425 }; 426 427 pinctrl_uart2: uart2-grp { 428 fsl,pins = < 429 MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 430 MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 431 MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 432 MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 433 >; 434 }; 435 pinctrl_uart5: uart5-grp { 436 fsl,pins = < 437 MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 438 MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 439 >; 440 }; 441 442 pinctrl_usbh_reg: gpio-usbh-reg { 443 fsl,pins = < 444 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */ 445 >; 446 }; 447 448 pinctrl_usdhc1: usdhc1-grp { 449 fsl,pins = < 450 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 451 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 452 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 453 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 454 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 455 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 456 >; 457 }; 458 459 pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { 460 fsl,pins = < 461 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 462 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 463 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 464 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 465 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 466 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 467 >; 468 }; 469 470 pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { 471 fsl,pins = < 472 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 473 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 474 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 475 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 476 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 477 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 478 >; 479 }; 480 481 pinctrl_usdhc2: usdhc2-grp { 482 fsl,pins = < 483 MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 484 MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 485 MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 486 MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 487 MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 488 MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 489 490 MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x14 491 >; 492 }; 493}; 494 495&iomuxc_snvs { 496 pinctrl_snvs_gpio1: snvs-gpio1-grp { 497 fsl,pins = < 498 MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */ 499 MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */ 500 MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */ 501 MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */ 502 MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */ 503 >; 504 }; 505 506 pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ 507 fsl,pins = < 508 MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */ 509 >; 510 }; 511 512 pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ 513 fsl,pins = < 514 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */ 515 >; 516 }; 517 518 pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ 519 fsl,pins = < 520 MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0b0 521 >; 522 }; 523 524 pinctrl_snvs_reg_sd: snvs-reg-sd-grp { 525 fsl,pins = < 526 MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x4001b8b0 527 >; 528 }; 529 530 pinctrl_snvs_usbc_det: snvs-usbc-det-grp { 531 fsl,pins = < 532 MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 533 >; 534 }; 535 536 pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { 537 fsl,pins = < 538 MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0 539 >; 540 }; 541 542 pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { 543 fsl,pins = < 544 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */ 545 >; 546 }; 547 548 pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { 549 fsl,pins = < 550 MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 551 >; 552 }; 553 554 pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { 555 fsl,pins = < 556 MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 557 >; 558 }; 559}; 560
