1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2011 Freescale Semiconductor, Inc. 4// Copyright 2011 Linaro Ltd. 5 6#include <dt-bindings/clock/imx6qdl-clock.h> 7#include <dt-bindings/input/input.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/ { 11 #address-cells = <1>; 12 #size-cells = <1>; 13 /* 14 * The decompressor and also some bootloaders rely on a 15 * pre-existing /chosen node to be available to insert the 16 * command line and merge other ATAGS info. 17 */ 18 chosen {}; 19 20 aliases { 21 ethernet0 = &fec; 22 can0 = &can1; 23 can1 = &can2; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 gpio4 = &gpio5; 29 gpio5 = &gpio6; 30 gpio6 = &gpio7; 31 i2c0 = &i2c1; 32 i2c1 = &i2c2; 33 i2c2 = &i2c3; 34 ipu0 = &ipu1; 35 mmc0 = &usdhc1; 36 mmc1 = &usdhc2; 37 mmc2 = &usdhc3; 38 mmc3 = &usdhc4; 39 serial0 = &uart1; 40 serial1 = &uart2; 41 serial2 = &uart3; 42 serial3 = &uart4; 43 serial4 = &uart5; 44 spi0 = &ecspi1; 45 spi1 = &ecspi2; 46 spi2 = &ecspi3; 47 spi3 = &ecspi4; 48 usbphy0 = &usbphy1; 49 usbphy1 = &usbphy2; 50 }; 51 52 clocks { 53 ckil { 54 compatible = "fsl,imx-ckil", "fixed-clock"; 55 #clock-cells = <0>; 56 clock-frequency = <32768>; 57 }; 58 59 ckih1 { 60 compatible = "fsl,imx-ckih1", "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <0>; 63 }; 64 65 osc { 66 compatible = "fsl,imx-osc", "fixed-clock"; 67 #clock-cells = <0>; 68 clock-frequency = <24000000>; 69 }; 70 }; 71 72 tempmon: tempmon { 73 compatible = "fsl,imx6q-tempmon"; 74 interrupt-parent = <&gpc>; 75 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 76 fsl,tempmon = <&anatop>; 77 fsl,tempmon-data = <&ocotp>; 78 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 79 #thermal-sensor-cells = <0>; 80 }; 81 82 ldb: ldb { 83 #address-cells = <1>; 84 #size-cells = <0>; 85 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb"; 86 gpr = <&gpr>; 87 status = "disabled"; 88 89 lvds-channel@0 { 90 #address-cells = <1>; 91 #size-cells = <0>; 92 reg = <0>; 93 status = "disabled"; 94 95 port@0 { 96 reg = <0>; 97 98 lvds0_mux_0: endpoint { 99 remote-endpoint = <&ipu1_di0_lvds0>; 100 }; 101 }; 102 103 port@1 { 104 reg = <1>; 105 106 lvds0_mux_1: endpoint { 107 remote-endpoint = <&ipu1_di1_lvds0>; 108 }; 109 }; 110 }; 111 112 lvds-channel@1 { 113 #address-cells = <1>; 114 #size-cells = <0>; 115 reg = <1>; 116 status = "disabled"; 117 118 port@0 { 119 reg = <0>; 120 121 lvds1_mux_0: endpoint { 122 remote-endpoint = <&ipu1_di0_lvds1>; 123 }; 124 }; 125 126 port@1 { 127 reg = <1>; 128 129 lvds1_mux_1: endpoint { 130 remote-endpoint = <&ipu1_di1_lvds1>; 131 }; 132 }; 133 }; 134 }; 135 136 pmu: pmu { 137 compatible = "arm,cortex-a9-pmu"; 138 interrupt-parent = <&gpc>; 139 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 140 }; 141 142 usbphynop1: usbphynop1 { 143 compatible = "usb-nop-xceiv"; 144 #phy-cells = <0>; 145 }; 146 147 usbphynop2: usbphynop2 { 148 compatible = "usb-nop-xceiv"; 149 #phy-cells = <0>; 150 }; 151 152 soc { 153 #address-cells = <1>; 154 #size-cells = <1>; 155 compatible = "simple-bus"; 156 interrupt-parent = <&gpc>; 157 ranges; 158 159 dma_apbh: dma-apbh@110000 { 160 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; 161 reg = <0x00110000 0x2000>; 162 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, 163 <0 13 IRQ_TYPE_LEVEL_HIGH>, 164 <0 13 IRQ_TYPE_LEVEL_HIGH>, 165 <0 13 IRQ_TYPE_LEVEL_HIGH>; 166 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; 167 #dma-cells = <1>; 168 dma-channels = <4>; 169 clocks = <&clks IMX6QDL_CLK_APBH_DMA>; 170 }; 171 172 gpmi: gpmi-nand@112000 { 173 compatible = "fsl,imx6q-gpmi-nand"; 174 reg = <0x00112000 0x2000>, <0x00114000 0x2000>; 175 reg-names = "gpmi-nand", "bch"; 176 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; 177 interrupt-names = "bch"; 178 clocks = <&clks IMX6QDL_CLK_GPMI_IO>, 179 <&clks IMX6QDL_CLK_GPMI_APB>, 180 <&clks IMX6QDL_CLK_GPMI_BCH>, 181 <&clks IMX6QDL_CLK_GPMI_BCH_APB>, 182 <&clks IMX6QDL_CLK_PER1_BCH>; 183 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", 184 "gpmi_bch_apb", "per1_bch"; 185 dmas = <&dma_apbh 0>; 186 dma-names = "rx-tx"; 187 status = "disabled"; 188 }; 189 190 hdmi: hdmi@120000 { 191 #address-cells = <1>; 192 #size-cells = <0>; 193 reg = <0x00120000 0x9000>; 194 interrupts = <0 115 0x04>; 195 gpr = <&gpr>; 196 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>, 197 <&clks IMX6QDL_CLK_HDMI_ISFR>; 198 clock-names = "iahb", "isfr"; 199 status = "disabled"; 200 201 port@0 { 202 reg = <0>; 203 204 hdmi_mux_0: endpoint { 205 remote-endpoint = <&ipu1_di0_hdmi>; 206 }; 207 }; 208 209 port@1 { 210 reg = <1>; 211 212 hdmi_mux_1: endpoint { 213 remote-endpoint = <&ipu1_di1_hdmi>; 214 }; 215 }; 216 }; 217 218 gpu_3d: gpu@130000 { 219 compatible = "vivante,gc"; 220 reg = <0x00130000 0x4000>; 221 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>, 223 <&clks IMX6QDL_CLK_GPU3D_CORE>, 224 <&clks IMX6QDL_CLK_GPU3D_SHADER>; 225 clock-names = "bus", "core", "shader"; 226 power-domains = <&pd_pu>; 227 #cooling-cells = <2>; 228 }; 229 230 gpu_2d: gpu@134000 { 231 compatible = "vivante,gc"; 232 reg = <0x00134000 0x4000>; 233 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&clks IMX6QDL_CLK_GPU2D_AXI>, 235 <&clks IMX6QDL_CLK_GPU2D_CORE>; 236 clock-names = "bus", "core"; 237 power-domains = <&pd_pu>; 238 #cooling-cells = <2>; 239 }; 240 241 timer@a00600 { 242 compatible = "arm,cortex-a9-twd-timer"; 243 reg = <0x00a00600 0x20>; 244 interrupts = <1 13 0xf01>; 245 interrupt-parent = <&intc>; 246 clocks = <&clks IMX6QDL_CLK_TWD>; 247 }; 248 249 intc: interrupt-controller@a01000 { 250 compatible = "arm,cortex-a9-gic"; 251 #interrupt-cells = <3>; 252 interrupt-controller; 253 reg = <0x00a01000 0x1000>, 254 <0x00a00100 0x100>; 255 interrupt-parent = <&intc>; 256 }; 257 258 L2: l2-cache@a02000 { 259 compatible = "arm,pl310-cache"; 260 reg = <0x00a02000 0x1000>; 261 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 262 cache-unified; 263 cache-level = <2>; 264 arm,tag-latency = <4 2 3>; 265 arm,data-latency = <4 2 3>; 266 arm,shared-override; 267 }; 268 269 pcie: pcie@1ffc000 { 270 compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; 271 reg = <0x01ffc000 0x04000>, 272 <0x01f00000 0x80000>; 273 reg-names = "dbi", "config"; 274 #address-cells = <3>; 275 #size-cells = <2>; 276 device_type = "pci"; 277 bus-range = <0x00 0xff>; 278 ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 279 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ 280 num-lanes = <1>; 281 num-viewport = <4>; 282 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 283 interrupt-names = "msi"; 284 #interrupt-cells = <1>; 285 interrupt-map-mask = <0 0 0 0x7>; 286 interrupt-map = <0 0 0 1 &gpc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 287 <0 0 0 2 &gpc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 288 <0 0 0 3 &gpc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 289 <0 0 0 4 &gpc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 290 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>, 291 <&clks IMX6QDL_CLK_LVDS1_GATE>, 292 <&clks IMX6QDL_CLK_PCIE_REF_125M>; 293 clock-names = "pcie", "pcie_bus", "pcie_phy"; 294 status = "disabled"; 295 }; 296 297 aips-bus@2000000 { /* AIPS1 */ 298 compatible = "fsl,aips-bus", "simple-bus"; 299 #address-cells = <1>; 300 #size-cells = <1>; 301 reg = <0x02000000 0x100000>; 302 ranges; 303 304 spba-bus@2000000 { 305 compatible = "fsl,spba-bus", "simple-bus"; 306 #address-cells = <1>; 307 #size-cells = <1>; 308 reg = <0x02000000 0x40000>; 309 ranges; 310 311 spdif: spdif@2004000 { 312 compatible = "fsl,imx35-spdif"; 313 reg = <0x02004000 0x4000>; 314 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 315 dmas = <&sdma 14 18 0>, 316 <&sdma 15 18 0>; 317 dma-names = "rx", "tx"; 318 clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, 319 <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, 320 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, 321 <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, 322 <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; 323 clock-names = "core", "rxtx0", 324 "rxtx1", "rxtx2", 325 "rxtx3", "rxtx4", 326 "rxtx5", "rxtx6", 327 "rxtx7", "spba"; 328 status = "disabled"; 329 }; 330 331 ecspi1: spi@2008000 { 332 #address-cells = <1>; 333 #size-cells = <0>; 334 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 335 reg = <0x02008000 0x4000>; 336 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 337 clocks = <&clks IMX6QDL_CLK_ECSPI1>, 338 <&clks IMX6QDL_CLK_ECSPI1>; 339 clock-names = "ipg", "per"; 340 dmas = <&sdma 3 8 1>, <&sdma 4 8 2>; 341 dma-names = "rx", "tx"; 342 status = "disabled"; 343 }; 344 345 ecspi2: spi@200c000 { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 349 reg = <0x0200c000 0x4000>; 350 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 351 clocks = <&clks IMX6QDL_CLK_ECSPI2>, 352 <&clks IMX6QDL_CLK_ECSPI2>; 353 clock-names = "ipg", "per"; 354 dmas = <&sdma 5 8 1>, <&sdma 6 8 2>; 355 dma-names = "rx", "tx"; 356 status = "disabled"; 357 }; 358 359 ecspi3: spi@2010000 { 360 #address-cells = <1>; 361 #size-cells = <0>; 362 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 363 reg = <0x02010000 0x4000>; 364 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 365 clocks = <&clks IMX6QDL_CLK_ECSPI3>, 366 <&clks IMX6QDL_CLK_ECSPI3>; 367 clock-names = "ipg", "per"; 368 dmas = <&sdma 7 8 1>, <&sdma 8 8 2>; 369 dma-names = "rx", "tx"; 370 status = "disabled"; 371 }; 372 373 ecspi4: spi@2014000 { 374 #address-cells = <1>; 375 #size-cells = <0>; 376 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; 377 reg = <0x02014000 0x4000>; 378 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&clks IMX6QDL_CLK_ECSPI4>, 380 <&clks IMX6QDL_CLK_ECSPI4>; 381 clock-names = "ipg", "per"; 382 dmas = <&sdma 9 8 1>, <&sdma 10 8 2>; 383 dma-names = "rx", "tx"; 384 status = "disabled"; 385 }; 386 387 uart1: serial@2020000 { 388 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 389 reg = <0x02020000 0x4000>; 390 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 392 <&clks IMX6QDL_CLK_UART_SERIAL>; 393 clock-names = "ipg", "per"; 394 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 395 dma-names = "rx", "tx"; 396 status = "disabled"; 397 }; 398 399 esai: esai@2024000 { 400 #sound-dai-cells = <0>; 401 compatible = "fsl,imx35-esai"; 402 reg = <0x02024000 0x4000>; 403 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&clks IMX6QDL_CLK_ESAI_IPG>, 405 <&clks IMX6QDL_CLK_ESAI_MEM>, 406 <&clks IMX6QDL_CLK_ESAI_EXTAL>, 407 <&clks IMX6QDL_CLK_ESAI_IPG>, 408 <&clks IMX6QDL_CLK_SPBA>; 409 clock-names = "core", "mem", "extal", "fsys", "spba"; 410 dmas = <&sdma 23 21 0>, <&sdma 24 21 0>; 411 dma-names = "rx", "tx"; 412 status = "disabled"; 413 }; 414 415 ssi1: ssi@2028000 { 416 #sound-dai-cells = <0>; 417 compatible = "fsl,imx6q-ssi", 418 "fsl,imx51-ssi"; 419 reg = <0x02028000 0x4000>; 420 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 421 clocks = <&clks IMX6QDL_CLK_SSI1_IPG>, 422 <&clks IMX6QDL_CLK_SSI1>; 423 clock-names = "ipg", "baud"; 424 dmas = <&sdma 37 1 0>, 425 <&sdma 38 1 0>; 426 dma-names = "rx", "tx"; 427 fsl,fifo-depth = <15>; 428 status = "disabled"; 429 }; 430 431 ssi2: ssi@202c000 { 432 #sound-dai-cells = <0>; 433 compatible = "fsl,imx6q-ssi", 434 "fsl,imx51-ssi"; 435 reg = <0x0202c000 0x4000>; 436 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 437 clocks = <&clks IMX6QDL_CLK_SSI2_IPG>, 438 <&clks IMX6QDL_CLK_SSI2>; 439 clock-names = "ipg", "baud"; 440 dmas = <&sdma 41 1 0>, 441 <&sdma 42 1 0>; 442 dma-names = "rx", "tx"; 443 fsl,fifo-depth = <15>; 444 status = "disabled"; 445 }; 446 447 ssi3: ssi@2030000 { 448 #sound-dai-cells = <0>; 449 compatible = "fsl,imx6q-ssi", 450 "fsl,imx51-ssi"; 451 reg = <0x02030000 0x4000>; 452 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&clks IMX6QDL_CLK_SSI3_IPG>, 454 <&clks IMX6QDL_CLK_SSI3>; 455 clock-names = "ipg", "baud"; 456 dmas = <&sdma 45 1 0>, 457 <&sdma 46 1 0>; 458 dma-names = "rx", "tx"; 459 fsl,fifo-depth = <15>; 460 status = "disabled"; 461 }; 462 463 asrc: asrc@2034000 { 464 compatible = "fsl,imx53-asrc"; 465 reg = <0x02034000 0x4000>; 466 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&clks IMX6QDL_CLK_ASRC_IPG>, 468 <&clks IMX6QDL_CLK_ASRC_MEM>, <&clks 0>, 469 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 470 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 471 <&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>, 472 <&clks IMX6QDL_CLK_ASRC>, <&clks 0>, <&clks 0>, 473 <&clks IMX6QDL_CLK_SPBA>; 474 clock-names = "mem", "ipg", "asrck_0", 475 "asrck_1", "asrck_2", "asrck_3", "asrck_4", 476 "asrck_5", "asrck_6", "asrck_7", "asrck_8", 477 "asrck_9", "asrck_a", "asrck_b", "asrck_c", 478 "asrck_d", "asrck_e", "asrck_f", "spba"; 479 dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>, 480 <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; 481 dma-names = "rxa", "rxb", "rxc", 482 "txa", "txb", "txc"; 483 fsl,asrc-rate = <48000>; 484 fsl,asrc-width = <16>; 485 status = "okay"; 486 }; 487 488 spba@203c000 { 489 reg = <0x0203c000 0x4000>; 490 }; 491 }; 492 493 vpu: vpu@2040000 { 494 compatible = "cnm,coda960"; 495 reg = <0x02040000 0x3c000>; 496 interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>, 497 <0 3 IRQ_TYPE_LEVEL_HIGH>; 498 interrupt-names = "bit", "jpeg"; 499 clocks = <&clks IMX6QDL_CLK_VPU_AXI>, 500 <&clks IMX6QDL_CLK_MMDC_CH0_AXI>; 501 clock-names = "per", "ahb"; 502 power-domains = <&pd_pu>; 503 resets = <&src 1>; 504 iram = <&ocram>; 505 }; 506 507 aipstz@207c000 { /* AIPSTZ1 */ 508 reg = <0x0207c000 0x4000>; 509 }; 510 511 pwm1: pwm@2080000 { 512 #pwm-cells = <2>; 513 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 514 reg = <0x02080000 0x4000>; 515 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 516 clocks = <&clks IMX6QDL_CLK_IPG>, 517 <&clks IMX6QDL_CLK_PWM1>; 518 clock-names = "ipg", "per"; 519 status = "disabled"; 520 }; 521 522 pwm2: pwm@2084000 { 523 #pwm-cells = <2>; 524 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 525 reg = <0x02084000 0x4000>; 526 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 527 clocks = <&clks IMX6QDL_CLK_IPG>, 528 <&clks IMX6QDL_CLK_PWM2>; 529 clock-names = "ipg", "per"; 530 status = "disabled"; 531 }; 532 533 pwm3: pwm@2088000 { 534 #pwm-cells = <2>; 535 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 536 reg = <0x02088000 0x4000>; 537 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 538 clocks = <&clks IMX6QDL_CLK_IPG>, 539 <&clks IMX6QDL_CLK_PWM3>; 540 clock-names = "ipg", "per"; 541 status = "disabled"; 542 }; 543 544 pwm4: pwm@208c000 { 545 #pwm-cells = <2>; 546 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; 547 reg = <0x0208c000 0x4000>; 548 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&clks IMX6QDL_CLK_IPG>, 550 <&clks IMX6QDL_CLK_PWM4>; 551 clock-names = "ipg", "per"; 552 status = "disabled"; 553 }; 554 555 can1: flexcan@2090000 { 556 compatible = "fsl,imx6q-flexcan"; 557 reg = <0x02090000 0x4000>; 558 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&clks IMX6QDL_CLK_CAN1_IPG>, 560 <&clks IMX6QDL_CLK_CAN1_SERIAL>; 561 clock-names = "ipg", "per"; 562 fsl,stop-mode = <&gpr 0x34 28 0x10 17>; 563 status = "disabled"; 564 }; 565 566 can2: flexcan@2094000 { 567 compatible = "fsl,imx6q-flexcan"; 568 reg = <0x02094000 0x4000>; 569 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&clks IMX6QDL_CLK_CAN2_IPG>, 571 <&clks IMX6QDL_CLK_CAN2_SERIAL>; 572 clock-names = "ipg", "per"; 573 fsl,stop-mode = <&gpr 0x34 29 0x10 18>; 574 status = "disabled"; 575 }; 576 577 gpt: gpt@2098000 { 578 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; 579 reg = <0x02098000 0x4000>; 580 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 581 clocks = <&clks IMX6QDL_CLK_GPT_IPG>, 582 <&clks IMX6QDL_CLK_GPT_IPG_PER>, 583 <&clks IMX6QDL_CLK_GPT_3M>; 584 clock-names = "ipg", "per", "osc_per"; 585 }; 586 587 gpio1: gpio@209c000 { 588 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 589 reg = <0x0209c000 0x4000>; 590 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 591 <0 67 IRQ_TYPE_LEVEL_HIGH>; 592 gpio-controller; 593 #gpio-cells = <2>; 594 interrupt-controller; 595 #interrupt-cells = <2>; 596 }; 597 598 gpio2: gpio@20a0000 { 599 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 600 reg = <0x020a0000 0x4000>; 601 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 602 <0 69 IRQ_TYPE_LEVEL_HIGH>; 603 gpio-controller; 604 #gpio-cells = <2>; 605 interrupt-controller; 606 #interrupt-cells = <2>; 607 }; 608 609 gpio3: gpio@20a4000 { 610 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 611 reg = <0x020a4000 0x4000>; 612 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 613 <0 71 IRQ_TYPE_LEVEL_HIGH>; 614 gpio-controller; 615 #gpio-cells = <2>; 616 interrupt-controller; 617 #interrupt-cells = <2>; 618 }; 619 620 gpio4: gpio@20a8000 { 621 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 622 reg = <0x020a8000 0x4000>; 623 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 624 <0 73 IRQ_TYPE_LEVEL_HIGH>; 625 gpio-controller; 626 #gpio-cells = <2>; 627 interrupt-controller; 628 #interrupt-cells = <2>; 629 }; 630 631 gpio5: gpio@20ac000 { 632 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 633 reg = <0x020ac000 0x4000>; 634 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 635 <0 75 IRQ_TYPE_LEVEL_HIGH>; 636 gpio-controller; 637 #gpio-cells = <2>; 638 interrupt-controller; 639 #interrupt-cells = <2>; 640 }; 641 642 gpio6: gpio@20b0000 { 643 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 644 reg = <0x020b0000 0x4000>; 645 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>, 646 <0 77 IRQ_TYPE_LEVEL_HIGH>; 647 gpio-controller; 648 #gpio-cells = <2>; 649 interrupt-controller; 650 #interrupt-cells = <2>; 651 }; 652 653 gpio7: gpio@20b4000 { 654 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; 655 reg = <0x020b4000 0x4000>; 656 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>, 657 <0 79 IRQ_TYPE_LEVEL_HIGH>; 658 gpio-controller; 659 #gpio-cells = <2>; 660 interrupt-controller; 661 #interrupt-cells = <2>; 662 }; 663 664 kpp: kpp@20b8000 { 665 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp"; 666 reg = <0x020b8000 0x4000>; 667 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 668 clocks = <&clks IMX6QDL_CLK_IPG>; 669 status = "disabled"; 670 }; 671 672 wdog1: wdog@20bc000 { 673 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 674 reg = <0x020bc000 0x4000>; 675 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 676 clocks = <&clks IMX6QDL_CLK_IPG>; 677 }; 678 679 wdog2: wdog@20c0000 { 680 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; 681 reg = <0x020c0000 0x4000>; 682 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 683 clocks = <&clks IMX6QDL_CLK_IPG>; 684 status = "disabled"; 685 }; 686 687 clks: ccm@20c4000 { 688 compatible = "fsl,imx6q-ccm"; 689 reg = <0x020c4000 0x4000>; 690 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 691 <0 88 IRQ_TYPE_LEVEL_HIGH>; 692 #clock-cells = <1>; 693 }; 694 695 anatop: anatop@20c8000 { 696 compatible = "fsl,imx6q-anatop", "syscon", "simple-mfd"; 697 reg = <0x020c8000 0x1000>; 698 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 699 <0 54 IRQ_TYPE_LEVEL_HIGH>, 700 <0 127 IRQ_TYPE_LEVEL_HIGH>; 701 702 reg_vdd1p1: regulator-1p1 { 703 compatible = "fsl,anatop-regulator"; 704 regulator-name = "vdd1p1"; 705 regulator-min-microvolt = <1000000>; 706 regulator-max-microvolt = <1200000>; 707 regulator-always-on; 708 anatop-reg-offset = <0x110>; 709 anatop-vol-bit-shift = <8>; 710 anatop-vol-bit-width = <5>; 711 anatop-min-bit-val = <4>; 712 anatop-min-voltage = <800000>; 713 anatop-max-voltage = <1375000>; 714 anatop-enable-bit = <0>; 715 }; 716 717 reg_vdd3p0: regulator-3p0 { 718 compatible = "fsl,anatop-regulator"; 719 regulator-name = "vdd3p0"; 720 regulator-min-microvolt = <2800000>; 721 regulator-max-microvolt = <3150000>; 722 regulator-always-on; 723 anatop-reg-offset = <0x120>; 724 anatop-vol-bit-shift = <8>; 725 anatop-vol-bit-width = <5>; 726 anatop-min-bit-val = <0>; 727 anatop-min-voltage = <2625000>; 728 anatop-max-voltage = <3400000>; 729 anatop-enable-bit = <0>; 730 }; 731 732 reg_vdd2p5: regulator-2p5 { 733 compatible = "fsl,anatop-regulator"; 734 regulator-name = "vdd2p5"; 735 regulator-min-microvolt = <2250000>; 736 regulator-max-microvolt = <2750000>; 737 regulator-always-on; 738 anatop-reg-offset = <0x130>; 739 anatop-vol-bit-shift = <8>; 740 anatop-vol-bit-width = <5>; 741 anatop-min-bit-val = <0>; 742 anatop-min-voltage = <2100000>; 743 anatop-max-voltage = <2875000>; 744 anatop-enable-bit = <0>; 745 }; 746 747 reg_arm: regulator-vddcore { 748 compatible = "fsl,anatop-regulator"; 749 regulator-name = "vddarm"; 750 regulator-min-microvolt = <725000>; 751 regulator-max-microvolt = <1450000>; 752 regulator-always-on; 753 anatop-reg-offset = <0x140>; 754 anatop-vol-bit-shift = <0>; 755 anatop-vol-bit-width = <5>; 756 anatop-delay-reg-offset = <0x170>; 757 anatop-delay-bit-shift = <24>; 758 anatop-delay-bit-width = <2>; 759 anatop-min-bit-val = <1>; 760 anatop-min-voltage = <725000>; 761 anatop-max-voltage = <1450000>; 762 }; 763 764 reg_pu: regulator-vddpu { 765 compatible = "fsl,anatop-regulator"; 766 regulator-name = "vddpu"; 767 regulator-min-microvolt = <725000>; 768 regulator-max-microvolt = <1450000>; 769 regulator-enable-ramp-delay = <150>; 770 anatop-reg-offset = <0x140>; 771 anatop-vol-bit-shift = <9>; 772 anatop-vol-bit-width = <5>; 773 anatop-delay-reg-offset = <0x170>; 774 anatop-delay-bit-shift = <26>; 775 anatop-delay-bit-width = <2>; 776 anatop-min-bit-val = <1>; 777 anatop-min-voltage = <725000>; 778 anatop-max-voltage = <1450000>; 779 }; 780 781 reg_soc: regulator-vddsoc { 782 compatible = "fsl,anatop-regulator"; 783 regulator-name = "vddsoc"; 784 regulator-min-microvolt = <725000>; 785 regulator-max-microvolt = <1450000>; 786 regulator-always-on; 787 anatop-reg-offset = <0x140>; 788 anatop-vol-bit-shift = <18>; 789 anatop-vol-bit-width = <5>; 790 anatop-delay-reg-offset = <0x170>; 791 anatop-delay-bit-shift = <28>; 792 anatop-delay-bit-width = <2>; 793 anatop-min-bit-val = <1>; 794 anatop-min-voltage = <725000>; 795 anatop-max-voltage = <1450000>; 796 }; 797 }; 798 799 usbphy1: usbphy@20c9000 { 800 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 801 reg = <0x020c9000 0x1000>; 802 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 803 clocks = <&clks IMX6QDL_CLK_USBPHY1>; 804 fsl,anatop = <&anatop>; 805 }; 806 807 usbphy2: usbphy@20ca000 { 808 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; 809 reg = <0x020ca000 0x1000>; 810 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 811 clocks = <&clks IMX6QDL_CLK_USBPHY2>; 812 fsl,anatop = <&anatop>; 813 }; 814 815 snvs: snvs@20cc000 { 816 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 817 reg = <0x020cc000 0x4000>; 818 819 snvs_rtc: snvs-rtc-lp { 820 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 821 regmap = <&snvs>; 822 offset = <0x34>; 823 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 824 <0 20 IRQ_TYPE_LEVEL_HIGH>; 825 }; 826 827 snvs_poweroff: snvs-poweroff { 828 compatible = "syscon-poweroff"; 829 regmap = <&snvs>; 830 offset = <0x38>; 831 value = <0x60>; 832 mask = <0x60>; 833 status = "disabled"; 834 }; 835 836 snvs_pwrkey: snvs-powerkey { 837 compatible = "fsl,sec-v4.0-pwrkey"; 838 regmap = <&snvs>; 839 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 840 linux,keycode = <KEY_POWER>; 841 wakeup-source; 842 status = "disabled"; 843 }; 844 845 snvs_lpgpr: snvs-lpgpr { 846 compatible = "fsl,imx6q-snvs-lpgpr"; 847 }; 848 }; 849 850 epit1: epit@20d0000 { /* EPIT1 */ 851 reg = <0x020d0000 0x4000>; 852 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 853 }; 854 855 epit2: epit@20d4000 { /* EPIT2 */ 856 reg = <0x020d4000 0x4000>; 857 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 858 }; 859 860 src: src@20d8000 { 861 compatible = "fsl,imx6q-src", "fsl,imx51-src"; 862 reg = <0x020d8000 0x4000>; 863 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 864 <0 96 IRQ_TYPE_LEVEL_HIGH>; 865 #reset-cells = <1>; 866 }; 867 868 gpc: gpc@20dc000 { 869 compatible = "fsl,imx6q-gpc"; 870 reg = <0x020dc000 0x4000>; 871 interrupt-controller; 872 #interrupt-cells = <3>; 873 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>, 874 <0 90 IRQ_TYPE_LEVEL_HIGH>; 875 interrupt-parent = <&intc>; 876 clocks = <&clks IMX6QDL_CLK_IPG>; 877 clock-names = "ipg"; 878 879 pgc { 880 #address-cells = <1>; 881 #size-cells = <0>; 882 883 power-domain@0 { 884 reg = <0>; 885 #power-domain-cells = <0>; 886 }; 887 pd_pu: power-domain@1 { 888 reg = <1>; 889 #power-domain-cells = <0>; 890 power-supply = <®_pu>; 891 clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>, 892 <&clks IMX6QDL_CLK_GPU3D_SHADER>, 893 <&clks IMX6QDL_CLK_GPU2D_CORE>, 894 <&clks IMX6QDL_CLK_GPU2D_AXI>, 895 <&clks IMX6QDL_CLK_OPENVG_AXI>, 896 <&clks IMX6QDL_CLK_VPU_AXI>; 897 }; 898 }; 899 }; 900 901 gpr: iomuxc-gpr@20e0000 { 902 compatible = "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd"; 903 reg = <0x20e0000 0x38>; 904 905 mux: mux-controller { 906 compatible = "mmio-mux"; 907 #mux-control-cells = <1>; 908 }; 909 }; 910 911 iomuxc: iomuxc@20e0000 { 912 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc"; 913 reg = <0x20e0000 0x4000>; 914 }; 915 916 dcic1: dcic@20e4000 { 917 reg = <0x020e4000 0x4000>; 918 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>; 919 }; 920 921 dcic2: dcic@20e8000 { 922 reg = <0x020e8000 0x4000>; 923 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>; 924 }; 925 926 sdma: sdma@20ec000 { 927 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; 928 reg = <0x020ec000 0x4000>; 929 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 930 clocks = <&clks IMX6QDL_CLK_IPG>, 931 <&clks IMX6QDL_CLK_SDMA>; 932 clock-names = "ipg", "ahb"; 933 #dma-cells = <3>; 934 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 935 }; 936 }; 937 938 aips-bus@2100000 { /* AIPS2 */ 939 compatible = "fsl,aips-bus", "simple-bus"; 940 #address-cells = <1>; 941 #size-cells = <1>; 942 reg = <0x02100000 0x100000>; 943 ranges; 944 945 crypto: caam@2100000 { 946 compatible = "fsl,sec-v4.0"; 947 #address-cells = <1>; 948 #size-cells = <1>; 949 reg = <0x2100000 0x10000>; 950 ranges = <0 0x2100000 0x10000>; 951 clocks = <&clks IMX6QDL_CLK_CAAM_MEM>, 952 <&clks IMX6QDL_CLK_CAAM_ACLK>, 953 <&clks IMX6QDL_CLK_CAAM_IPG>, 954 <&clks IMX6QDL_CLK_EIM_SLOW>; 955 clock-names = "mem", "aclk", "ipg", "emi_slow"; 956 957 sec_jr0: jr0@1000 { 958 compatible = "fsl,sec-v4.0-job-ring"; 959 reg = <0x1000 0x1000>; 960 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 961 }; 962 963 sec_jr1: jr1@2000 { 964 compatible = "fsl,sec-v4.0-job-ring"; 965 reg = <0x2000 0x1000>; 966 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 967 }; 968 }; 969 970 aipstz@217c000 { /* AIPSTZ2 */ 971 reg = <0x0217c000 0x4000>; 972 }; 973 974 usbotg: usb@2184000 { 975 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 976 reg = <0x02184000 0x200>; 977 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 978 clocks = <&clks IMX6QDL_CLK_USBOH3>; 979 fsl,usbphy = <&usbphy1>; 980 fsl,usbmisc = <&usbmisc 0>; 981 ahb-burst-config = <0x0>; 982 tx-burst-size-dword = <0x10>; 983 rx-burst-size-dword = <0x10>; 984 status = "disabled"; 985 }; 986 987 usbh1: usb@2184200 { 988 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 989 reg = <0x02184200 0x200>; 990 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&clks IMX6QDL_CLK_USBOH3>; 992 fsl,usbphy = <&usbphy2>; 993 fsl,usbmisc = <&usbmisc 1>; 994 dr_mode = "host"; 995 ahb-burst-config = <0x0>; 996 tx-burst-size-dword = <0x10>; 997 rx-burst-size-dword = <0x10>; 998 status = "disabled"; 999 }; 1000 1001 usbh2: usb@2184400 { 1002 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1003 reg = <0x02184400 0x200>; 1004 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1006 fsl,usbphy = <&usbphynop1>; 1007 phy_type = "hsic"; 1008 fsl,usbmisc = <&usbmisc 2>; 1009 dr_mode = "host"; 1010 ahb-burst-config = <0x0>; 1011 tx-burst-size-dword = <0x10>; 1012 rx-burst-size-dword = <0x10>; 1013 status = "disabled"; 1014 }; 1015 1016 usbh3: usb@2184600 { 1017 compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; 1018 reg = <0x02184600 0x200>; 1019 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 1020 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1021 fsl,usbphy = <&usbphynop2>; 1022 phy_type = "hsic"; 1023 fsl,usbmisc = <&usbmisc 3>; 1024 dr_mode = "host"; 1025 ahb-burst-config = <0x0>; 1026 tx-burst-size-dword = <0x10>; 1027 rx-burst-size-dword = <0x10>; 1028 status = "disabled"; 1029 }; 1030 1031 usbmisc: usbmisc@2184800 { 1032 #index-cells = <1>; 1033 compatible = "fsl,imx6q-usbmisc"; 1034 reg = <0x02184800 0x200>; 1035 clocks = <&clks IMX6QDL_CLK_USBOH3>; 1036 }; 1037 1038 fec: ethernet@2188000 { 1039 compatible = "fsl,imx6q-fec"; 1040 reg = <0x02188000 0x4000>; 1041 interrupt-names = "int0", "pps"; 1042 interrupts-extended = 1043 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>, 1044 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 1045 clocks = <&clks IMX6QDL_CLK_ENET>, 1046 <&clks IMX6QDL_CLK_ENET>, 1047 <&clks IMX6QDL_CLK_ENET_REF>; 1048 clock-names = "ipg", "ahb", "ptp"; 1049 status = "disabled"; 1050 }; 1051 1052 mlb@218c000 { 1053 reg = <0x0218c000 0x4000>; 1054 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>, 1055 <0 117 IRQ_TYPE_LEVEL_HIGH>, 1056 <0 126 IRQ_TYPE_LEVEL_HIGH>; 1057 }; 1058 1059 usdhc1: usdhc@2190000 { 1060 compatible = "fsl,imx6q-usdhc"; 1061 reg = <0x02190000 0x4000>; 1062 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&clks IMX6QDL_CLK_USDHC1>, 1064 <&clks IMX6QDL_CLK_USDHC1>, 1065 <&clks IMX6QDL_CLK_USDHC1>; 1066 clock-names = "ipg", "ahb", "per"; 1067 bus-width = <4>; 1068 status = "disabled"; 1069 }; 1070 1071 usdhc2: usdhc@2194000 { 1072 compatible = "fsl,imx6q-usdhc"; 1073 reg = <0x02194000 0x4000>; 1074 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 1075 clocks = <&clks IMX6QDL_CLK_USDHC2>, 1076 <&clks IMX6QDL_CLK_USDHC2>, 1077 <&clks IMX6QDL_CLK_USDHC2>; 1078 clock-names = "ipg", "ahb", "per"; 1079 bus-width = <4>; 1080 status = "disabled"; 1081 }; 1082 1083 usdhc3: usdhc@2198000 { 1084 compatible = "fsl,imx6q-usdhc"; 1085 reg = <0x02198000 0x4000>; 1086 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 1087 clocks = <&clks IMX6QDL_CLK_USDHC3>, 1088 <&clks IMX6QDL_CLK_USDHC3>, 1089 <&clks IMX6QDL_CLK_USDHC3>; 1090 clock-names = "ipg", "ahb", "per"; 1091 bus-width = <4>; 1092 status = "disabled"; 1093 }; 1094 1095 usdhc4: usdhc@219c000 { 1096 compatible = "fsl,imx6q-usdhc"; 1097 reg = <0x0219c000 0x4000>; 1098 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&clks IMX6QDL_CLK_USDHC4>, 1100 <&clks IMX6QDL_CLK_USDHC4>, 1101 <&clks IMX6QDL_CLK_USDHC4>; 1102 clock-names = "ipg", "ahb", "per"; 1103 bus-width = <4>; 1104 status = "disabled"; 1105 }; 1106 1107 i2c1: i2c@21a0000 { 1108 #address-cells = <1>; 1109 #size-cells = <0>; 1110 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1111 reg = <0x021a0000 0x4000>; 1112 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&clks IMX6QDL_CLK_I2C1>; 1114 status = "disabled"; 1115 }; 1116 1117 i2c2: i2c@21a4000 { 1118 #address-cells = <1>; 1119 #size-cells = <0>; 1120 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1121 reg = <0x021a4000 0x4000>; 1122 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&clks IMX6QDL_CLK_I2C2>; 1124 status = "disabled"; 1125 }; 1126 1127 i2c3: i2c@21a8000 { 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; 1131 reg = <0x021a8000 0x4000>; 1132 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&clks IMX6QDL_CLK_I2C3>; 1134 status = "disabled"; 1135 }; 1136 1137 romcp@21ac000 { 1138 reg = <0x021ac000 0x4000>; 1139 }; 1140 1141 mmdc0: memory-controller@21b0000 { /* MMDC0 */ 1142 compatible = "fsl,imx6q-mmdc"; 1143 reg = <0x021b0000 0x4000>; 1144 clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; 1145 }; 1146 1147 mmdc1: memory-controller@21b4000 { /* MMDC1 */ 1148 compatible = "fsl,imx6q-mmdc"; 1149 reg = <0x021b4000 0x4000>; 1150 status = "disabled"; 1151 }; 1152 1153 weim: weim@21b8000 { 1154 #address-cells = <2>; 1155 #size-cells = <1>; 1156 compatible = "fsl,imx6q-weim"; 1157 reg = <0x021b8000 0x4000>; 1158 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 1159 clocks = <&clks IMX6QDL_CLK_EIM_SLOW>; 1160 fsl,weim-cs-gpr = <&gpr>; 1161 status = "disabled"; 1162 }; 1163 1164 ocotp: ocotp@21bc000 { 1165 compatible = "fsl,imx6q-ocotp", "syscon"; 1166 reg = <0x021bc000 0x4000>; 1167 clocks = <&clks IMX6QDL_CLK_IIM>; 1168 }; 1169 1170 tzasc@21d0000 { /* TZASC1 */ 1171 reg = <0x021d0000 0x4000>; 1172 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; 1173 }; 1174 1175 tzasc@21d4000 { /* TZASC2 */ 1176 reg = <0x021d4000 0x4000>; 1177 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; 1178 }; 1179 1180 audmux: audmux@21d8000 { 1181 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; 1182 reg = <0x021d8000 0x4000>; 1183 status = "disabled"; 1184 }; 1185 1186 mipi_csi: mipi@21dc000 { 1187 compatible = "fsl,imx6-mipi-csi2"; 1188 reg = <0x021dc000 0x4000>; 1189 #address-cells = <1>; 1190 #size-cells = <0>; 1191 interrupts = <0 100 0x04>, <0 101 0x04>; 1192 clocks = <&clks IMX6QDL_CLK_HSI_TX>, 1193 <&clks IMX6QDL_CLK_VIDEO_27M>, 1194 <&clks IMX6QDL_CLK_EIM_PODF>; 1195 clock-names = "dphy", "ref", "pix"; 1196 status = "disabled"; 1197 }; 1198 1199 mipi_dsi: mipi@21e0000 { 1200 reg = <0x021e0000 0x4000>; 1201 status = "disabled"; 1202 1203 ports { 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 1207 port@0 { 1208 reg = <0>; 1209 1210 mipi_mux_0: endpoint { 1211 remote-endpoint = <&ipu1_di0_mipi>; 1212 }; 1213 }; 1214 1215 port@1 { 1216 reg = <1>; 1217 1218 mipi_mux_1: endpoint { 1219 remote-endpoint = <&ipu1_di1_mipi>; 1220 }; 1221 }; 1222 }; 1223 }; 1224 1225 vdoa@21e4000 { 1226 compatible = "fsl,imx6q-vdoa"; 1227 reg = <0x021e4000 0x4000>; 1228 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; 1229 clocks = <&clks IMX6QDL_CLK_VDOA>; 1230 }; 1231 1232 uart2: serial@21e8000 { 1233 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1234 reg = <0x021e8000 0x4000>; 1235 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1237 <&clks IMX6QDL_CLK_UART_SERIAL>; 1238 clock-names = "ipg", "per"; 1239 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 1240 dma-names = "rx", "tx"; 1241 status = "disabled"; 1242 }; 1243 1244 uart3: serial@21ec000 { 1245 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1246 reg = <0x021ec000 0x4000>; 1247 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 1248 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1249 <&clks IMX6QDL_CLK_UART_SERIAL>; 1250 clock-names = "ipg", "per"; 1251 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 1252 dma-names = "rx", "tx"; 1253 status = "disabled"; 1254 }; 1255 1256 uart4: serial@21f0000 { 1257 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1258 reg = <0x021f0000 0x4000>; 1259 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1261 <&clks IMX6QDL_CLK_UART_SERIAL>; 1262 clock-names = "ipg", "per"; 1263 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 1264 dma-names = "rx", "tx"; 1265 status = "disabled"; 1266 }; 1267 1268 uart5: serial@21f4000 { 1269 compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; 1270 reg = <0x021f4000 0x4000>; 1271 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 1272 clocks = <&clks IMX6QDL_CLK_UART_IPG>, 1273 <&clks IMX6QDL_CLK_UART_SERIAL>; 1274 clock-names = "ipg", "per"; 1275 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 1276 dma-names = "rx", "tx"; 1277 status = "disabled"; 1278 }; 1279 }; 1280 1281 ipu1: ipu@2400000 { 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 compatible = "fsl,imx6q-ipu"; 1285 reg = <0x02400000 0x400000>; 1286 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>, 1287 <0 5 IRQ_TYPE_LEVEL_HIGH>; 1288 clocks = <&clks IMX6QDL_CLK_IPU1>, 1289 <&clks IMX6QDL_CLK_IPU1_DI0>, 1290 <&clks IMX6QDL_CLK_IPU1_DI1>; 1291 clock-names = "bus", "di0", "di1"; 1292 resets = <&src 2>; 1293 1294 ipu1_csi0: port@0 { 1295 reg = <0>; 1296 1297 ipu1_csi0_from_ipu1_csi0_mux: endpoint { 1298 remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>; 1299 }; 1300 }; 1301 1302 ipu1_csi1: port@1 { 1303 reg = <1>; 1304 }; 1305 1306 ipu1_di0: port@2 { 1307 #address-cells = <1>; 1308 #size-cells = <0>; 1309 reg = <2>; 1310 1311 ipu1_di0_disp0: endpoint@0 { 1312 reg = <0>; 1313 }; 1314 1315 ipu1_di0_hdmi: endpoint@1 { 1316 reg = <1>; 1317 remote-endpoint = <&hdmi_mux_0>; 1318 }; 1319 1320 ipu1_di0_mipi: endpoint@2 { 1321 reg = <2>; 1322 remote-endpoint = <&mipi_mux_0>; 1323 }; 1324 1325 ipu1_di0_lvds0: endpoint@3 { 1326 reg = <3>; 1327 remote-endpoint = <&lvds0_mux_0>; 1328 }; 1329 1330 ipu1_di0_lvds1: endpoint@4 { 1331 reg = <4>; 1332 remote-endpoint = <&lvds1_mux_0>; 1333 }; 1334 }; 1335 1336 ipu1_di1: port@3 { 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 reg = <3>; 1340 1341 ipu1_di1_disp1: endpoint@0 { 1342 reg = <0>; 1343 }; 1344 1345 ipu1_di1_hdmi: endpoint@1 { 1346 reg = <1>; 1347 remote-endpoint = <&hdmi_mux_1>; 1348 }; 1349 1350 ipu1_di1_mipi: endpoint@2 { 1351 reg = <2>; 1352 remote-endpoint = <&mipi_mux_1>; 1353 }; 1354 1355 ipu1_di1_lvds0: endpoint@3 { 1356 reg = <3>; 1357 remote-endpoint = <&lvds0_mux_1>; 1358 }; 1359 1360 ipu1_di1_lvds1: endpoint@4 { 1361 reg = <4>; 1362 remote-endpoint = <&lvds1_mux_1>; 1363 }; 1364 }; 1365 }; 1366 }; 1367}; 1368
