1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright 2013 Freescale Semiconductor, Inc. 4 * 5 * Author: Fabio Estevam <fabio.estevam@freescale.com> 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9 10/ { 11 chosen { 12 stdout-path = &uart1; 13 }; 14 15 sound { 16 compatible = "fsl,imx6-wandboard-sgtl5000", 17 "fsl,imx-audio-sgtl5000"; 18 model = "imx6-wandboard-sgtl5000"; 19 ssi-controller = <&ssi1>; 20 audio-codec = <&codec>; 21 audio-routing = 22 "MIC_IN", "Mic Jack", 23 "Mic Jack", "Mic Bias", 24 "Headphone Jack", "HP_OUT"; 25 mux-int-port = <1>; 26 mux-ext-port = <3>; 27 }; 28 29 sound-spdif { 30 compatible = "fsl,imx-audio-spdif"; 31 model = "imx-spdif"; 32 spdif-controller = <&spdif>; 33 spdif-out; 34 }; 35 36 reg_1p5v: regulator-1p5v { 37 compatible = "regulator-fixed"; 38 regulator-name = "1P5V"; 39 regulator-min-microvolt = <1500000>; 40 regulator-max-microvolt = <1500000>; 41 regulator-always-on; 42 }; 43 44 reg_1p8v: regulator-1p8v { 45 compatible = "regulator-fixed"; 46 regulator-name = "1P8V"; 47 regulator-min-microvolt = <1800000>; 48 regulator-max-microvolt = <1800000>; 49 regulator-always-on; 50 }; 51 52 reg_2p8v: regulator-2p8v { 53 compatible = "regulator-fixed"; 54 regulator-name = "2P8V"; 55 regulator-min-microvolt = <2800000>; 56 regulator-max-microvolt = <2800000>; 57 regulator-always-on; 58 }; 59 60 reg_2p5v: regulator-2p5v { 61 compatible = "regulator-fixed"; 62 regulator-name = "2P5V"; 63 regulator-min-microvolt = <2500000>; 64 regulator-max-microvolt = <2500000>; 65 regulator-always-on; 66 }; 67 68 reg_3p3v: regulator-3p3v { 69 compatible = "regulator-fixed"; 70 regulator-name = "3P3V"; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 regulator-always-on; 74 }; 75 76 reg_usb_otg_vbus: regulator-usbotgvbus { 77 compatible = "regulator-fixed"; 78 regulator-name = "usb_otg_vbus"; 79 regulator-min-microvolt = <5000000>; 80 regulator-max-microvolt = <5000000>; 81 pinctrl-names = "default"; 82 pinctrl-0 = <&pinctrl_usbotgvbus>; 83 gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; 84 }; 85}; 86 87&audmux { 88 pinctrl-names = "default"; 89 pinctrl-0 = <&pinctrl_audmux>; 90 status = "okay"; 91}; 92 93&hdmi { 94 ddc-i2c-bus = <&i2c1>; 95 status = "okay"; 96}; 97 98&i2c1 { 99 clock-frequency = <100000>; 100 pinctrl-names = "default"; 101 pinctrl-0 = <&pinctrl_i2c1>; 102 status = "okay"; 103}; 104 105&i2c2 { 106 clock-frequency = <100000>; 107 pinctrl-names = "default"; 108 pinctrl-0 = <&pinctrl_i2c2>; 109 status = "okay"; 110 111 codec: sgtl5000@a { 112 pinctrl-names = "default"; 113 pinctrl-0 = <&pinctrl_mclk>; 114 compatible = "fsl,sgtl5000"; 115 reg = <0x0a>; 116 clocks = <&clks IMX6QDL_CLK_CKO>; 117 VDDA-supply = <®_2p5v>; 118 VDDIO-supply = <®_3p3v>; 119 lrclk-strength = <3>; 120 }; 121 122 camera@3c { 123 compatible = "ovti,ov5645"; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_ov5645>; 126 reg = <0x3c>; 127 clocks = <&clks IMX6QDL_CLK_CKO2>; 128 clock-names = "xclk"; 129 clock-frequency = <24000000>; 130 vdddo-supply = <®_1p8v>; 131 vdda-supply = <®_2p8v>; 132 vddd-supply = <®_1p5v>; 133 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; 134 reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; 135 136 port { 137 ov5645_to_mipi_csi2: endpoint { 138 remote-endpoint = <&mipi_csi2_in>; 139 clock-lanes = <0>; 140 data-lanes = <1 2>; 141 }; 142 }; 143 }; 144}; 145 146&iomuxc { 147 pinctrl-names = "default"; 148 149 imx6qdl-wandboard { 150 151 pinctrl_audmux: audmuxgrp { 152 fsl,pins = < 153 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 154 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 155 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 156 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 157 >; 158 }; 159 160 pinctrl_enet: enetgrp { 161 fsl,pins = < 162 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 163 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 164 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 165 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 166 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 167 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 168 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 169 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 170 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 171 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 172 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 173 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 174 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 175 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 176 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 177 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 178 >; 179 }; 180 181 pinctrl_i2c1: i2c1grp { 182 fsl,pins = < 183 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 184 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 185 >; 186 }; 187 188 pinctrl_i2c2: i2c2grp { 189 fsl,pins = < 190 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 191 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 192 >; 193 }; 194 195 pinctrl_mclk: mclkgrp { 196 fsl,pins = < 197 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 198 >; 199 }; 200 201 pinctrl_ov5645: ov5645grp { 202 fsl,pins = < 203 MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0 204 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0 205 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 206 >; 207 }; 208 209 pinctrl_spdif: spdifgrp { 210 fsl,pins = < 211 MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0 212 >; 213 }; 214 215 pinctrl_uart1: uart1grp { 216 fsl,pins = < 217 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 218 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 219 >; 220 }; 221 222 pinctrl_uart3: uart3grp { 223 fsl,pins = < 224 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 225 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 226 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 227 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 228 >; 229 }; 230 231 pinctrl_usbotg: usbotggrp { 232 fsl,pins = < 233 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 234 >; 235 }; 236 237 pinctrl_usbotgvbus: usbotgvbusgrp { 238 fsl,pins = < 239 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x130b0 240 >; 241 }; 242 243 pinctrl_usdhc1: usdhc1grp { 244 fsl,pins = < 245 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 246 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 247 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 248 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 249 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 250 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 251 >; 252 }; 253 254 pinctrl_usdhc2: usdhc2grp { 255 fsl,pins = < 256 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 257 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 258 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 259 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 260 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 261 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 262 >; 263 }; 264 265 pinctrl_usdhc3: usdhc3grp { 266 fsl,pins = < 267 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 268 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 269 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 270 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 271 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 272 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 273 >; 274 }; 275 }; 276}; 277 278&fec { 279 pinctrl-names = "default"; 280 pinctrl-0 = <&pinctrl_enet>; 281 phy-mode = "rgmii-id"; 282 phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; 283 status = "okay"; 284}; 285 286&mipi_csi { 287 status = "okay"; 288 289 port@0 { 290 reg = <0>; 291 292 mipi_csi2_in: endpoint { 293 remote-endpoint = <&ov5645_to_mipi_csi2>; 294 clock-lanes = <0>; 295 data-lanes = <1 2>; 296 }; 297 }; 298}; 299 300&spdif { 301 pinctrl-names = "default"; 302 pinctrl-0 = <&pinctrl_spdif>; 303 status = "okay"; 304}; 305 306&ssi1 { 307 status = "okay"; 308}; 309 310&uart1 { 311 pinctrl-names = "default"; 312 pinctrl-0 = <&pinctrl_uart1>; 313 status = "okay"; 314}; 315 316&uart3 { 317 pinctrl-names = "default"; 318 pinctrl-0 = <&pinctrl_uart3>; 319 uart-has-rtscts; 320 status = "okay"; 321}; 322 323&usbh1 { 324 status = "okay"; 325}; 326 327&usbotg { 328 vbus-supply = <®_usb_otg_vbus>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&pinctrl_usbotg>; 331 disable-over-current; 332 dr_mode = "otg"; 333 status = "okay"; 334}; 335 336&usdhc1 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&pinctrl_usdhc1>; 339 cd-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; 340 status = "okay"; 341}; 342 343&usdhc3 { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_usdhc3>; 346 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; 347 status = "okay"; 348}; 349
