1// SPDX-License-Identifier: GPL-2.0 OR X11 2/* 3 * Copyright 2015 Boundary Devices, Inc. 4 */ 5#include <dt-bindings/gpio/gpio.h> 6#include <dt-bindings/input/input.h> 7 8/ { 9 chosen { 10 stdout-path = &uart2; 11 }; 12 13 memory@10000000 { 14 device_type = "memory"; 15 reg = <0x10000000 0xF0000000>; 16 }; 17 18 regulators { 19 compatible = "simple-bus"; 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 reg_1p8v: regulator@0 { 24 compatible = "regulator-fixed"; 25 reg = <0>; 26 regulator-name = "1P8V"; 27 regulator-min-microvolt = <1800000>; 28 regulator-max-microvolt = <1800000>; 29 regulator-always-on; 30 }; 31 32 reg_2p5v: regulator@1 { 33 compatible = "regulator-fixed"; 34 reg = <1>; 35 regulator-name = "2P5V"; 36 regulator-min-microvolt = <2500000>; 37 regulator-max-microvolt = <2500000>; 38 regulator-always-on; 39 }; 40 41 reg_3p3v: regulator@2 { 42 compatible = "regulator-fixed"; 43 reg = <2>; 44 regulator-name = "3P3V"; 45 regulator-min-microvolt = <3300000>; 46 regulator-max-microvolt = <3300000>; 47 regulator-always-on; 48 }; 49 50 reg_usb_otg_vbus: regulator@3 { 51 compatible = "regulator-fixed"; 52 reg = <3>; 53 regulator-name = "usb_otg_vbus"; 54 regulator-min-microvolt = <5000000>; 55 regulator-max-microvolt = <5000000>; 56 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 57 enable-active-high; 58 }; 59 60 reg_usb_h1_vbus: regulator@4 { 61 compatible = "regulator-fixed"; 62 reg = <4>; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_usbh1>; 65 regulator-name = "usb_h1_vbus"; 66 regulator-min-microvolt = <3300000>; 67 regulator-max-microvolt = <3300000>; 68 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; 69 enable-active-high; 70 }; 71 72 reg_wlan_vmmc: regulator@5 { 73 compatible = "regulator-fixed"; 74 reg = <5>; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&pinctrl_wlan_vmmc>; 77 regulator-name = "reg_wlan_vmmc"; 78 regulator-min-microvolt = <3300000>; 79 regulator-max-microvolt = <3300000>; 80 gpio = <&gpio6 15 GPIO_ACTIVE_HIGH>; 81 startup-delay-us = <70000>; 82 enable-active-high; 83 }; 84 85 reg_can_xcvr: regulator@6 { 86 compatible = "regulator-fixed"; 87 reg = <6>; 88 regulator-name = "CAN XCVR"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_can_xcvr>; 93 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; 94 }; 95 }; 96 97 gpio-keys { 98 compatible = "gpio-keys"; 99 pinctrl-names = "default"; 100 pinctrl-0 = <&pinctrl_gpio_keys>; 101 102 power { 103 label = "Power Button"; 104 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; 105 linux,code = <KEY_POWER>; 106 wakeup-source; 107 }; 108 109 menu { 110 label = "Menu"; 111 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; 112 linux,code = <KEY_MENU>; 113 }; 114 115 home { 116 label = "Home"; 117 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 118 linux,code = <KEY_HOME>; 119 }; 120 121 back { 122 label = "Back"; 123 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; 124 linux,code = <KEY_BACK>; 125 }; 126 127 volume-up { 128 label = "Volume Up"; 129 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; 130 linux,code = <KEY_VOLUMEUP>; 131 }; 132 133 volume-down { 134 label = "Volume Down"; 135 gpios = <&gpio7 1 GPIO_ACTIVE_LOW>; 136 linux,code = <KEY_VOLUMEDOWN>; 137 }; 138 }; 139 140 i2c2mux { 141 compatible = "i2c-mux-gpio"; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_i2c2mux>; 144 #address-cells = <1>; 145 #size-cells = <0>; 146 mux-gpios = <&gpio3 20 GPIO_ACTIVE_HIGH 147 &gpio4 15 GPIO_ACTIVE_HIGH>; 148 i2c-parent = <&i2c2>; 149 idle-state = <0>; 150 151 i2c2mux@1 { 152 reg = <1>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 }; 156 157 i2c2mux@2 { 158 reg = <2>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 }; 162 }; 163 164 i2c3mux { 165 compatible = "i2c-mux-gpio"; 166 pinctrl-names = "default"; 167 pinctrl-0 = <&pinctrl_i2c3mux>; 168 #address-cells = <1>; 169 #size-cells = <0>; 170 mux-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>; 171 i2c-parent = <&i2c3>; 172 idle-state = <0>; 173 174 i2c3mux@1 { 175 reg = <1>; 176 #address-cells = <1>; 177 #size-cells = <0>; 178 }; 179 }; 180 181 leds { 182 compatible = "gpio-leds"; 183 184 speaker-enable { 185 gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; 186 retain-state-suspended; 187 default-state = "off"; 188 }; 189 190 ttymxc4-rs232 { 191 gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; 192 retain-state-suspended; 193 default-state = "on"; 194 }; 195 }; 196 197 backlight_lcd: backlight-lcd { 198 compatible = "pwm-backlight"; 199 pwms = <&pwm1 0 5000000>; 200 brightness-levels = <0 4 8 16 32 64 128 255>; 201 default-brightness-level = <7>; 202 power-supply = <®_3p3v>; 203 status = "okay"; 204 }; 205 206 backlight_lvds0: backlight-lvds0 { 207 compatible = "pwm-backlight"; 208 pwms = <&pwm4 0 5000000>; 209 brightness-levels = <0 4 8 16 32 64 128 255>; 210 default-brightness-level = <7>; 211 power-supply = <®_3p3v>; 212 status = "okay"; 213 }; 214 215 backlight_lvds1: backlight-lvds1 { 216 compatible = "pwm-backlight"; 217 pwms = <&pwm2 0 5000000>; 218 brightness-levels = <0 4 8 16 32 64 128 255>; 219 default-brightness-level = <7>; 220 power-supply = <®_3p3v>; 221 status = "okay"; 222 }; 223 224 lcd_display: disp0 { 225 compatible = "fsl,imx-parallel-display"; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 interface-pix-fmt = "bgr666"; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&pinctrl_j15>; 231 status = "okay"; 232 233 port@0 { 234 reg = <0>; 235 236 lcd_display_in: endpoint { 237 remote-endpoint = <&ipu1_di0_disp0>; 238 }; 239 }; 240 241 port@1 { 242 reg = <1>; 243 244 lcd_display_out: endpoint { 245 remote-endpoint = <&lcd_panel_in>; 246 }; 247 }; 248 }; 249 250 panel-lcd { 251 compatible = "okaya,rs800480t-7x0gp"; 252 backlight = <&backlight_lcd>; 253 254 port { 255 lcd_panel_in: endpoint { 256 remote-endpoint = <&lcd_display_out>; 257 }; 258 }; 259 }; 260 261 panel-lvds0 { 262 compatible = "hannstar,hsd100pxn1"; 263 backlight = <&backlight_lvds0>; 264 265 port { 266 panel_in_lvds0: endpoint { 267 remote-endpoint = <&lvds0_out>; 268 }; 269 }; 270 }; 271 272 panel-lvds1 { 273 compatible = "hannstar,hsd100pxn1"; 274 backlight = <&backlight_lvds1>; 275 276 port { 277 panel_in_lvds1: endpoint { 278 remote-endpoint = <&lvds1_out>; 279 }; 280 }; 281 }; 282 283 sound { 284 compatible = "fsl,imx6q-nitrogen6_max-sgtl5000", 285 "fsl,imx-audio-sgtl5000"; 286 model = "imx6q-nitrogen6_max-sgtl5000"; 287 ssi-controller = <&ssi1>; 288 audio-codec = <&codec>; 289 audio-routing = 290 "MIC_IN", "Mic Jack", 291 "Mic Jack", "Mic Bias", 292 "Headphone Jack", "HP_OUT"; 293 mux-int-port = <1>; 294 mux-ext-port = <3>; 295 }; 296}; 297 298&audmux { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_audmux>; 301 status = "okay"; 302}; 303 304&can1 { 305 pinctrl-names = "default"; 306 pinctrl-0 = <&pinctrl_can1>; 307 xceiver-supply = <®_can_xcvr>; 308 status = "okay"; 309}; 310 311&clks { 312 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 313 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 314 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 315 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 316}; 317 318&ecspi1 { 319 cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_ecspi1>; 322 status = "okay"; 323 324 flash: m25p80@0 { 325 compatible = "microchip,sst25vf016b"; 326 spi-max-frequency = <20000000>; 327 reg = <0>; 328 }; 329}; 330 331&fec { 332 pinctrl-names = "default"; 333 pinctrl-0 = <&pinctrl_enet>; 334 phy-mode = "rgmii"; 335 phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; 336 txen-skew-ps = <0>; 337 txc-skew-ps = <3000>; 338 rxdv-skew-ps = <0>; 339 rxc-skew-ps = <3000>; 340 rxd0-skew-ps = <0>; 341 rxd1-skew-ps = <0>; 342 rxd2-skew-ps = <0>; 343 rxd3-skew-ps = <0>; 344 txd0-skew-ps = <0>; 345 txd1-skew-ps = <0>; 346 txd2-skew-ps = <0>; 347 txd3-skew-ps = <0>; 348 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>, 349 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>; 350 fsl,err006687-workaround-present; 351 status = "okay"; 352}; 353 354&hdmi { 355 ddc-i2c-bus = <&i2c2>; 356 status = "okay"; 357}; 358 359&i2c1 { 360 clock-frequency = <100000>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_i2c1>; 363 status = "okay"; 364 365 codec: sgtl5000@a { 366 compatible = "fsl,sgtl5000"; 367 pinctrl-names = "default"; 368 pinctrl-0 = <&pinctrl_sgtl5000>; 369 reg = <0x0a>; 370 clocks = <&clks IMX6QDL_CLK_CKO>; 371 VDDA-supply = <®_2p5v>; 372 VDDIO-supply = <®_3p3v>; 373 }; 374 375 rtc: rtc@68 { 376 compatible = "microcrystal,rv4162"; 377 pinctrl-names = "default"; 378 pinctrl-0 = <&pinctrl_rv4162>; 379 reg = <0x68>; 380 interrupts-extended = <&gpio4 6 IRQ_TYPE_LEVEL_LOW>; 381 }; 382}; 383 384&i2c2 { 385 clock-frequency = <100000>; 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_i2c2>; 388 status = "okay"; 389}; 390 391&i2c3 { 392 clock-frequency = <100000>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_i2c3>; 395 status = "okay"; 396 397 touchscreen@4 { 398 compatible = "eeti,egalax_ts"; 399 reg = <0x04>; 400 interrupt-parent = <&gpio1>; 401 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 402 wakeup-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; 403 }; 404 405 touchscreen@38 { 406 compatible = "edt,edt-ft5x06"; 407 reg = <0x38>; 408 interrupt-parent = <&gpio1>; 409 interrupts = <9 IRQ_TYPE_EDGE_FALLING>; 410 wakeup-source; 411 }; 412}; 413 414&iomuxc { 415 imx6q-nitrogen6-max { 416 pinctrl_audmux: audmuxgrp { 417 fsl,pins = < 418 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 419 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0 420 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0 421 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0 422 >; 423 }; 424 425 pinctrl_can1: can1grp { 426 fsl,pins = < 427 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0 428 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0 429 >; 430 }; 431 432 pinctrl_can_xcvr: can-xcvrgrp { 433 fsl,pins = < 434 /* Flexcan XCVR enable */ 435 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0 436 >; 437 }; 438 439 pinctrl_ecspi1: ecspi1grp { 440 fsl,pins = < 441 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 442 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 443 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 444 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 445 >; 446 }; 447 448 pinctrl_enet: enetgrp { 449 fsl,pins = < 450 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0 451 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0 452 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030 453 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030 454 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030 455 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030 456 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030 457 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030 458 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0 459 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 460 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 461 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 462 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 463 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 464 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 465 /* Phy reset */ 466 MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x0f0b0 467 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 468 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 469 >; 470 }; 471 472 pinctrl_gpio_keys: gpio-keysgrp { 473 fsl,pins = < 474 /* Power Button */ 475 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 476 /* Menu Button */ 477 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 478 /* Home Button */ 479 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 480 /* Back Button */ 481 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 482 /* Volume Up Button */ 483 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 484 /* Volume Down Button */ 485 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0 486 >; 487 }; 488 489 pinctrl_i2c1: i2c1grp { 490 fsl,pins = < 491 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 492 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 493 >; 494 }; 495 496 pinctrl_i2c2: i2c2grp { 497 fsl,pins = < 498 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 499 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 500 >; 501 }; 502 503 pinctrl_i2c2mux: i2c2muxgrp { 504 fsl,pins = < 505 /* ov5642 camera i2c enable */ 506 MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x000b0 507 /* ov5640_mipi camera i2c enable */ 508 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x000b0 509 >; 510 }; 511 512 pinctrl_i2c3: i2c3grp { 513 fsl,pins = < 514 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 515 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1 516 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 517 >; 518 }; 519 520 pinctrl_i2c3mux: i2c3muxgrp { 521 fsl,pins = < 522 /* PCIe I2C enable */ 523 MX6QDL_PAD_EIM_OE__GPIO2_IO25 0x000b0 524 >; 525 }; 526 527 pinctrl_j15: j15grp { 528 fsl,pins = < 529 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 530 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 531 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 532 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 533 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 534 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 535 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 536 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 537 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 538 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 539 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 540 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 541 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 542 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 543 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 544 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 545 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 546 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 547 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 548 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 549 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 550 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 551 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 552 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 553 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 554 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 555 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 556 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 557 >; 558 }; 559 560 pinctrl_pcie: pciegrp { 561 fsl,pins = < 562 /* PCIe reset */ 563 MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x000b0 564 >; 565 }; 566 567 pinctrl_pwm1: pwm1grp { 568 fsl,pins = < 569 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1 570 >; 571 }; 572 573 pinctrl_pwm2: pwm2grp { 574 fsl,pins = < 575 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 576 >; 577 }; 578 579 pinctrl_pwm3: pwm3grp { 580 fsl,pins = < 581 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 582 >; 583 }; 584 585 pinctrl_pwm4: pwm4grp { 586 fsl,pins = < 587 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 588 >; 589 }; 590 591 pinctrl_rv4162: rv4162grp { 592 fsl,pins = < 593 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 594 >; 595 }; 596 597 pinctrl_sgtl5000: sgtl5000grp { 598 fsl,pins = < 599 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 600 MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x1b0b0 601 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 602 >; 603 }; 604 605 pinctrl_uart1: uart1grp { 606 fsl,pins = < 607 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 608 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 609 >; 610 }; 611 612 pinctrl_uart2: uart2grp { 613 fsl,pins = < 614 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 615 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 616 >; 617 }; 618 619 pinctrl_uart5: uart5grp { 620 fsl,pins = < 621 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x130b1 622 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x030b1 623 /* RS485 RX Enable: pull up */ 624 MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x1b0b1 625 /* RS485 DEN: pull down */ 626 MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x030b1 627 /* RS485/!RS232 Select: pull down (rs232) */ 628 MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x030b1 629 /* ON: pull down */ 630 MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x030b1 631 >; 632 }; 633 634 pinctrl_usbh1: usbh1grp { 635 fsl,pins = < 636 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x0b0b0 637 >; 638 }; 639 640 pinctrl_usbotg: usbotggrp { 641 fsl,pins = < 642 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 643 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 644 /* power enable, high active */ 645 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0 646 >; 647 }; 648 649 pinctrl_usdhc2: usdhc2grp { 650 fsl,pins = < 651 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 652 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 653 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 654 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 655 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 656 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 657 >; 658 }; 659 660 pinctrl_usdhc3: usdhc3grp { 661 fsl,pins = < 662 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 663 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 664 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 665 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 666 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 667 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 668 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x100b0 669 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 670 >; 671 }; 672 673 pinctrl_usdhc4: usdhc4grp { 674 fsl,pins = < 675 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059 676 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059 677 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059 678 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059 679 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059 680 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059 681 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059 682 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059 683 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059 684 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059 685 >; 686 }; 687 688 pinctrl_wlan_vmmc: wlan-vmmcgrp { 689 fsl,pins = < 690 MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x100b0 691 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x000b0 692 MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x000b0 693 MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT 0x000b0 694 >; 695 }; 696 }; 697}; 698 699&ipu1_di0_disp0 { 700 remote-endpoint = <&lcd_display_in>; 701}; 702 703&ldb { 704 status = "okay"; 705 706 lvds-channel@0 { 707 status = "okay"; 708 709 port@4 { 710 reg = <4>; 711 712 lvds0_out: endpoint { 713 remote-endpoint = <&panel_in_lvds0>; 714 }; 715 }; 716 }; 717 718 lvds-channel@1 { 719 status = "okay"; 720 721 port@4 { 722 reg = <4>; 723 724 lvds1_out: endpoint { 725 remote-endpoint = <&panel_in_lvds1>; 726 }; 727 }; 728 }; 729}; 730 731&pcie { 732 pinctrl-names = "default"; 733 pinctrl-0 = <&pinctrl_pcie>; 734 reset-gpio = <&gpio6 31 GPIO_ACTIVE_LOW>; 735 status = "okay"; 736}; 737 738&pwm1 { 739 pinctrl-names = "default"; 740 pinctrl-0 = <&pinctrl_pwm1>; 741 status = "okay"; 742}; 743 744&pwm2 { 745 pinctrl-names = "default"; 746 pinctrl-0 = <&pinctrl_pwm2>; 747 status = "okay"; 748}; 749 750&pwm3 { 751 pinctrl-names = "default"; 752 pinctrl-0 = <&pinctrl_pwm3>; 753 status = "okay"; 754}; 755 756&pwm4 { 757 pinctrl-names = "default"; 758 pinctrl-0 = <&pinctrl_pwm4>; 759 status = "okay"; 760}; 761 762&ssi1 { 763 status = "okay"; 764}; 765 766&uart1 { 767 pinctrl-names = "default"; 768 pinctrl-0 = <&pinctrl_uart1>; 769 status = "okay"; 770}; 771 772&uart2 { 773 pinctrl-names = "default"; 774 pinctrl-0 = <&pinctrl_uart2>; 775 status = "okay"; 776}; 777 778&uart5 { 779 pinctrl-names = "default"; 780 pinctrl-0 = <&pinctrl_uart5>; 781 status = "okay"; 782}; 783 784&usbh1 { 785 vbus-supply = <®_usb_h1_vbus>; 786 status = "okay"; 787}; 788 789&usbotg { 790 vbus-supply = <®_usb_otg_vbus>; 791 pinctrl-names = "default"; 792 pinctrl-0 = <&pinctrl_usbotg>; 793 disable-over-current; 794 status = "okay"; 795}; 796 797&usdhc2 { 798 pinctrl-names = "default"; 799 pinctrl-0 = <&pinctrl_usdhc2>; 800 bus-width = <4>; 801 non-removable; 802 vmmc-supply = <®_wlan_vmmc>; 803 cap-power-off-card; 804 keep-power-in-suspend; 805 status = "okay"; 806 807 #address-cells = <1>; 808 #size-cells = <0>; 809 wlcore: wlcore@2 { 810 compatible = "ti,wl1271"; 811 reg = <2>; 812 interrupt-parent = <&gpio6>; 813 interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; 814 ref-clock-frequency = <38400000>; 815 }; 816}; 817 818&usdhc3 { 819 pinctrl-names = "default"; 820 pinctrl-0 = <&pinctrl_usdhc3>; 821 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 822 bus-width = <4>; 823 vmmc-supply = <®_3p3v>; 824 status = "okay"; 825}; 826 827&usdhc4 { 828 pinctrl-names = "default"; 829 pinctrl-0 = <&pinctrl_usdhc4>; 830 bus-width = <8>; 831 non-removable; 832 vmmc-supply = <®_1p8v>; 833 keep-power-in-suspend; 834 status = "okay"; 835}; 836
