1/* 2 * Copyright 2016 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49 50/ { 51 /* these are used by bootloader for disabling nodes */ 52 aliases { 53 led0 = &led0; 54 led1 = &led1; 55 nand = &gpmi; 56 usb0 = &usbh1; 57 usb1 = &usbotg; 58 }; 59 60 chosen { 61 stdout-path = &uart2; 62 }; 63 64 leds { 65 compatible = "gpio-leds"; 66 pinctrl-names = "default"; 67 pinctrl-0 = <&pinctrl_gpio_leds>; 68 69 led0: user1 { 70 label = "user1"; 71 gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 72 default-state = "on"; 73 linux,default-trigger = "heartbeat"; 74 }; 75 76 led1: user2 { 77 label = "user2"; 78 gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 79 default-state = "off"; 80 }; 81 }; 82 83 memory@10000000 { 84 device_type = "memory"; 85 reg = <0x10000000 0x20000000>; 86 }; 87 88 pps { 89 compatible = "pps-gpio"; 90 pinctrl-names = "default"; 91 pinctrl-0 = <&pinctrl_pps>; 92 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 93 status = "okay"; 94 }; 95 96 reg_5p0v: regulator-5p0v { 97 compatible = "regulator-fixed"; 98 regulator-name = "5P0V"; 99 regulator-min-microvolt = <5000000>; 100 regulator-max-microvolt = <5000000>; 101 regulator-always-on; 102 }; 103 104 reg_usb_otg_vbus: regulator-usb-otg-vbus { 105 compatible = "regulator-fixed"; 106 regulator-name = "usb_otg_vbus"; 107 regulator-min-microvolt = <5000000>; 108 regulator-max-microvolt = <5000000>; 109 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 110 enable-active-high; 111 }; 112}; 113 114&gpmi { 115 pinctrl-names = "default"; 116 pinctrl-0 = <&pinctrl_gpmi_nand>; 117 status = "okay"; 118}; 119 120&hdmi { 121 pinctrl-names = "default"; 122 pinctrl-0 = <&pinctrl_hdmi>; 123 ddc-i2c-bus = <&i2c3>; 124 status = "okay"; 125}; 126 127&i2c1 { 128 clock-frequency = <100000>; 129 pinctrl-names = "default"; 130 pinctrl-0 = <&pinctrl_i2c1>; 131 status = "okay"; 132 133 gpio: pca9555@23 { 134 compatible = "nxp,pca9555"; 135 reg = <0x23>; 136 gpio-controller; 137 #gpio-cells = <2>; 138 }; 139 140 eeprom1: eeprom@50 { 141 compatible = "atmel,24c02"; 142 reg = <0x50>; 143 pagesize = <16>; 144 }; 145 146 eeprom2: eeprom@51 { 147 compatible = "atmel,24c02"; 148 reg = <0x51>; 149 pagesize = <16>; 150 }; 151 152 eeprom3: eeprom@52 { 153 compatible = "atmel,24c02"; 154 reg = <0x52>; 155 pagesize = <16>; 156 }; 157 158 eeprom4: eeprom@53 { 159 compatible = "atmel,24c02"; 160 reg = <0x53>; 161 pagesize = <16>; 162 }; 163 164 rtc: ds1672@68 { 165 compatible = "dallas,ds1672"; 166 reg = <0x68>; 167 }; 168}; 169 170&i2c2 { 171 clock-frequency = <100000>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&pinctrl_i2c2>; 174 status = "okay"; 175 176 ltc3676: pmic@3c { 177 compatible = "lltc,ltc3676"; 178 reg = <0x3c>; 179 pinctrl-names = "default"; 180 pinctrl-0 = <&pinctrl_pmic>; 181 interrupt-parent = <&gpio1>; 182 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 183 184 regulators { 185 /* VDD_SOC (1+R1/R2 = 1.635) */ 186 reg_vdd_soc: sw1 { 187 regulator-name = "vddsoc"; 188 regulator-min-microvolt = <674400>; 189 regulator-max-microvolt = <1308000>; 190 lltc,fb-voltage-divider = <127000 200000>; 191 regulator-ramp-delay = <7000>; 192 regulator-boot-on; 193 regulator-always-on; 194 }; 195 196 /* VDD_DDR (1+R1/R2 = 2.105) */ 197 reg_vdd_ddr: sw2 { 198 regulator-name = "vddddr"; 199 regulator-min-microvolt = <868310>; 200 regulator-max-microvolt = <1684000>; 201 lltc,fb-voltage-divider = <221000 200000>; 202 regulator-ramp-delay = <7000>; 203 regulator-boot-on; 204 regulator-always-on; 205 }; 206 207 /* VDD_ARM (1+R1/R2 = 1.635) */ 208 reg_vdd_arm: sw3 { 209 regulator-name = "vddarm"; 210 regulator-min-microvolt = <674400>; 211 regulator-max-microvolt = <1308000>; 212 lltc,fb-voltage-divider = <127000 200000>; 213 regulator-ramp-delay = <7000>; 214 regulator-boot-on; 215 regulator-always-on; 216 }; 217 218 /* VDD_3P3 (1+R1/R2 = 1.281) */ 219 reg_3p3v: sw4 { 220 regulator-name = "vdd3p3"; 221 regulator-min-microvolt = <1880000>; 222 regulator-max-microvolt = <3647000>; 223 lltc,fb-voltage-divider = <200000 56200>; 224 regulator-ramp-delay = <7000>; 225 regulator-boot-on; 226 regulator-always-on; 227 }; 228 229 /* VDD_1P8a (1+R1/R2 = 2.505): Analog Video Decoder */ 230 reg_1p8a: ldo2 { 231 regulator-name = "vdd1p8a"; 232 regulator-min-microvolt = <1816125>; 233 regulator-max-microvolt = <1816125>; 234 lltc,fb-voltage-divider = <301000 200000>; 235 regulator-boot-on; 236 regulator-always-on; 237 }; 238 239 /* VDD_1P8b: microSD VDD_1P8 */ 240 reg_1p8b: ldo3 { 241 regulator-name = "vdd1p8b"; 242 regulator-min-microvolt = <1800000>; 243 regulator-max-microvolt = <1800000>; 244 regulator-boot-on; 245 }; 246 247 /* VDD_HIGH (1+R1/R2 = 4.17) */ 248 reg_3p0v: ldo4 { 249 regulator-name = "vdd3p0"; 250 regulator-min-microvolt = <3023250>; 251 regulator-max-microvolt = <3023250>; 252 lltc,fb-voltage-divider = <634000 200000>; 253 regulator-boot-on; 254 regulator-always-on; 255 }; 256 }; 257 }; 258}; 259 260&i2c3 { 261 clock-frequency = <100000>; 262 pinctrl-names = "default"; 263 pinctrl-0 = <&pinctrl_i2c3>; 264 status = "okay"; 265 266 adv7180: camera@20 { 267 compatible = "adi,adv7180"; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&pinctrl_adv7180>; 270 reg = <0x20>; 271 powerdown-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; 272 interrupt-parent = <&gpio5>; 273 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 274 275 port { 276 adv7180_to_ipu1_csi0_mux: endpoint { 277 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; 278 bus-width = <8>; 279 }; 280 }; 281 }; 282}; 283 284&ipu1_csi0_from_ipu1_csi0_mux { 285 bus-width = <8>; 286}; 287 288&ipu1_csi0_mux_from_parallel_sensor { 289 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; 290 bus-width = <8>; 291}; 292 293&ipu1_csi0 { 294 pinctrl-names = "default"; 295 pinctrl-0 = <&pinctrl_ipu1_csi0>; 296}; 297 298&pcie { 299 pinctrl-names = "default"; 300 pinctrl-0 = <&pinctrl_pcie>; 301 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 302 status = "okay"; 303}; 304 305&pwm2 { 306 pinctrl-names = "default"; 307 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 308 status = "disabled"; 309}; 310 311&pwm3 { 312 pinctrl-names = "default"; 313 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 314 status = "disabled"; 315}; 316 317&pwm4 { 318 pinctrl-names = "default"; 319 pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ 320 status = "disabled"; 321}; 322 323&uart2 { 324 pinctrl-names = "default"; 325 pinctrl-0 = <&pinctrl_uart2>; 326 status = "okay"; 327}; 328 329&uart3 { 330 pinctrl-names = "default"; 331 pinctrl-0 = <&pinctrl_uart3>; 332 status = "okay"; 333}; 334 335&uart4 { 336 pinctrl-names = "default"; 337 pinctrl-0 = <&pinctrl_uart4>; 338 status = "okay"; 339}; 340 341&uart5 { 342 pinctrl-names = "default"; 343 pinctrl-0 = <&pinctrl_uart5>; 344 status = "okay"; 345}; 346 347&usbh1 { 348 status = "okay"; 349}; 350 351&usbotg { 352 vbus-supply = <®_usb_otg_vbus>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&pinctrl_usbotg>; 355 disable-over-current; 356 status = "okay"; 357}; 358 359&usdhc3 { 360 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 361 pinctrl-0 = <&pinctrl_usdhc3>; 362 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 363 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 364 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 365 status = "okay"; 366}; 367 368&wdog1 { 369 pinctrl-names = "default"; 370 pinctrl-0 = <&pinctrl_wdog>; 371 fsl,ext-reset-output; 372}; 373 374&iomuxc { 375 pinctrl_adv7180: adv7180grp { 376 fsl,pins = < 377 MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x0001b0b0 378 MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x4001b0b0 379 >; 380 }; 381 382 pinctrl_gpmi_nand: gpminandgrp { 383 fsl,pins = < 384 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 385 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 386 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 387 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 388 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 389 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 390 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 391 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 392 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 393 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 394 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 395 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 396 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 397 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 398 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 399 >; 400 }; 401 402 pinctrl_hdmi: hdmigrp { 403 fsl,pins = < 404 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0 405 >; 406 }; 407 408 pinctrl_i2c1: i2c1grp { 409 fsl,pins = < 410 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 411 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 412 >; 413 }; 414 415 pinctrl_i2c2: i2c2grp { 416 fsl,pins = < 417 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 418 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 419 >; 420 }; 421 422 pinctrl_i2c3: i2c3grp { 423 fsl,pins = < 424 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 425 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 426 >; 427 }; 428 429 pinctrl_ipu1_csi0: ipu1csi0grp { 430 fsl,pins = < 431 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 432 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 433 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 434 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 435 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 436 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 437 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 438 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 439 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 440 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 441 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 442 >; 443 }; 444 445 pinctrl_gpio_leds: gpioledsgrp { 446 fsl,pins = < 447 MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0 448 MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x1b0b0 449 >; 450 }; 451 452 pinctrl_pcie: pciegrp { 453 fsl,pins = < 454 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 455 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b0 /* PCIESKT_WDIS# */ 456 >; 457 }; 458 459 pinctrl_pmic: pmicgrp { 460 fsl,pins = < 461 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 462 >; 463 }; 464 465 pinctrl_pps: ppsgrp { 466 fsl,pins = < 467 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 468 >; 469 }; 470 471 pinctrl_pwm2: pwm2grp { 472 fsl,pins = < 473 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 474 >; 475 }; 476 477 pinctrl_pwm3: pwm3grp { 478 fsl,pins = < 479 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 480 >; 481 }; 482 483 pinctrl_pwm4: pwm4grp { 484 fsl,pins = < 485 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 486 >; 487 }; 488 489 pinctrl_uart2: uart2grp { 490 fsl,pins = < 491 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 492 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 493 >; 494 }; 495 496 pinctrl_uart3: uart3grp { 497 fsl,pins = < 498 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 499 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 500 >; 501 }; 502 503 pinctrl_uart4: uart4grp { 504 fsl,pins = < 505 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 506 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 507 >; 508 }; 509 510 pinctrl_uart5: uart5grp { 511 fsl,pins = < 512 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 513 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 514 >; 515 }; 516 517 pinctrl_usbotg: usbotggrp { 518 fsl,pins = < 519 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 520 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 521 >; 522 }; 523 524 pinctrl_usdhc3: usdhc3grp { 525 fsl,pins = < 526 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 527 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 528 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 529 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 530 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 531 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 532 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 533 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 534 >; 535 }; 536 537 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 538 fsl,pins = < 539 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 540 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 541 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 542 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 543 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 544 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 545 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 546 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 547 >; 548 }; 549 550 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 551 fsl,pins = < 552 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 553 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 554 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 555 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 556 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 557 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 558 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 559 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 560 >; 561 }; 562 563 pinctrl_wdog: wdoggrp { 564 fsl,pins = < 565 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 566 >; 567 }; 568}; 569
