1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright 2013 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7 8/ { 9 /* these are used by bootloader for disabling nodes */ 10 aliases { 11 led0 = &led0; 12 led1 = &led1; 13 led2 = &led2; 14 nand = &gpmi; 15 ssi0 = &ssi1; 16 usb0 = &usbh1; 17 usb1 = &usbotg; 18 }; 19 20 chosen { 21 bootargs = "console=ttymxc1,115200"; 22 }; 23 24 backlight { 25 compatible = "pwm-backlight"; 26 pwms = <&pwm4 0 5000000>; 27 brightness-levels = <0 4 8 16 32 64 128 255>; 28 default-brightness-level = <7>; 29 }; 30 31 leds { 32 compatible = "gpio-leds"; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&pinctrl_gpio_leds>; 35 36 led0: user1 { 37 label = "user1"; 38 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 39 default-state = "on"; 40 linux,default-trigger = "heartbeat"; 41 }; 42 43 led1: user2 { 44 label = "user2"; 45 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 46 default-state = "off"; 47 }; 48 49 led2: user3 { 50 label = "user3"; 51 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 52 default-state = "off"; 53 }; 54 }; 55 56 memory@10000000 { 57 device_type = "memory"; 58 reg = <0x10000000 0x20000000>; 59 }; 60 61 pps { 62 compatible = "pps-gpio"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_pps>; 65 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 66 status = "okay"; 67 }; 68 69 reg_1p0v: regulator-1p0v { 70 compatible = "regulator-fixed"; 71 regulator-name = "1P0V"; 72 regulator-min-microvolt = <1000000>; 73 regulator-max-microvolt = <1000000>; 74 regulator-always-on; 75 }; 76 77 reg_3p3v: regulator-3p3v { 78 compatible = "regulator-fixed"; 79 regulator-name = "3P3V"; 80 regulator-min-microvolt = <3300000>; 81 regulator-max-microvolt = <3300000>; 82 regulator-always-on; 83 }; 84 85 reg_5p0v: regulator-5p0v { 86 compatible = "regulator-fixed"; 87 regulator-name = "5P0V"; 88 regulator-min-microvolt = <5000000>; 89 regulator-max-microvolt = <5000000>; 90 regulator-always-on; 91 }; 92 93 reg_usb_otg_vbus: regulator-usb-otg-vbus { 94 compatible = "regulator-fixed"; 95 regulator-name = "usb_otg_vbus"; 96 regulator-min-microvolt = <5000000>; 97 regulator-max-microvolt = <5000000>; 98 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 99 enable-active-high; 100 }; 101 102 sound { 103 compatible = "fsl,imx6q-ventana-sgtl5000", 104 "fsl,imx-audio-sgtl5000"; 105 model = "sgtl5000-audio"; 106 ssi-controller = <&ssi1>; 107 audio-codec = <&codec>; 108 audio-routing = 109 "MIC_IN", "Mic Jack", 110 "Mic Jack", "Mic Bias", 111 "Headphone Jack", "HP_OUT"; 112 mux-int-port = <1>; 113 mux-ext-port = <4>; 114 }; 115}; 116 117&audmux { 118 pinctrl-names = "default"; 119 pinctrl-0 = <&pinctrl_audmux>; 120 status = "okay"; 121}; 122 123&can1 { 124 pinctrl-names = "default"; 125 pinctrl-0 = <&pinctrl_flexcan1>; 126 status = "okay"; 127}; 128 129&clks { 130 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 131 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 132 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 133 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 134}; 135 136&ecspi3 { 137 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_ecspi3>; 140 status = "okay"; 141}; 142 143&fec { 144 pinctrl-names = "default"; 145 pinctrl-0 = <&pinctrl_enet>; 146 phy-mode = "rgmii-id"; 147 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>; 148 status = "okay"; 149}; 150 151&gpmi { 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_gpmi_nand>; 154 status = "okay"; 155}; 156 157&hdmi { 158 ddc-i2c-bus = <&i2c3>; 159 status = "okay"; 160}; 161 162&i2c1 { 163 clock-frequency = <100000>; 164 pinctrl-names = "default"; 165 pinctrl-0 = <&pinctrl_i2c1>; 166 status = "okay"; 167 168 eeprom1: eeprom@50 { 169 compatible = "atmel,24c02"; 170 reg = <0x50>; 171 pagesize = <16>; 172 }; 173 174 eeprom2: eeprom@51 { 175 compatible = "atmel,24c02"; 176 reg = <0x51>; 177 pagesize = <16>; 178 }; 179 180 eeprom3: eeprom@52 { 181 compatible = "atmel,24c02"; 182 reg = <0x52>; 183 pagesize = <16>; 184 }; 185 186 eeprom4: eeprom@53 { 187 compatible = "atmel,24c02"; 188 reg = <0x53>; 189 pagesize = <16>; 190 }; 191 192 gpio: pca9555@23 { 193 compatible = "nxp,pca9555"; 194 reg = <0x23>; 195 gpio-controller; 196 #gpio-cells = <2>; 197 }; 198 199 rtc: ds1672@68 { 200 compatible = "dallas,ds1672"; 201 reg = <0x68>; 202 }; 203}; 204 205&i2c2 { 206 clock-frequency = <100000>; 207 pinctrl-names = "default"; 208 pinctrl-0 = <&pinctrl_i2c2>; 209 status = "okay"; 210 211 ltc3676: pmic@3c { 212 compatible = "lltc,ltc3676"; 213 reg = <0x3c>; 214 pinctrl-names = "default"; 215 pinctrl-0 = <&pinctrl_pmic>; 216 interrupt-parent = <&gpio1>; 217 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 218 219 regulators { 220 /* VDD_SOC (1+R1/R2 = 1.635) */ 221 reg_vdd_soc: sw1 { 222 regulator-name = "vddsoc"; 223 regulator-min-microvolt = <674400>; 224 regulator-max-microvolt = <1308000>; 225 lltc,fb-voltage-divider = <127000 200000>; 226 regulator-ramp-delay = <7000>; 227 regulator-boot-on; 228 regulator-always-on; 229 }; 230 231 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */ 232 reg_1p8v: sw2 { 233 regulator-name = "vdd1p8"; 234 regulator-min-microvolt = <1033310>; 235 regulator-max-microvolt = <2004000>; 236 lltc,fb-voltage-divider = <301000 200000>; 237 regulator-ramp-delay = <7000>; 238 regulator-boot-on; 239 regulator-always-on; 240 }; 241 242 /* VDD_ARM (1+R1/R2 = 1.635) */ 243 reg_vdd_arm: sw3 { 244 regulator-name = "vddarm"; 245 regulator-min-microvolt = <674400>; 246 regulator-max-microvolt = <1308000>; 247 lltc,fb-voltage-divider = <127000 200000>; 248 regulator-ramp-delay = <7000>; 249 regulator-boot-on; 250 regulator-always-on; 251 }; 252 253 /* VDD_DDR (1+R1/R2 = 2.105) */ 254 reg_vdd_ddr: sw4 { 255 regulator-name = "vddddr"; 256 regulator-min-microvolt = <868310>; 257 regulator-max-microvolt = <1684000>; 258 lltc,fb-voltage-divider = <221000 200000>; 259 regulator-ramp-delay = <7000>; 260 regulator-boot-on; 261 regulator-always-on; 262 }; 263 264 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 265 reg_2p5v: ldo2 { 266 regulator-name = "vdd2p5"; 267 regulator-min-microvolt = <2490375>; 268 regulator-max-microvolt = <2490375>; 269 lltc,fb-voltage-divider = <487000 200000>; 270 regulator-boot-on; 271 regulator-always-on; 272 }; 273 274 /* VDD_AUD_1P8: Audio codec */ 275 reg_aud_1p8v: ldo3 { 276 regulator-name = "vdd1p8"; 277 regulator-min-microvolt = <1800000>; 278 regulator-max-microvolt = <1800000>; 279 regulator-boot-on; 280 }; 281 282 /* VDD_HIGH (1+R1/R2 = 4.17) */ 283 reg_3p0v: ldo4 { 284 regulator-name = "vdd3p0"; 285 regulator-min-microvolt = <3023250>; 286 regulator-max-microvolt = <3023250>; 287 lltc,fb-voltage-divider = <634000 200000>; 288 regulator-boot-on; 289 regulator-always-on; 290 }; 291 }; 292 }; 293}; 294 295&i2c3 { 296 clock-frequency = <100000>; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&pinctrl_i2c3>; 299 status = "okay"; 300 301 codec: sgtl5000@a { 302 compatible = "fsl,sgtl5000"; 303 reg = <0x0a>; 304 clocks = <&clks IMX6QDL_CLK_CKO>; 305 VDDA-supply = <®_1p8v>; 306 VDDIO-supply = <®_3p3v>; 307 }; 308 309 touchscreen: egalax_ts@4 { 310 compatible = "eeti,egalax_ts"; 311 reg = <0x04>; 312 interrupt-parent = <&gpio7>; 313 interrupts = <12 2>; 314 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; 315 }; 316}; 317 318&ldb { 319 status = "okay"; 320 321 lvds-channel@0 { 322 fsl,data-mapping = "spwg"; 323 fsl,data-width = <18>; 324 status = "okay"; 325 326 display-timings { 327 native-mode = <&timing0>; 328 timing0: hsd100pxn1 { 329 clock-frequency = <65000000>; 330 hactive = <1024>; 331 vactive = <768>; 332 hback-porch = <220>; 333 hfront-porch = <40>; 334 vback-porch = <21>; 335 vfront-porch = <7>; 336 hsync-len = <60>; 337 vsync-len = <10>; 338 }; 339 }; 340 }; 341}; 342 343&pcie { 344 pinctrl-names = "default"; 345 pinctrl-0 = <&pinctrl_pcie>; 346 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>; 347 status = "okay"; 348}; 349 350&pwm2 { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 353 status = "disabled"; 354}; 355 356&pwm3 { 357 pinctrl-names = "default"; 358 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 359 status = "disabled"; 360}; 361 362&pwm4 { 363 pinctrl-names = "default"; 364 pinctrl-0 = <&pinctrl_pwm4>; 365 status = "okay"; 366}; 367 368&ssi1 { 369 status = "okay"; 370}; 371 372&uart1 { 373 pinctrl-names = "default"; 374 pinctrl-0 = <&pinctrl_uart1>; 375 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; 376 status = "okay"; 377}; 378 379&uart2 { 380 pinctrl-names = "default"; 381 pinctrl-0 = <&pinctrl_uart2>; 382 status = "okay"; 383}; 384 385&uart5 { 386 pinctrl-names = "default"; 387 pinctrl-0 = <&pinctrl_uart5>; 388 status = "okay"; 389}; 390 391&usbotg { 392 vbus-supply = <®_usb_otg_vbus>; 393 pinctrl-names = "default"; 394 pinctrl-0 = <&pinctrl_usbotg>; 395 disable-over-current; 396 status = "okay"; 397}; 398 399&usbh1 { 400 status = "okay"; 401}; 402 403&usdhc3 { 404 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 405 pinctrl-0 = <&pinctrl_usdhc3>; 406 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 407 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 408 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>; 409 vmmc-supply = <®_3p3v>; 410 no-1-8-v; /* firmware will remove if board revision supports */ 411 status = "okay"; 412}; 413 414&wdog1 { 415 pinctrl-names = "default"; 416 pinctrl-0 = <&pinctrl_wdog>; 417 fsl,ext-reset-output; 418}; 419 420&iomuxc { 421 pinctrl_audmux: audmuxgrp { 422 fsl,pins = < 423 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0 424 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0 425 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 426 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 427 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ 428 >; 429 }; 430 431 pinctrl_ecspi3: escpi3grp { 432 fsl,pins = < 433 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 434 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 435 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 436 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 437 >; 438 }; 439 440 pinctrl_enet: enetgrp { 441 fsl,pins = < 442 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 443 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 444 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 445 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 446 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 447 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 448 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 449 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 450 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 451 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 452 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 453 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 454 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 455 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 456 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 457 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 458 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */ 459 >; 460 }; 461 462 pinctrl_flexcan1: flexcan1grp { 463 fsl,pins = < 464 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 465 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 466 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ 467 >; 468 }; 469 470 pinctrl_gpio_leds: gpioledsgrp { 471 fsl,pins = < 472 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 473 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 474 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 475 >; 476 }; 477 478 pinctrl_gpmi_nand: gpminandgrp { 479 fsl,pins = < 480 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 481 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 482 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 483 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 484 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 485 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 486 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 487 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 488 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 489 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 490 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 491 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 492 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 493 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 494 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 495 >; 496 }; 497 498 pinctrl_i2c1: i2c1grp { 499 fsl,pins = < 500 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 501 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 502 >; 503 }; 504 505 pinctrl_i2c2: i2c2grp { 506 fsl,pins = < 507 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 508 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 509 >; 510 }; 511 512 pinctrl_i2c3: i2c3grp { 513 fsl,pins = < 514 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 515 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 516 >; 517 }; 518 519 pinctrl_pcie: pciegrp { 520 fsl,pins = < 521 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */ 522 >; 523 }; 524 525 pinctrl_pmic: pmicgrp { 526 fsl,pins = < 527 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */ 528 >; 529 }; 530 531 pinctrl_pps: ppsgrp { 532 fsl,pins = < 533 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 534 >; 535 }; 536 537 pinctrl_pwm2: pwm2grp { 538 fsl,pins = < 539 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 540 >; 541 }; 542 543 pinctrl_pwm3: pwm3grp { 544 fsl,pins = < 545 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 546 >; 547 }; 548 549 pinctrl_pwm4: pwm4grp { 550 fsl,pins = < 551 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 552 >; 553 }; 554 555 pinctrl_uart1: uart1grp { 556 fsl,pins = < 557 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 558 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 559 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */ 560 >; 561 }; 562 563 pinctrl_uart2: uart2grp { 564 fsl,pins = < 565 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 566 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 567 >; 568 }; 569 570 pinctrl_uart5: uart5grp { 571 fsl,pins = < 572 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 573 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 574 >; 575 }; 576 577 pinctrl_usbotg: usbotggrp { 578 fsl,pins = < 579 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 580 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */ 581 >; 582 }; 583 584 pinctrl_usdhc3: usdhc3grp { 585 fsl,pins = < 586 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 587 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 588 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 589 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 590 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 591 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 592 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */ 593 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059 594 >; 595 }; 596 597 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 598 fsl,pins = < 599 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 600 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9 601 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 602 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 603 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 604 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 605 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */ 606 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9 607 >; 608 }; 609 610 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 611 fsl,pins = < 612 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 613 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 614 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 615 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 616 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 617 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 618 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */ 619 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9 620 >; 621 }; 622 623 pinctrl_wdog: wdoggrp { 624 fsl,pins = < 625 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 626 >; 627 }; 628}; 629
