1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright 2013 Freescale Semiconductor, Inc.
4
5#include <dt-bindings/interrupt-controller/irq.h>
6#include "imx6q-pinfunc.h"
7#include "imx6qdl.dtsi"
8
9/ {
10	aliases {
11		ipu1 = &ipu2;
12		spi4 = &ecspi5;
13	};
14
15	cpus {
16		#address-cells = <1>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			compatible = "arm,cortex-a9";
21			device_type = "cpu";
22			reg = <0>;
23			next-level-cache = <&L2>;
24			operating-points = <
25				/* kHz    uV */
26				1200000 1275000
27				996000  1250000
28				852000  1250000
29				792000  1175000
30				396000  975000
31			>;
32			fsl,soc-operating-points = <
33				/* ARM kHz  SOC-PU uV */
34				1200000 1275000
35				996000	1250000
36				852000	1250000
37				792000	1175000
38				396000	1175000
39			>;
40			clock-latency = <61036>; /* two CLK32 periods */
41			#cooling-cells = <2>;
42			clocks = <&clks IMX6QDL_CLK_ARM>,
43				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44				 <&clks IMX6QDL_CLK_STEP>,
45				 <&clks IMX6QDL_CLK_PLL1_SW>,
46				 <&clks IMX6QDL_CLK_PLL1_SYS>;
47			clock-names = "arm", "pll2_pfd2_396m", "step",
48				      "pll1_sw", "pll1_sys";
49			arm-supply = <&reg_arm>;
50			pu-supply = <&reg_pu>;
51			soc-supply = <&reg_soc>;
52		};
53
54		cpu1: cpu@1 {
55			compatible = "arm,cortex-a9";
56			device_type = "cpu";
57			reg = <1>;
58			next-level-cache = <&L2>;
59			operating-points = <
60				/* kHz    uV */
61				1200000 1275000
62				996000  1250000
63				852000  1250000
64				792000  1175000
65				396000  975000
66			>;
67			fsl,soc-operating-points = <
68				/* ARM kHz  SOC-PU uV */
69				1200000 1275000
70				996000	1250000
71				852000	1250000
72				792000	1175000
73				396000	1175000
74			>;
75			clock-latency = <61036>; /* two CLK32 periods */
76			clocks = <&clks IMX6QDL_CLK_ARM>,
77				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
78				 <&clks IMX6QDL_CLK_STEP>,
79				 <&clks IMX6QDL_CLK_PLL1_SW>,
80				 <&clks IMX6QDL_CLK_PLL1_SYS>;
81			clock-names = "arm", "pll2_pfd2_396m", "step",
82				      "pll1_sw", "pll1_sys";
83			arm-supply = <&reg_arm>;
84			pu-supply = <&reg_pu>;
85			soc-supply = <&reg_soc>;
86		};
87
88		cpu2: cpu@2 {
89			compatible = "arm,cortex-a9";
90			device_type = "cpu";
91			reg = <2>;
92			next-level-cache = <&L2>;
93			operating-points = <
94				/* kHz    uV */
95				1200000 1275000
96				996000  1250000
97				852000  1250000
98				792000  1175000
99				396000  975000
100			>;
101			fsl,soc-operating-points = <
102				/* ARM kHz  SOC-PU uV */
103				1200000 1275000
104				996000	1250000
105				852000	1250000
106				792000	1175000
107				396000	1175000
108			>;
109			clock-latency = <61036>; /* two CLK32 periods */
110			clocks = <&clks IMX6QDL_CLK_ARM>,
111				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
112				 <&clks IMX6QDL_CLK_STEP>,
113				 <&clks IMX6QDL_CLK_PLL1_SW>,
114				 <&clks IMX6QDL_CLK_PLL1_SYS>;
115			clock-names = "arm", "pll2_pfd2_396m", "step",
116				      "pll1_sw", "pll1_sys";
117			arm-supply = <&reg_arm>;
118			pu-supply = <&reg_pu>;
119			soc-supply = <&reg_soc>;
120		};
121
122		cpu3: cpu@3 {
123			compatible = "arm,cortex-a9";
124			device_type = "cpu";
125			reg = <3>;
126			next-level-cache = <&L2>;
127			operating-points = <
128				/* kHz    uV */
129				1200000 1275000
130				996000  1250000
131				852000  1250000
132				792000  1175000
133				396000  975000
134			>;
135			fsl,soc-operating-points = <
136				/* ARM kHz  SOC-PU uV */
137				1200000 1275000
138				996000	1250000
139				852000	1250000
140				792000	1175000
141				396000	1175000
142			>;
143			clock-latency = <61036>; /* two CLK32 periods */
144			clocks = <&clks IMX6QDL_CLK_ARM>,
145				 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
146				 <&clks IMX6QDL_CLK_STEP>,
147				 <&clks IMX6QDL_CLK_PLL1_SW>,
148				 <&clks IMX6QDL_CLK_PLL1_SYS>;
149			clock-names = "arm", "pll2_pfd2_396m", "step",
150				      "pll1_sw", "pll1_sys";
151			arm-supply = <&reg_arm>;
152			pu-supply = <&reg_pu>;
153			soc-supply = <&reg_soc>;
154		};
155	};
156
157	soc {
158		ocram: sram@900000 {
159			compatible = "mmio-sram";
160			reg = <0x00900000 0x40000>;
161			clocks = <&clks IMX6QDL_CLK_OCRAM>;
162		};
163
164		aips-bus@2000000 { /* AIPS1 */
165			spba-bus@2000000 {
166				ecspi5: spi@2018000 {
167					#address-cells = <1>;
168					#size-cells = <0>;
169					compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
170					reg = <0x02018000 0x4000>;
171					interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
172					clocks = <&clks IMX6Q_CLK_ECSPI5>,
173						 <&clks IMX6Q_CLK_ECSPI5>;
174					clock-names = "ipg", "per";
175					dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
176					dma-names = "rx", "tx";
177					status = "disabled";
178				};
179			};
180
181			iomuxc: iomuxc@20e0000 {
182				compatible = "fsl,imx6q-iomuxc";
183			};
184		};
185
186		sata: sata@2200000 {
187			compatible = "fsl,imx6q-ahci";
188			reg = <0x02200000 0x4000>;
189			interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
190			clocks = <&clks IMX6QDL_CLK_SATA>,
191				 <&clks IMX6QDL_CLK_SATA_REF_100M>,
192				 <&clks IMX6QDL_CLK_AHB>;
193			clock-names = "sata", "sata_ref", "ahb";
194			status = "disabled";
195		};
196
197		gpu_vg: gpu@2204000 {
198			compatible = "vivante,gc";
199			reg = <0x02204000 0x4000>;
200			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
201			clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>,
202				 <&clks IMX6QDL_CLK_GPU2D_CORE>;
203			clock-names = "bus", "core";
204			power-domains = <&pd_pu>;
205			#cooling-cells = <2>;
206		};
207
208		ipu2: ipu@2800000 {
209			#address-cells = <1>;
210			#size-cells = <0>;
211			compatible = "fsl,imx6q-ipu";
212			reg = <0x02800000 0x400000>;
213			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
214				     <0 7 IRQ_TYPE_LEVEL_HIGH>;
215			clocks = <&clks IMX6QDL_CLK_IPU2>,
216				 <&clks IMX6QDL_CLK_IPU2_DI0>,
217				 <&clks IMX6QDL_CLK_IPU2_DI1>;
218			clock-names = "bus", "di0", "di1";
219			resets = <&src 4>;
220
221			ipu2_csi0: port@0 {
222				reg = <0>;
223
224				ipu2_csi0_from_mipi_vc2: endpoint {
225					remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
226				};
227			};
228
229			ipu2_csi1: port@1 {
230				reg = <1>;
231
232				ipu2_csi1_from_ipu2_csi1_mux: endpoint {
233					remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
234				};
235			};
236
237			ipu2_di0: port@2 {
238				#address-cells = <1>;
239				#size-cells = <0>;
240				reg = <2>;
241
242				ipu2_di0_disp0: endpoint@0 {
243					reg = <0>;
244				};
245
246				ipu2_di0_hdmi: endpoint@1 {
247					reg = <1>;
248					remote-endpoint = <&hdmi_mux_2>;
249				};
250
251				ipu2_di0_mipi: endpoint@2 {
252					reg = <2>;
253					remote-endpoint = <&mipi_mux_2>;
254				};
255
256				ipu2_di0_lvds0: endpoint@3 {
257					reg = <3>;
258					remote-endpoint = <&lvds0_mux_2>;
259				};
260
261				ipu2_di0_lvds1: endpoint@4 {
262					reg = <4>;
263					remote-endpoint = <&lvds1_mux_2>;
264				};
265			};
266
267			ipu2_di1: port@3 {
268				#address-cells = <1>;
269				#size-cells = <0>;
270				reg = <3>;
271
272				ipu2_di1_hdmi: endpoint@1 {
273					reg = <1>;
274					remote-endpoint = <&hdmi_mux_3>;
275				};
276
277				ipu2_di1_mipi: endpoint@2 {
278					reg = <2>;
279					remote-endpoint = <&mipi_mux_3>;
280				};
281
282				ipu2_di1_lvds0: endpoint@3 {
283					reg = <3>;
284					remote-endpoint = <&lvds0_mux_3>;
285				};
286
287				ipu2_di1_lvds1: endpoint@4 {
288					reg = <4>;
289					remote-endpoint = <&lvds1_mux_3>;
290				};
291			};
292		};
293	};
294
295	capture-subsystem {
296		compatible = "fsl,imx-capture-subsystem";
297		ports = <&ipu1_csi0>, <&ipu1_csi1>, <&ipu2_csi0>, <&ipu2_csi1>;
298	};
299
300	display-subsystem {
301		compatible = "fsl,imx-display-subsystem";
302		ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
303	};
304};
305
306&gpio1 {
307	gpio-ranges = <&iomuxc  0 136  2>, <&iomuxc  2 141 1>, <&iomuxc  3 139 1>,
308		      <&iomuxc  4 142  2>, <&iomuxc  6 140 1>, <&iomuxc  7 144 2>,
309		      <&iomuxc  9 138  1>, <&iomuxc 10 213 3>, <&iomuxc 13  20 1>,
310		      <&iomuxc 14  19  1>, <&iomuxc 15  21 1>, <&iomuxc 16 208 1>,
311		      <&iomuxc 17 207  1>, <&iomuxc 18 210 3>, <&iomuxc 21 209 1>,
312		      <&iomuxc 22 116 10>;
313};
314
315&gpio2 {
316	gpio-ranges = <&iomuxc  0 191 16>, <&iomuxc 16 55 14>, <&iomuxc 30 35 1>,
317		      <&iomuxc 31  44  1>;
318};
319
320&gpio3 {
321	gpio-ranges = <&iomuxc 0 69 16>, <&iomuxc 16 36 8>, <&iomuxc 24 45 8>;
322};
323
324&gpio4 {
325	gpio-ranges = <&iomuxc 5 149 1>, <&iomuxc 6 126 10>, <&iomuxc 16 87 16>;
326};
327
328&gpio5 {
329	gpio-ranges = <&iomuxc 0  85  1>, <&iomuxc  2  34  1>, <&iomuxc 4 53 1>,
330		      <&iomuxc 5 103 13>, <&iomuxc 18 150 14>;
331};
332
333&gpio6 {
334	gpio-ranges = <&iomuxc  0 164 6>, <&iomuxc  6  54 1>, <&iomuxc  7 181  5>,
335		      <&iomuxc 14 186 3>, <&iomuxc 17 170 2>, <&iomuxc 19  22 12>,
336		      <&iomuxc 31  86 1>;
337};
338
339&gpio7 {
340	gpio-ranges = <&iomuxc 0 172 9>, <&iomuxc 9 189 2>, <&iomuxc 11 146 3>;
341};
342
343&gpr {
344	ipu1_csi0_mux {
345		compatible = "video-mux";
346		mux-controls = <&mux 0>;
347		#address-cells = <1>;
348		#size-cells = <0>;
349
350		port@0 {
351			reg = <0>;
352
353			ipu1_csi0_mux_from_mipi_vc0: endpoint {
354				remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
355			};
356		};
357
358		port@1 {
359			reg = <1>;
360
361			ipu1_csi0_mux_from_parallel_sensor: endpoint {
362			};
363		};
364
365		port@2 {
366			reg = <2>;
367
368			ipu1_csi0_mux_to_ipu1_csi0: endpoint {
369				remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
370			};
371		};
372	};
373
374	ipu2_csi1_mux {
375		compatible = "video-mux";
376		mux-controls = <&mux 1>;
377		#address-cells = <1>;
378		#size-cells = <0>;
379
380		port@0 {
381			reg = <0>;
382
383			ipu2_csi1_mux_from_mipi_vc3: endpoint {
384				remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
385			};
386		};
387
388		port@1 {
389			reg = <1>;
390
391			ipu2_csi1_mux_from_parallel_sensor: endpoint {
392			};
393		};
394
395		port@2 {
396			reg = <2>;
397
398			ipu2_csi1_mux_to_ipu2_csi1: endpoint {
399				remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
400			};
401		};
402	};
403};
404
405&hdmi {
406	compatible = "fsl,imx6q-hdmi";
407
408	port@2 {
409		reg = <2>;
410
411		hdmi_mux_2: endpoint {
412			remote-endpoint = <&ipu2_di0_hdmi>;
413		};
414	};
415
416	port@3 {
417		reg = <3>;
418
419		hdmi_mux_3: endpoint {
420			remote-endpoint = <&ipu2_di1_hdmi>;
421		};
422	};
423};
424
425&ipu1_csi1 {
426	ipu1_csi1_from_mipi_vc1: endpoint {
427		remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
428	};
429};
430
431&ldb {
432	clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
433		 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
434		 <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, <&clks IMX6QDL_CLK_IPU2_DI1_SEL>,
435		 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
436	clock-names = "di0_pll", "di1_pll",
437		      "di0_sel", "di1_sel", "di2_sel", "di3_sel",
438		      "di0", "di1";
439
440	lvds-channel@0 {
441		port@2 {
442			reg = <2>;
443
444			lvds0_mux_2: endpoint {
445				remote-endpoint = <&ipu2_di0_lvds0>;
446			};
447		};
448
449		port@3 {
450			reg = <3>;
451
452			lvds0_mux_3: endpoint {
453				remote-endpoint = <&ipu2_di1_lvds0>;
454			};
455		};
456	};
457
458	lvds-channel@1 {
459		port@2 {
460			reg = <2>;
461
462			lvds1_mux_2: endpoint {
463				remote-endpoint = <&ipu2_di0_lvds1>;
464			};
465		};
466
467		port@3 {
468			reg = <3>;
469
470			lvds1_mux_3: endpoint {
471				remote-endpoint = <&ipu2_di1_lvds1>;
472			};
473		};
474	};
475};
476
477&mipi_csi {
478	port@1 {
479		reg = <1>;
480
481		mipi_vc0_to_ipu1_csi0_mux: endpoint {
482			remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
483		};
484	};
485
486	port@2 {
487		reg = <2>;
488
489		mipi_vc1_to_ipu1_csi1: endpoint {
490			remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
491		};
492	};
493
494	port@3 {
495		reg = <3>;
496
497		mipi_vc2_to_ipu2_csi0: endpoint {
498			remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
499		};
500	};
501
502	port@4 {
503		reg = <4>;
504
505		mipi_vc3_to_ipu2_csi1_mux: endpoint {
506			remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
507		};
508	};
509};
510
511&mipi_dsi {
512	ports {
513		port@2 {
514			reg = <2>;
515
516			mipi_mux_2: endpoint {
517				remote-endpoint = <&ipu2_di0_mipi>;
518			};
519		};
520
521		port@3 {
522			reg = <3>;
523
524			mipi_mux_3: endpoint {
525				remote-endpoint = <&ipu2_di1_mipi>;
526			};
527		};
528	};
529};
530
531&mux {
532	mux-reg-masks = <0x04 0x00080000>, /* MIPI_IPU1_MUX */
533			<0x04 0x00100000>, /* MIPI_IPU2_MUX */
534			<0x0c 0x0000000c>, /* HDMI_MUX_CTL */
535			<0x0c 0x000000c0>, /* LVDS0_MUX_CTL */
536			<0x0c 0x00000300>, /* LVDS1_MUX_CTL */
537			<0x28 0x00000003>, /* DCIC1_MUX_CTL */
538			<0x28 0x0000000c>; /* DCIC2_MUX_CTL */
539};
540
541&vpu {
542	compatible = "fsl,imx6q-vpu", "cnm,coda960";
543};
544