1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6/dts-v1/;
7#include "imx6q.dtsi"
8#include "imx6qdl-gw54xx.dtsi"
9#include <dt-bindings/media/tda1997x.h>
10
11/ {
12	model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX";
13	compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q";
14
15	sound-digital {
16		compatible = "simple-audio-card";
17		simple-audio-card,name = "tda1997x-audio";
18
19		simple-audio-card,dai-link@0 {
20			format = "i2s";
21
22			cpu {
23				sound-dai = <&ssi2>;
24			};
25
26			codec {
27				bitclock-master;
28				frame-master;
29				sound-dai = <&hdmi_receiver>;
30			};
31		};
32	};
33};
34
35&i2c3 {
36	adv7180: camera@20 {
37		compatible = "adi,adv7180";
38		pinctrl-names = "default";
39		pinctrl-0 = <&pinctrl_adv7180>;
40		reg = <0x20>;
41		powerdown-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
42		interrupt-parent = <&gpio3>;
43		interrupts = <30 IRQ_TYPE_LEVEL_LOW>;
44
45		port {
46			adv7180_to_ipu2_csi1_mux: endpoint {
47				remote-endpoint = <&ipu2_csi1_mux_from_parallel_sensor>;
48				bus-width = <8>;
49			};
50		};
51	};
52
53	hdmi_receiver: hdmi-receiver@48 {
54		compatible = "nxp,tda19971";
55		pinctrl-names = "default";
56		pinctrl-0 = <&pinctrl_tda1997x>;
57		reg = <0x48>;
58		interrupt-parent = <&gpio1>;
59		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
60		DOVDD-supply = <&reg_3p3v>;
61		AVDD-supply = <&sw4_reg>;
62		DVDD-supply = <&sw4_reg>;
63		#sound-dai-cells = <0>;
64		nxp,audout-format = "i2s";
65		nxp,audout-layout = <0>;
66		nxp,audout-width = <16>;
67		nxp,audout-mclk-fs = <128>;
68		/*
69		 * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
70		 * and Y[11:4] across 16bits in the same cycle
71		 * which we map to VP[15:08]<->CSI_DATA[19:12]
72		 */
73		nxp,vidout-portcfg =
74			/*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/
75			< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
76			/*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/
77			< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
78			/*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/
79			< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
80			/*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/
81			< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
82
83		port {
84			tda1997x_to_ipu1_csi0_mux: endpoint {
85				remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
86				bus-width = <16>;
87				hsync-active = <1>;
88				vsync-active = <1>;
89				data-active = <1>;
90			};
91		};
92	};
93};
94
95&ipu1_csi0_from_ipu1_csi0_mux {
96	bus-width = <16>;
97};
98
99&ipu1_csi0_mux_from_parallel_sensor {
100	remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
101	bus-width = <16>;
102};
103
104&ipu1_csi0 {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_ipu1_csi0>;
107};
108
109&ipu2_csi1_from_ipu2_csi1_mux {
110	bus-width = <8>;
111};
112
113&ipu2_csi1_mux_from_parallel_sensor {
114	remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
115	bus-width = <8>;
116};
117
118&ipu2_csi1 {
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_ipu2_csi1>;
121};
122
123&sata {
124	status = "okay";
125};
126
127&iomuxc {
128	pinctrl_adv7180: adv7180grp {
129		fsl,pins = <
130			MX6QDL_PAD_EIM_D30__GPIO3_IO30          0x0001b0b0
131			MX6QDL_PAD_EIM_D31__GPIO3_IO31          0x4001b0b0
132		>;
133	};
134
135	pinctrl_ipu1_csi0: ipu1_csi0grp {
136		fsl,pins = <
137			MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04		0x1b0b0
138			MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05		0x1b0b0
139			MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06		0x1b0b0
140			MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07		0x1b0b0
141			MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08		0x1b0b0
142			MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09		0x1b0b0
143			MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10		0x1b0b0
144			MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11		0x1b0b0
145			MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12		0x1b0b0
146			MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13		0x1b0b0
147			MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14		0x1b0b0
148			MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15		0x1b0b0
149			MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16		0x1b0b0
150			MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17		0x1b0b0
151			MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18		0x1b0b0
152			MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19		0x1b0b0
153			MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC		0x1b0b0
154			MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK	0x1b0b0
155			MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC		0x1b0b0
156		>;
157	};
158
159	pinctrl_ipu2_csi1: ipu2_csi1grp {
160		fsl,pins = <
161			MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19    0x1b0b0
162			MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18    0x1b0b0
163			MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17    0x1b0b0
164			MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16    0x1b0b0
165			MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15    0x1b0b0
166			MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14    0x1b0b0
167			MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13    0x1b0b0
168			MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12    0x1b0b0
169			MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC     0x1b0b0
170			MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC     0x1b0b0
171			MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK    0x1b0b0
172		>;
173	};
174
175	pinctrl_tda1997x: tda1997xgrp {
176		fsl,pins = <
177			MX6QDL_PAD_GPIO_7__GPIO1_IO07	0x1b0b0
178		>;
179	};
180};
181