1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2011 Freescale Semiconductor, Inc. 4// Copyright 2011 Linaro Ltd. 5 6#include "imx51-pinfunc.h" 7#include <dt-bindings/clock/imx5-clock.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 /* 16 * The decompressor and also some bootloaders rely on a 17 * pre-existing /chosen node to be available to insert the 18 * command line and merge other ATAGS info. 19 */ 20 chosen {}; 21 22 aliases { 23 ethernet0 = &fec; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 mmc0 = &esdhc1; 31 mmc1 = &esdhc2; 32 mmc2 = &esdhc3; 33 mmc3 = &esdhc4; 34 serial0 = &uart1; 35 serial1 = &uart2; 36 serial2 = &uart3; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &cspi; 40 }; 41 42 tzic: tz-interrupt-controller@e0000000 { 43 compatible = "fsl,imx51-tzic", "fsl,tzic"; 44 interrupt-controller; 45 #interrupt-cells = <1>; 46 reg = <0xe0000000 0x4000>; 47 }; 48 49 clocks { 50 ckil { 51 compatible = "fsl,imx-ckil", "fixed-clock"; 52 #clock-cells = <0>; 53 clock-frequency = <32768>; 54 }; 55 56 ckih1 { 57 compatible = "fsl,imx-ckih1", "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <0>; 60 }; 61 62 ckih2 { 63 compatible = "fsl,imx-ckih2", "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 }; 67 68 osc { 69 compatible = "fsl,imx-osc", "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <24000000>; 72 }; 73 }; 74 75 cpus { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 cpu: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a8"; 81 reg = <0>; 82 clock-latency = <62500>; 83 clocks = <&clks IMX5_CLK_CPU_PODF>; 84 clock-names = "cpu"; 85 operating-points = < 86 166000 1000000 87 600000 1050000 88 800000 1100000 89 >; 90 voltage-tolerance = <5>; 91 }; 92 }; 93 94 pmu: pmu { 95 compatible = "arm,cortex-a8-pmu"; 96 interrupt-parent = <&tzic>; 97 interrupts = <77>; 98 }; 99 100 usbphy0: usbphy0 { 101 compatible = "usb-nop-xceiv"; 102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>; 103 clock-names = "main_clk"; 104 #phy-cells = <0>; 105 }; 106 107 display-subsystem { 108 compatible = "fsl,imx-display-subsystem"; 109 ports = <&ipu_di0>, <&ipu_di1>; 110 }; 111 112 soc { 113 #address-cells = <1>; 114 #size-cells = <1>; 115 compatible = "simple-bus"; 116 interrupt-parent = <&tzic>; 117 ranges; 118 119 iram: iram@1ffe0000 { 120 compatible = "mmio-sram"; 121 reg = <0x1ffe0000 0x20000>; 122 }; 123 124 gpu: gpu@30000000 { 125 compatible = "amd,imageon-200.1", "amd,imageon"; 126 reg = <0x30000000 0x20000>; 127 reg-names = "kgsl_3d0_reg_memory"; 128 interrupts = <12>; 129 interrupt-names = "kgsl_3d0_irq"; 130 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; 131 clock-names = "core_clk", "mem_iface_clk"; 132 }; 133 134 ipu: ipu@40000000 { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 compatible = "fsl,imx51-ipu"; 138 reg = <0x40000000 0x20000000>; 139 interrupts = <11 10>; 140 clocks = <&clks IMX5_CLK_IPU_GATE>, 141 <&clks IMX5_CLK_IPU_DI0_GATE>, 142 <&clks IMX5_CLK_IPU_DI1_GATE>; 143 clock-names = "bus", "di0", "di1"; 144 resets = <&src 2>; 145 146 ipu_di0: port@2 { 147 reg = <2>; 148 149 ipu_di0_disp1: endpoint { 150 }; 151 }; 152 153 ipu_di1: port@3 { 154 reg = <3>; 155 156 ipu_di1_disp2: endpoint { 157 }; 158 }; 159 }; 160 161 aips@70000000 { /* AIPS1 */ 162 compatible = "fsl,aips-bus", "simple-bus"; 163 #address-cells = <1>; 164 #size-cells = <1>; 165 reg = <0x70000000 0x10000000>; 166 ranges; 167 168 spba@70000000 { 169 compatible = "fsl,spba-bus", "simple-bus"; 170 #address-cells = <1>; 171 #size-cells = <1>; 172 reg = <0x70000000 0x40000>; 173 ranges; 174 175 esdhc1: esdhc@70004000 { 176 compatible = "fsl,imx51-esdhc"; 177 reg = <0x70004000 0x4000>; 178 interrupts = <1>; 179 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 180 <&clks IMX5_CLK_DUMMY>, 181 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 182 clock-names = "ipg", "ahb", "per"; 183 status = "disabled"; 184 }; 185 186 esdhc2: esdhc@70008000 { 187 compatible = "fsl,imx51-esdhc"; 188 reg = <0x70008000 0x4000>; 189 interrupts = <2>; 190 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 191 <&clks IMX5_CLK_DUMMY>, 192 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 193 clock-names = "ipg", "ahb", "per"; 194 bus-width = <4>; 195 status = "disabled"; 196 }; 197 198 uart3: serial@7000c000 { 199 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 200 reg = <0x7000c000 0x4000>; 201 interrupts = <33>; 202 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 203 <&clks IMX5_CLK_UART3_PER_GATE>; 204 clock-names = "ipg", "per"; 205 status = "disabled"; 206 }; 207 208 ecspi1: spi@70010000 { 209 #address-cells = <1>; 210 #size-cells = <0>; 211 compatible = "fsl,imx51-ecspi"; 212 reg = <0x70010000 0x4000>; 213 interrupts = <36>; 214 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 215 <&clks IMX5_CLK_ECSPI1_PER_GATE>; 216 clock-names = "ipg", "per"; 217 status = "disabled"; 218 }; 219 220 ssi2: ssi@70014000 { 221 #sound-dai-cells = <0>; 222 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 223 reg = <0x70014000 0x4000>; 224 interrupts = <30>; 225 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, 226 <&clks IMX5_CLK_SSI2_ROOT_GATE>; 227 clock-names = "ipg", "baud"; 228 dmas = <&sdma 24 1 0>, 229 <&sdma 25 1 0>; 230 dma-names = "rx", "tx"; 231 fsl,fifo-depth = <15>; 232 status = "disabled"; 233 }; 234 235 esdhc3: esdhc@70020000 { 236 compatible = "fsl,imx51-esdhc"; 237 reg = <0x70020000 0x4000>; 238 interrupts = <3>; 239 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, 240 <&clks IMX5_CLK_DUMMY>, 241 <&clks IMX5_CLK_ESDHC3_PER_GATE>; 242 clock-names = "ipg", "ahb", "per"; 243 bus-width = <4>; 244 status = "disabled"; 245 }; 246 247 esdhc4: esdhc@70024000 { 248 compatible = "fsl,imx51-esdhc"; 249 reg = <0x70024000 0x4000>; 250 interrupts = <4>; 251 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, 252 <&clks IMX5_CLK_DUMMY>, 253 <&clks IMX5_CLK_ESDHC4_PER_GATE>; 254 clock-names = "ipg", "ahb", "per"; 255 bus-width = <4>; 256 status = "disabled"; 257 }; 258 }; 259 260 aipstz1: bridge@73f00000 { 261 compatible = "fsl,imx51-aipstz"; 262 reg = <0x73f00000 0x60>; 263 }; 264 265 usbotg: usb@73f80000 { 266 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 267 reg = <0x73f80000 0x0200>; 268 interrupts = <18>; 269 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 270 fsl,usbmisc = <&usbmisc 0>; 271 fsl,usbphy = <&usbphy0>; 272 status = "disabled"; 273 }; 274 275 usbh1: usb@73f80200 { 276 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 277 reg = <0x73f80200 0x0200>; 278 interrupts = <14>; 279 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 280 fsl,usbmisc = <&usbmisc 1>; 281 dr_mode = "host"; 282 status = "disabled"; 283 }; 284 285 usbh2: usb@73f80400 { 286 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 287 reg = <0x73f80400 0x0200>; 288 interrupts = <16>; 289 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 290 fsl,usbmisc = <&usbmisc 2>; 291 dr_mode = "host"; 292 status = "disabled"; 293 }; 294 295 usbh3: usb@73f80600 { 296 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 297 reg = <0x73f80600 0x0200>; 298 interrupts = <17>; 299 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 300 fsl,usbmisc = <&usbmisc 3>; 301 dr_mode = "host"; 302 status = "disabled"; 303 }; 304 305 usbmisc: usbmisc@73f80800 { 306 #index-cells = <1>; 307 compatible = "fsl,imx51-usbmisc"; 308 reg = <0x73f80800 0x200>; 309 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 310 }; 311 312 gpio1: gpio@73f84000 { 313 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 314 reg = <0x73f84000 0x4000>; 315 interrupts = <50 51>; 316 gpio-controller; 317 #gpio-cells = <2>; 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 }; 321 322 gpio2: gpio@73f88000 { 323 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 324 reg = <0x73f88000 0x4000>; 325 interrupts = <52 53>; 326 gpio-controller; 327 #gpio-cells = <2>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 }; 331 332 gpio3: gpio@73f8c000 { 333 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 334 reg = <0x73f8c000 0x4000>; 335 interrupts = <54 55>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 }; 341 342 gpio4: gpio@73f90000 { 343 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 344 reg = <0x73f90000 0x4000>; 345 interrupts = <56 57>; 346 gpio-controller; 347 #gpio-cells = <2>; 348 interrupt-controller; 349 #interrupt-cells = <2>; 350 }; 351 352 kpp: kpp@73f94000 { 353 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; 354 reg = <0x73f94000 0x4000>; 355 interrupts = <60>; 356 clocks = <&clks IMX5_CLK_DUMMY>; 357 status = "disabled"; 358 }; 359 360 wdog1: wdog@73f98000 { 361 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 362 reg = <0x73f98000 0x4000>; 363 interrupts = <58>; 364 clocks = <&clks IMX5_CLK_DUMMY>; 365 }; 366 367 wdog2: wdog@73f9c000 { 368 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 369 reg = <0x73f9c000 0x4000>; 370 interrupts = <59>; 371 clocks = <&clks IMX5_CLK_DUMMY>; 372 status = "disabled"; 373 }; 374 375 gpt: timer@73fa0000 { 376 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; 377 reg = <0x73fa0000 0x4000>; 378 interrupts = <39>; 379 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, 380 <&clks IMX5_CLK_GPT_HF_GATE>; 381 clock-names = "ipg", "per"; 382 }; 383 384 iomuxc: iomuxc@73fa8000 { 385 compatible = "fsl,imx51-iomuxc"; 386 reg = <0x73fa8000 0x4000>; 387 }; 388 389 pwm1: pwm@73fb4000 { 390 #pwm-cells = <2>; 391 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 392 reg = <0x73fb4000 0x4000>; 393 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, 394 <&clks IMX5_CLK_PWM1_HF_GATE>; 395 clock-names = "ipg", "per"; 396 interrupts = <61>; 397 }; 398 399 pwm2: pwm@73fb8000 { 400 #pwm-cells = <2>; 401 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 402 reg = <0x73fb8000 0x4000>; 403 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, 404 <&clks IMX5_CLK_PWM2_HF_GATE>; 405 clock-names = "ipg", "per"; 406 interrupts = <94>; 407 }; 408 409 uart1: serial@73fbc000 { 410 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 411 reg = <0x73fbc000 0x4000>; 412 interrupts = <31>; 413 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, 414 <&clks IMX5_CLK_UART1_PER_GATE>; 415 clock-names = "ipg", "per"; 416 status = "disabled"; 417 }; 418 419 uart2: serial@73fc0000 { 420 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 421 reg = <0x73fc0000 0x4000>; 422 interrupts = <32>; 423 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, 424 <&clks IMX5_CLK_UART2_PER_GATE>; 425 clock-names = "ipg", "per"; 426 status = "disabled"; 427 }; 428 429 src: src@73fd0000 { 430 compatible = "fsl,imx51-src"; 431 reg = <0x73fd0000 0x4000>; 432 #reset-cells = <1>; 433 }; 434 435 clks: ccm@73fd4000{ 436 compatible = "fsl,imx51-ccm"; 437 reg = <0x73fd4000 0x4000>; 438 interrupts = <0 71 0x04 0 72 0x04>; 439 #clock-cells = <1>; 440 }; 441 }; 442 443 aips@80000000 { /* AIPS2 */ 444 compatible = "fsl,aips-bus", "simple-bus"; 445 #address-cells = <1>; 446 #size-cells = <1>; 447 reg = <0x80000000 0x10000000>; 448 ranges; 449 450 aipstz2: bridge@83f00000 { 451 compatible = "fsl,imx51-aipstz"; 452 reg = <0x83f00000 0x60>; 453 }; 454 455 iim: iim@83f98000 { 456 compatible = "fsl,imx51-iim", "fsl,imx27-iim"; 457 reg = <0x83f98000 0x4000>; 458 interrupts = <69>; 459 clocks = <&clks IMX5_CLK_IIM_GATE>; 460 }; 461 462 tigerp: tigerp@83fa0000 { 463 compatible = "fsl,imx51-tigerp"; 464 reg = <0x83fa0000 0x28>; 465 }; 466 467 owire: owire@83fa4000 { 468 compatible = "fsl,imx51-owire", "fsl,imx21-owire"; 469 reg = <0x83fa4000 0x4000>; 470 interrupts = <88>; 471 clocks = <&clks IMX5_CLK_OWIRE_GATE>; 472 status = "disabled"; 473 }; 474 475 ecspi2: spi@83fac000 { 476 #address-cells = <1>; 477 #size-cells = <0>; 478 compatible = "fsl,imx51-ecspi"; 479 reg = <0x83fac000 0x4000>; 480 interrupts = <37>; 481 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, 482 <&clks IMX5_CLK_ECSPI2_PER_GATE>; 483 clock-names = "ipg", "per"; 484 status = "disabled"; 485 }; 486 487 sdma: sdma@83fb0000 { 488 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 489 reg = <0x83fb0000 0x4000>; 490 interrupts = <6>; 491 clocks = <&clks IMX5_CLK_SDMA_GATE>, 492 <&clks IMX5_CLK_AHB>; 493 clock-names = "ipg", "ahb"; 494 #dma-cells = <3>; 495 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 496 }; 497 498 cspi: spi@83fc0000 { 499 #address-cells = <1>; 500 #size-cells = <0>; 501 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 502 reg = <0x83fc0000 0x4000>; 503 interrupts = <38>; 504 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, 505 <&clks IMX5_CLK_CSPI_IPG_GATE>; 506 clock-names = "ipg", "per"; 507 status = "disabled"; 508 }; 509 510 i2c2: i2c@83fc4000 { 511 #address-cells = <1>; 512 #size-cells = <0>; 513 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 514 reg = <0x83fc4000 0x4000>; 515 interrupts = <63>; 516 clocks = <&clks IMX5_CLK_I2C2_GATE>; 517 status = "disabled"; 518 }; 519 520 i2c1: i2c@83fc8000 { 521 #address-cells = <1>; 522 #size-cells = <0>; 523 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 524 reg = <0x83fc8000 0x4000>; 525 interrupts = <62>; 526 clocks = <&clks IMX5_CLK_I2C1_GATE>; 527 status = "disabled"; 528 }; 529 530 ssi1: ssi@83fcc000 { 531 #sound-dai-cells = <0>; 532 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 533 reg = <0x83fcc000 0x4000>; 534 interrupts = <29>; 535 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, 536 <&clks IMX5_CLK_SSI1_ROOT_GATE>; 537 clock-names = "ipg", "baud"; 538 dmas = <&sdma 28 0 0>, 539 <&sdma 29 0 0>; 540 dma-names = "rx", "tx"; 541 fsl,fifo-depth = <15>; 542 status = "disabled"; 543 }; 544 545 audmux: audmux@83fd0000 { 546 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; 547 reg = <0x83fd0000 0x4000>; 548 clocks = <&clks IMX5_CLK_DUMMY>; 549 clock-names = "audmux"; 550 status = "disabled"; 551 }; 552 553 m4if: m4if@83fd8000 { 554 compatible = "fsl,imx51-m4if"; 555 reg = <0x83fd8000 0x1000>; 556 }; 557 558 weim: weim@83fda000 { 559 #address-cells = <2>; 560 #size-cells = <1>; 561 compatible = "fsl,imx51-weim"; 562 reg = <0x83fda000 0x1000>; 563 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; 564 ranges = < 565 0 0 0xb0000000 0x08000000 566 1 0 0xb8000000 0x08000000 567 2 0 0xc0000000 0x08000000 568 3 0 0xc8000000 0x04000000 569 4 0 0xcc000000 0x02000000 570 5 0 0xce000000 0x02000000 571 >; 572 status = "disabled"; 573 }; 574 575 nfc: nand@83fdb000 { 576 #address-cells = <1>; 577 #size-cells = <1>; 578 compatible = "fsl,imx51-nand"; 579 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 580 interrupts = <8>; 581 clocks = <&clks IMX5_CLK_NFC_GATE>; 582 status = "disabled"; 583 }; 584 585 pata: pata@83fe0000 { 586 compatible = "fsl,imx51-pata", "fsl,imx27-pata"; 587 reg = <0x83fe0000 0x4000>; 588 interrupts = <70>; 589 clocks = <&clks IMX5_CLK_PATA_GATE>; 590 status = "disabled"; 591 }; 592 593 ssi3: ssi@83fe8000 { 594 #sound-dai-cells = <0>; 595 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 596 reg = <0x83fe8000 0x4000>; 597 interrupts = <96>; 598 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, 599 <&clks IMX5_CLK_SSI3_ROOT_GATE>; 600 clock-names = "ipg", "baud"; 601 dmas = <&sdma 46 0 0>, 602 <&sdma 47 0 0>; 603 dma-names = "rx", "tx"; 604 fsl,fifo-depth = <15>; 605 status = "disabled"; 606 }; 607 608 fec: ethernet@83fec000 { 609 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 610 reg = <0x83fec000 0x4000>; 611 interrupts = <87>; 612 clocks = <&clks IMX5_CLK_FEC_GATE>, 613 <&clks IMX5_CLK_FEC_GATE>, 614 <&clks IMX5_CLK_FEC_GATE>; 615 clock-names = "ipg", "ahb", "ptp"; 616 status = "disabled"; 617 }; 618 619 vpu: vpu@83ff4000 { 620 compatible = "fsl,imx51-vpu", "cnm,codahx4"; 621 reg = <0x83ff4000 0x1000>; 622 interrupts = <9>; 623 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 624 <&clks IMX5_CLK_VPU_GATE>; 625 clock-names = "per", "ahb"; 626 resets = <&src 1>; 627 iram = <&iram>; 628 }; 629 630 sahara: crypto@83ff8000 { 631 compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; 632 reg = <0x83ff8000 0x4000>; 633 interrupts = <19 20>; 634 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, 635 <&clks IMX5_CLK_SAHARA_IPG_GATE>; 636 clock-names = "ipg", "ahb"; 637 }; 638 }; 639 }; 640}; 641
