1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/ 4 */ 5/dts-v1/; 6 7#include "dra72x.dtsi" 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/clk/ti-dra7-atl.h> 10 11/ { 12 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"; 13 14 aliases { 15 display0 = &hdmi0; 16 }; 17 18 chosen { 19 stdout-path = &uart1; 20 }; 21 22 evm_12v0: fixedregulator-evm12v0 { 23 /* main supply */ 24 compatible = "regulator-fixed"; 25 regulator-name = "evm_12v0"; 26 regulator-min-microvolt = <12000000>; 27 regulator-max-microvolt = <12000000>; 28 regulator-always-on; 29 regulator-boot-on; 30 }; 31 32 evm_5v0: fixedregulator-evm5v0 { 33 /* Output 1 of TPS43351QDAPRQ1 on dra72-evm */ 34 /* Output 1 of LM5140QRWGTQ1 on dra71-evm */ 35 compatible = "regulator-fixed"; 36 regulator-name = "evm_5v0"; 37 regulator-min-microvolt = <5000000>; 38 regulator-max-microvolt = <5000000>; 39 vin-supply = <&evm_12v0>; 40 regulator-always-on; 41 regulator-boot-on; 42 }; 43 44 evm_3v6: fixedregulator-evm_3v6 { 45 compatible = "regulator-fixed"; 46 regulator-name = "evm_3v6"; 47 regulator-min-microvolt = <3600000>; 48 regulator-max-microvolt = <3600000>; 49 vin-supply = <&evm_5v0>; 50 regulator-always-on; 51 regulator-boot-on; 52 }; 53 54 vsys_3v3: fixedregulator-vsys3v3 { 55 /* Output 2 of TPS43351QDAPRQ1 on dra72-evm */ 56 /* Output 2 of LM5140QRWGTQ1 on dra71-evm */ 57 compatible = "regulator-fixed"; 58 regulator-name = "vsys_3v3"; 59 regulator-min-microvolt = <3300000>; 60 regulator-max-microvolt = <3300000>; 61 vin-supply = <&evm_12v0>; 62 regulator-always-on; 63 regulator-boot-on; 64 }; 65 66 evm_3v3_sw: fixedregulator-evm_3v3 { 67 /* TPS22965DSG */ 68 compatible = "regulator-fixed"; 69 regulator-name = "evm_3v3"; 70 regulator-min-microvolt = <3300000>; 71 regulator-max-microvolt = <3300000>; 72 vin-supply = <&vsys_3v3>; 73 regulator-always-on; 74 regulator-boot-on; 75 }; 76 77 aic_dvdd: fixedregulator-aic_dvdd { 78 /* TPS77018DBVT */ 79 compatible = "regulator-fixed"; 80 regulator-name = "aic_dvdd"; 81 vin-supply = <&evm_3v3_sw>; 82 regulator-min-microvolt = <1800000>; 83 regulator-max-microvolt = <1800000>; 84 }; 85 86 evm_3v3_sd: fixedregulator-sd { 87 compatible = "regulator-fixed"; 88 regulator-name = "evm_3v3_sd"; 89 regulator-min-microvolt = <3300000>; 90 regulator-max-microvolt = <3300000>; 91 vin-supply = <&evm_3v3_sw>; 92 enable-active-high; 93 gpio = <&pcf_gpio_21 5 GPIO_ACTIVE_HIGH>; 94 }; 95 96 extcon_usb1: extcon_usb1 { 97 compatible = "linux,extcon-usb-gpio"; 98 id-gpio = <&pcf_gpio_21 1 GPIO_ACTIVE_HIGH>; 99 }; 100 101 extcon_usb2: extcon_usb2 { 102 compatible = "linux,extcon-usb-gpio"; 103 id-gpio = <&pcf_gpio_21 2 GPIO_ACTIVE_HIGH>; 104 }; 105 106 hdmi0: connector { 107 compatible = "hdmi-connector"; 108 label = "hdmi"; 109 110 type = "a"; 111 112 port { 113 hdmi_connector_in: endpoint { 114 remote-endpoint = <&tpd12s015_out>; 115 }; 116 }; 117 }; 118 119 tpd12s015: encoder { 120 compatible = "ti,tpd12s015"; 121 122 gpios = <&pcf_hdmi 4 GPIO_ACTIVE_HIGH>, /* P4, CT CP HPD */ 123 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */ 124 <&gpio7 12 GPIO_ACTIVE_HIGH>; /* gpio7_12/sp1_cs2, HPD */ 125 126 ports { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 130 port@0 { 131 reg = <0>; 132 133 tpd12s015_in: endpoint { 134 remote-endpoint = <&hdmi_out>; 135 }; 136 }; 137 138 port@1 { 139 reg = <1>; 140 141 tpd12s015_out: endpoint { 142 remote-endpoint = <&hdmi_connector_in>; 143 }; 144 }; 145 }; 146 }; 147 148 sound0: sound0 { 149 compatible = "simple-audio-card"; 150 simple-audio-card,name = "DRA7xx-EVM"; 151 simple-audio-card,widgets = 152 "Headphone", "Headphone Jack", 153 "Line", "Line Out", 154 "Microphone", "Mic Jack", 155 "Line", "Line In"; 156 simple-audio-card,routing = 157 "Headphone Jack", "HPLOUT", 158 "Headphone Jack", "HPROUT", 159 "Line Out", "LLOUT", 160 "Line Out", "RLOUT", 161 "MIC3L", "Mic Jack", 162 "MIC3R", "Mic Jack", 163 "Mic Jack", "Mic Bias", 164 "LINE1L", "Line In", 165 "LINE1R", "Line In"; 166 simple-audio-card,format = "dsp_b"; 167 simple-audio-card,bitclock-master = <&sound0_master>; 168 simple-audio-card,frame-master = <&sound0_master>; 169 simple-audio-card,bitclock-inversion; 170 171 sound0_master: simple-audio-card,cpu { 172 sound-dai = <&mcasp3>; 173 system-clock-frequency = <5644800>; 174 }; 175 176 simple-audio-card,codec { 177 sound-dai = <&tlv320aic3106>; 178 clocks = <&atl_clkin2_ck>; 179 }; 180 }; 181 182 vmmcwl_fixed: fixedregulator-mmcwl { 183 compatible = "regulator-fixed"; 184 regulator-name = "vmmcwl_fixed"; 185 regulator-min-microvolt = <1800000>; 186 regulator-max-microvolt = <1800000>; 187 gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>; 188 enable-active-high; 189 }; 190}; 191 192&dra7_pmx_core { 193 dcan1_pins_default: dcan1_pins_default { 194 pinctrl-single,pins = < 195 DRA7XX_CORE_IOPAD(0x37d0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* dcan1_tx */ 196 DRA7XX_CORE_IOPAD(0x3818, PULL_UP | MUX_MODE1) /* wakeup0.dcan1_rx */ 197 >; 198 }; 199 200 dcan1_pins_sleep: dcan1_pins_sleep { 201 pinctrl-single,pins = < 202 DRA7XX_CORE_IOPAD(0x37d0, MUX_MODE15 | PULL_UP) /* dcan1_tx.off */ 203 DRA7XX_CORE_IOPAD(0x3818, MUX_MODE15 | PULL_UP) /* wakeup0.off */ 204 >; 205 }; 206}; 207 208&i2c1 { 209 status = "okay"; 210 clock-frequency = <400000>; 211 212 pcf_lcd: gpio@20 { 213 compatible = "nxp,pcf8575"; 214 reg = <0x20>; 215 gpio-controller; 216 #gpio-cells = <2>; 217 interrupt-controller; 218 #interrupt-cells = <2>; 219 }; 220 221 pcf_gpio_21: gpio@21 { 222 compatible = "ti,pcf8575", "nxp,pcf8575"; 223 reg = <0x21>; 224 lines-initial-states = <0x1408>; 225 gpio-controller; 226 #gpio-cells = <2>; 227 interrupt-controller; 228 #interrupt-cells = <2>; 229 }; 230 231 tlv320aic3106: tlv320aic3106@19 { 232 #sound-dai-cells = <0>; 233 compatible = "ti,tlv320aic3106"; 234 reg = <0x19>; 235 adc-settle-ms = <40>; 236 ai3x-micbias-vg = <1>; /* 2.0V */ 237 status = "okay"; 238 239 /* Regulators */ 240 AVDD-supply = <&evm_3v3_sw>; 241 IOVDD-supply = <&evm_3v3_sw>; 242 DRVDD-supply = <&evm_3v3_sw>; 243 DVDD-supply = <&aic_dvdd>; 244 }; 245}; 246 247&i2c5 { 248 status = "okay"; 249 clock-frequency = <400000>; 250 251 pcf_hdmi: pcf8575@26 { 252 compatible = "ti,pcf8575", "nxp,pcf8575"; 253 reg = <0x26>; 254 gpio-controller; 255 #gpio-cells = <2>; 256 /* 257 * initial state is used here to keep the mdio interface 258 * selected on RU89 through SEL_VIN4_MUX_S0, VIN2_S1 and 259 * VIN2_S0 driven high otherwise Ethernet stops working 260 * VIN6_SEL_S0 is low, thus selecting McASP3 over VIN6 261 */ 262 lines-initial-states = <0x0f2b>; 263 264 p1 { 265 /* vin6_sel_s0: high: VIN6, low: audio */ 266 gpio-hog; 267 gpios = <1 GPIO_ACTIVE_HIGH>; 268 output-low; 269 line-name = "vin6_sel_s0"; 270 }; 271 }; 272}; 273 274&uart1 { 275 status = "okay"; 276 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 277 <&dra7_pmx_core 0x3e0>; 278}; 279 280&elm { 281 status = "okay"; 282}; 283 284&gpmc { 285 /* 286 * For the existing IOdelay configuration via U-Boot we don't 287 * support NAND on dra72-evm. Keep it disabled. Enabling it 288 * requires a different configuration by U-Boot. 289 */ 290 status = "disabled"; 291 ranges = <0 0 0x08000000 0x01000000>; /* minimum GPMC partition = 16MB */ 292 nand@0,0 { 293 /* To use NAND, DIP switch SW5 must be set like so: 294 * SW5.1 (NAND_SELn) = ON (LOW) 295 * SW5.9 (GPMC_WPN) = OFF (HIGH) 296 */ 297 compatible = "ti,omap2-nand"; 298 reg = <0 0 4>; /* device IO registers */ 299 interrupt-parent = <&gpmc>; 300 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 301 <1 IRQ_TYPE_NONE>; /* termcount */ 302 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */ 303 ti,nand-xfer-type = "prefetch-dma"; 304 ti,nand-ecc-opt = "bch8"; 305 ti,elm-id = <&elm>; 306 nand-bus-width = <16>; 307 gpmc,device-width = <2>; 308 gpmc,sync-clk-ps = <0>; 309 gpmc,cs-on-ns = <0>; 310 gpmc,cs-rd-off-ns = <80>; 311 gpmc,cs-wr-off-ns = <80>; 312 gpmc,adv-on-ns = <0>; 313 gpmc,adv-rd-off-ns = <60>; 314 gpmc,adv-wr-off-ns = <60>; 315 gpmc,we-on-ns = <10>; 316 gpmc,we-off-ns = <50>; 317 gpmc,oe-on-ns = <4>; 318 gpmc,oe-off-ns = <40>; 319 gpmc,access-ns = <40>; 320 gpmc,wr-access-ns = <80>; 321 gpmc,rd-cycle-ns = <80>; 322 gpmc,wr-cycle-ns = <80>; 323 gpmc,bus-turnaround-ns = <0>; 324 gpmc,cycle2cycle-delay-ns = <0>; 325 gpmc,clk-activation-ns = <0>; 326 gpmc,wr-data-mux-bus-ns = <0>; 327 /* MTD partition table */ 328 /* All SPL-* partitions are sized to minimal length 329 * which can be independently programmable. For 330 * NAND flash this is equal to size of erase-block */ 331 #address-cells = <1>; 332 #size-cells = <1>; 333 partition@0 { 334 label = "NAND.SPL"; 335 reg = <0x00000000 0x000020000>; 336 }; 337 partition@1 { 338 label = "NAND.SPL.backup1"; 339 reg = <0x00020000 0x00020000>; 340 }; 341 partition@2 { 342 label = "NAND.SPL.backup2"; 343 reg = <0x00040000 0x00020000>; 344 }; 345 partition@3 { 346 label = "NAND.SPL.backup3"; 347 reg = <0x00060000 0x00020000>; 348 }; 349 partition@4 { 350 label = "NAND.u-boot-spl-os"; 351 reg = <0x00080000 0x00040000>; 352 }; 353 partition@5 { 354 label = "NAND.u-boot"; 355 reg = <0x000c0000 0x00100000>; 356 }; 357 partition@6 { 358 label = "NAND.u-boot-env"; 359 reg = <0x001c0000 0x00020000>; 360 }; 361 partition@7 { 362 label = "NAND.u-boot-env.backup1"; 363 reg = <0x001e0000 0x00020000>; 364 }; 365 partition@8 { 366 label = "NAND.kernel"; 367 reg = <0x00200000 0x00800000>; 368 }; 369 partition@9 { 370 label = "NAND.file-system"; 371 reg = <0x00a00000 0x0f600000>; 372 }; 373 }; 374}; 375 376&omap_dwc3_1 { 377 extcon = <&extcon_usb1>; 378}; 379 380&omap_dwc3_2 { 381 extcon = <&extcon_usb2>; 382}; 383 384&usb1 { 385 dr_mode = "otg"; 386 extcon = <&extcon_usb1>; 387}; 388 389&usb2 { 390 dr_mode = "host"; 391 extcon = <&extcon_usb2>; 392}; 393 394&mmc1 { 395 status = "okay"; 396 pinctrl-names = "default"; 397 pinctrl-0 = <&mmc1_pins_default>; 398 vmmc-supply = <&evm_3v3_sd>; 399 bus-width = <4>; 400 /* 401 * SDCD signal is not being used here - using the fact that GPIO mode 402 * is a viable alternative 403 */ 404 cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>; 405 max-frequency = <192000000>; 406}; 407 408&mmc2 { 409 /* SW5-3 in ON position */ 410 status = "okay"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&mmc2_pins_default>; 413 bus-width = <8>; 414 non-removable; 415 max-frequency = <192000000>; 416}; 417 418&mmc4 { 419 status = "okay"; 420 vmmc-supply = <&evm_3v6>; 421 vqmmc-supply = <&vmmcwl_fixed>; 422 bus-width = <4>; 423 cap-power-off-card; 424 keep-power-in-suspend; 425 non-removable; 426 pinctrl-names = "default", "hs", "sdr12", "sdr25"; 427 pinctrl-0 = <&mmc4_pins_default>; 428 pinctrl-1 = <&mmc4_pins_default>; 429 pinctrl-2 = <&mmc4_pins_default>; 430 pinctrl-3 = <&mmc4_pins_default>; 431 #address-cells = <1>; 432 #size-cells = <0>; 433 wifi@2 { 434 compatible = "ti,wl1835"; 435 reg = <2>; 436 interrupt-parent = <&gpio5>; 437 interrupts = <7 IRQ_TYPE_EDGE_RISING>; 438 }; 439}; 440 441&mac { 442 status = "okay"; 443}; 444 445&dcan1 { 446 status = "ok"; 447 pinctrl-names = "default", "sleep", "active"; 448 pinctrl-0 = <&dcan1_pins_sleep>; 449 pinctrl-1 = <&dcan1_pins_sleep>; 450 pinctrl-2 = <&dcan1_pins_default>; 451}; 452 453&qspi { 454 status = "okay"; 455 456 spi-max-frequency = <76800000>; 457 m25p80@0 { 458 compatible = "s25fl256s1"; 459 spi-max-frequency = <76800000>; 460 reg = <0>; 461 spi-tx-bus-width = <1>; 462 spi-rx-bus-width = <4>; 463 #address-cells = <1>; 464 #size-cells = <1>; 465 466 /* MTD partition table. 467 * The ROM checks the first four physical blocks 468 * for a valid file to boot and the flash here is 469 * 64KiB block size. 470 */ 471 partition@0 { 472 label = "QSPI.SPL"; 473 reg = <0x00000000 0x000010000>; 474 }; 475 partition@1 { 476 label = "QSPI.SPL.backup1"; 477 reg = <0x00010000 0x00010000>; 478 }; 479 partition@2 { 480 label = "QSPI.SPL.backup2"; 481 reg = <0x00020000 0x00010000>; 482 }; 483 partition@3 { 484 label = "QSPI.SPL.backup3"; 485 reg = <0x00030000 0x00010000>; 486 }; 487 partition@4 { 488 label = "QSPI.u-boot"; 489 reg = <0x00040000 0x00100000>; 490 }; 491 partition@5 { 492 label = "QSPI.u-boot-spl-os"; 493 reg = <0x00140000 0x00080000>; 494 }; 495 partition@6 { 496 label = "QSPI.u-boot-env"; 497 reg = <0x001c0000 0x00010000>; 498 }; 499 partition@7 { 500 label = "QSPI.u-boot-env.backup1"; 501 reg = <0x001d0000 0x0010000>; 502 }; 503 partition@8 { 504 label = "QSPI.kernel"; 505 reg = <0x001e0000 0x0800000>; 506 }; 507 partition@9 { 508 label = "QSPI.file-system"; 509 reg = <0x009e0000 0x01620000>; 510 }; 511 }; 512}; 513 514&dss { 515 status = "ok"; 516}; 517 518&hdmi { 519 status = "ok"; 520 521 port { 522 hdmi_out: endpoint { 523 remote-endpoint = <&tpd12s015_in>; 524 }; 525 }; 526}; 527 528&atl { 529 assigned-clocks = <&abe_dpll_sys_clk_mux>, 530 <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>, 531 <&dpll_abe_ck>, 532 <&dpll_abe_m2x2_ck>, 533 <&atl_clkin2_ck>; 534 assigned-clock-parents = <&sys_clkin2>, <&dpll_abe_m2_ck>; 535 assigned-clock-rates = <0>, <0>, <180633600>, <361267200>, <5644800>; 536 537 status = "okay"; 538 539 atl2 { 540 bws = <DRA7_ATL_WS_MCASP2_FSX>; 541 aws = <DRA7_ATL_WS_MCASP3_FSX>; 542 }; 543}; 544 545&mcasp3 { 546 #sound-dai-cells = <0>; 547 548 assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; 549 assigned-clock-parents = <&atl_clkin2_ck>; 550 551 status = "okay"; 552 553 op-mode = <0>; /* MCASP_IIS_MODE */ 554 tdm-slots = <2>; 555 /* 4 serializer */ 556 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 557 1 2 0 0 558 >; 559 tx-num-evt = <32>; 560 rx-num-evt = <32>; 561}; 562 563&mailbox5 { 564 status = "okay"; 565 mbox_ipu1_ipc3x: mbox_ipu1_ipc3x { 566 status = "okay"; 567 }; 568 mbox_dsp1_ipc3x: mbox_dsp1_ipc3x { 569 status = "okay"; 570 }; 571}; 572 573&mailbox6 { 574 status = "okay"; 575 mbox_ipu2_ipc3x: mbox_ipu2_ipc3x { 576 status = "okay"; 577 }; 578}; 579 580&pcie1_rc { 581 status = "okay"; 582}; 583
