1#include <dt-bindings/pinctrl/bcm2835.h>
2#include <dt-bindings/clock/bcm2835.h>
3#include <dt-bindings/clock/bcm2835-aux.h>
4#include <dt-bindings/gpio/gpio.h>
5#include <dt-bindings/interrupt-controller/irq.h>
6#include <dt-bindings/soc/bcm2835-pm.h>
7
8/* firmware-provided startup stubs live here, where the secondary CPUs are
9 * spinning.
10 */
11/memreserve/ 0x00000000 0x00001000;
12
13/* This include file covers the common peripherals and configuration between
14 * bcm2835 and bcm2836 implementations, leaving the CPU configuration to
15 * bcm2835.dtsi and bcm2836.dtsi.
16 */
17
18/ {
19	compatible = "brcm,bcm2835";
20	model = "BCM2835";
21	interrupt-parent = <&intc>;
22	#address-cells = <1>;
23	#size-cells = <1>;
24
25	aliases {
26		serial0 = &uart0;
27		serial1 = &uart1;
28	};
29
30	chosen {
31		stdout-path = "serial0:115200n8";
32	};
33
34	thermal-zones {
35		cpu_thermal: cpu-thermal {
36			polling-delay-passive = <0>;
37			polling-delay = <1000>;
38
39			thermal-sensors = <&thermal>;
40
41			trips {
42				cpu-crit {
43					temperature	= <80000>;
44					hysteresis	= <0>;
45					type		= "critical";
46				};
47			};
48
49			cooling-maps {
50			};
51		};
52	};
53
54	soc {
55		compatible = "simple-bus";
56		#address-cells = <1>;
57		#size-cells = <1>;
58
59		timer@7e003000 {
60			compatible = "brcm,bcm2835-system-timer";
61			reg = <0x7e003000 0x1000>;
62			interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
63			/* This could be a reference to BCM2835_CLOCK_TIMER,
64			 * but we don't have the driver using the common clock
65			 * support yet.
66			 */
67			clock-frequency = <1000000>;
68		};
69
70		txp@7e004000 {
71			compatible = "brcm,bcm2835-txp";
72			reg = <0x7e004000 0x20>;
73			interrupts = <1 11>;
74		};
75
76		dma: dma@7e007000 {
77			compatible = "brcm,bcm2835-dma";
78			reg = <0x7e007000 0xf00>;
79			interrupts = <1 16>,
80				     <1 17>,
81				     <1 18>,
82				     <1 19>,
83				     <1 20>,
84				     <1 21>,
85				     <1 22>,
86				     <1 23>,
87				     <1 24>,
88				     <1 25>,
89				     <1 26>,
90				     /* dma channel 11-14 share one irq */
91				     <1 27>,
92				     <1 27>,
93				     <1 27>,
94				     <1 27>,
95				     /* unused shared irq for all channels */
96				     <1 28>;
97			interrupt-names = "dma0",
98					  "dma1",
99					  "dma2",
100					  "dma3",
101					  "dma4",
102					  "dma5",
103					  "dma6",
104					  "dma7",
105					  "dma8",
106					  "dma9",
107					  "dma10",
108					  "dma11",
109					  "dma12",
110					  "dma13",
111					  "dma14",
112					  "dma-shared-all";
113			#dma-cells = <1>;
114			brcm,dma-channel-mask = <0x7f35>;
115		};
116
117		intc: interrupt-controller@7e00b200 {
118			compatible = "brcm,bcm2835-armctrl-ic";
119			reg = <0x7e00b200 0x200>;
120			interrupt-controller;
121			#interrupt-cells = <2>;
122		};
123
124		pm: watchdog@7e100000 {
125			compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
126			#power-domain-cells = <1>;
127			#reset-cells = <1>;
128			reg = <0x7e100000 0x114>,
129			      <0x7e00a000 0x24>;
130			clocks = <&clocks BCM2835_CLOCK_V3D>,
131				 <&clocks BCM2835_CLOCK_PERI_IMAGE>,
132				 <&clocks BCM2835_CLOCK_H264>,
133				 <&clocks BCM2835_CLOCK_ISP>;
134			clock-names = "v3d", "peri_image", "h264", "isp";
135			system-power-controller;
136		};
137
138		clocks: cprman@7e101000 {
139			compatible = "brcm,bcm2835-cprman";
140			#clock-cells = <1>;
141			reg = <0x7e101000 0x2000>;
142
143			/* CPRMAN derives almost everything from the
144			 * platform's oscillator.  However, the DSI
145			 * pixel clocks come from the DSI analog PHY.
146			 */
147			clocks = <&clk_osc>,
148				<&dsi0 0>, <&dsi0 1>, <&dsi0 2>,
149				<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
150		};
151
152		rng@7e104000 {
153			compatible = "brcm,bcm2835-rng";
154			reg = <0x7e104000 0x10>;
155			interrupts = <2 29>;
156		};
157
158		mailbox: mailbox@7e00b880 {
159			compatible = "brcm,bcm2835-mbox";
160			reg = <0x7e00b880 0x40>;
161			interrupts = <0 1>;
162			#mbox-cells = <0>;
163		};
164
165		gpio: gpio@7e200000 {
166			compatible = "brcm,bcm2835-gpio";
167			reg = <0x7e200000 0xb4>;
168			/*
169			 * The GPIO IP block is designed for 3 banks of GPIOs.
170			 * Each bank has a GPIO interrupt for itself.
171			 * There is an overall "any bank" interrupt.
172			 * In order, these are GIC interrupts 17, 18, 19, 20.
173			 * Since the BCM2835 only has 2 banks, the 2nd bank
174			 * interrupt output appears to be mirrored onto the
175			 * 3rd bank's interrupt signal.
176			 * So, a bank0 interrupt shows up on 17, 20, and
177			 * a bank1 interrupt shows up on 18, 19, 20!
178			 */
179			interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
180
181			gpio-controller;
182			#gpio-cells = <2>;
183
184			interrupt-controller;
185			#interrupt-cells = <2>;
186
187			/* Defines pin muxing groups according to
188			 * BCM2835-ARM-Peripherals.pdf page 102.
189			 *
190			 * While each pin can have its mux selected
191			 * for various functions individually, some
192			 * groups only make sense to switch to a
193			 * particular function together.
194			 */
195			dpi_gpio0: dpi_gpio0 {
196				brcm,pins = <0 1 2 3 4 5 6 7 8 9 10 11
197					     12 13 14 15 16 17 18 19
198					     20 21 22 23 24 25 26 27>;
199				brcm,function = <BCM2835_FSEL_ALT2>;
200			};
201			emmc_gpio22: emmc_gpio22 {
202				brcm,pins = <22 23 24 25 26 27>;
203				brcm,function = <BCM2835_FSEL_ALT3>;
204			};
205			emmc_gpio34: emmc_gpio34 {
206				brcm,pins = <34 35 36 37 38 39>;
207				brcm,function = <BCM2835_FSEL_ALT3>;
208				brcm,pull = <BCM2835_PUD_OFF
209					     BCM2835_PUD_UP
210					     BCM2835_PUD_UP
211					     BCM2835_PUD_UP
212					     BCM2835_PUD_UP
213					     BCM2835_PUD_UP>;
214			};
215			emmc_gpio48: emmc_gpio48 {
216				brcm,pins = <48 49 50 51 52 53>;
217				brcm,function = <BCM2835_FSEL_ALT3>;
218			};
219
220			gpclk0_gpio4: gpclk0_gpio4 {
221				brcm,pins = <4>;
222				brcm,function = <BCM2835_FSEL_ALT0>;
223			};
224			gpclk1_gpio5: gpclk1_gpio5 {
225				brcm,pins = <5>;
226				brcm,function = <BCM2835_FSEL_ALT0>;
227			};
228			gpclk1_gpio42: gpclk1_gpio42 {
229				brcm,pins = <42>;
230				brcm,function = <BCM2835_FSEL_ALT0>;
231			};
232			gpclk1_gpio44: gpclk1_gpio44 {
233				brcm,pins = <44>;
234				brcm,function = <BCM2835_FSEL_ALT0>;
235			};
236			gpclk2_gpio6: gpclk2_gpio6 {
237				brcm,pins = <6>;
238				brcm,function = <BCM2835_FSEL_ALT0>;
239			};
240			gpclk2_gpio43: gpclk2_gpio43 {
241				brcm,pins = <43>;
242				brcm,function = <BCM2835_FSEL_ALT0>;
243				brcm,pull = <BCM2835_PUD_OFF>;
244			};
245
246			i2c0_gpio0: i2c0_gpio0 {
247				brcm,pins = <0 1>;
248				brcm,function = <BCM2835_FSEL_ALT0>;
249			};
250			i2c0_gpio28: i2c0_gpio28 {
251				brcm,pins = <28 29>;
252				brcm,function = <BCM2835_FSEL_ALT0>;
253			};
254			i2c0_gpio44: i2c0_gpio44 {
255				brcm,pins = <44 45>;
256				brcm,function = <BCM2835_FSEL_ALT1>;
257			};
258			i2c1_gpio2: i2c1_gpio2 {
259				brcm,pins = <2 3>;
260				brcm,function = <BCM2835_FSEL_ALT0>;
261			};
262			i2c1_gpio44: i2c1_gpio44 {
263				brcm,pins = <44 45>;
264				brcm,function = <BCM2835_FSEL_ALT2>;
265			};
266			i2c_slave_gpio18: i2c_slave_gpio18 {
267				brcm,pins = <18 19 20 21>;
268				brcm,function = <BCM2835_FSEL_ALT3>;
269			};
270
271			jtag_gpio4: jtag_gpio4 {
272				brcm,pins = <4 5 6 12 13>;
273				brcm,function = <BCM2835_FSEL_ALT5>;
274			};
275			jtag_gpio22: jtag_gpio22 {
276				brcm,pins = <22 23 24 25 26 27>;
277				brcm,function = <BCM2835_FSEL_ALT4>;
278			};
279
280			pcm_gpio18: pcm_gpio18 {
281				brcm,pins = <18 19 20 21>;
282				brcm,function = <BCM2835_FSEL_ALT0>;
283			};
284			pcm_gpio28: pcm_gpio28 {
285				brcm,pins = <28 29 30 31>;
286				brcm,function = <BCM2835_FSEL_ALT2>;
287			};
288
289			pwm0_gpio12: pwm0_gpio12 {
290				brcm,pins = <12>;
291				brcm,function = <BCM2835_FSEL_ALT0>;
292			};
293			pwm0_gpio18: pwm0_gpio18 {
294				brcm,pins = <18>;
295				brcm,function = <BCM2835_FSEL_ALT5>;
296			};
297			pwm0_gpio40: pwm0_gpio40 {
298				brcm,pins = <40>;
299				brcm,function = <BCM2835_FSEL_ALT0>;
300			};
301			pwm1_gpio13: pwm1_gpio13 {
302				brcm,pins = <13>;
303				brcm,function = <BCM2835_FSEL_ALT0>;
304			};
305			pwm1_gpio19: pwm1_gpio19 {
306				brcm,pins = <19>;
307				brcm,function = <BCM2835_FSEL_ALT5>;
308			};
309			pwm1_gpio41: pwm1_gpio41 {
310				brcm,pins = <41>;
311				brcm,function = <BCM2835_FSEL_ALT0>;
312			};
313			pwm1_gpio45: pwm1_gpio45 {
314				brcm,pins = <45>;
315				brcm,function = <BCM2835_FSEL_ALT0>;
316			};
317
318			sdhost_gpio48: sdhost_gpio48 {
319				brcm,pins = <48 49 50 51 52 53>;
320				brcm,function = <BCM2835_FSEL_ALT0>;
321			};
322
323			spi0_gpio7: spi0_gpio7 {
324				brcm,pins = <7 8 9 10 11>;
325				brcm,function = <BCM2835_FSEL_ALT0>;
326			};
327			spi0_gpio35: spi0_gpio35 {
328				brcm,pins = <35 36 37 38 39>;
329				brcm,function = <BCM2835_FSEL_ALT0>;
330			};
331			spi1_gpio16: spi1_gpio16 {
332				brcm,pins = <16 17 18 19 20 21>;
333				brcm,function = <BCM2835_FSEL_ALT4>;
334			};
335			spi2_gpio40: spi2_gpio40 {
336				brcm,pins = <40 41 42 43 44 45>;
337				brcm,function = <BCM2835_FSEL_ALT4>;
338			};
339
340			uart0_gpio14: uart0_gpio14 {
341				brcm,pins = <14 15>;
342				brcm,function = <BCM2835_FSEL_ALT0>;
343			};
344			/* Separate from the uart0_gpio14 group
345			 * because it conflicts with spi1_gpio16, and
346			 * people often run uart0 on the two pins
347			 * without flow control.
348			 */
349			uart0_ctsrts_gpio16: uart0_ctsrts_gpio16 {
350				brcm,pins = <16 17>;
351				brcm,function = <BCM2835_FSEL_ALT3>;
352			};
353			uart0_ctsrts_gpio30: uart0_ctsrts_gpio30 {
354				brcm,pins = <30 31>;
355				brcm,function = <BCM2835_FSEL_ALT3>;
356				brcm,pull = <BCM2835_PUD_UP BCM2835_PUD_OFF>;
357			};
358			uart0_gpio32: uart0_gpio32 {
359				brcm,pins = <32 33>;
360				brcm,function = <BCM2835_FSEL_ALT3>;
361				brcm,pull = <BCM2835_PUD_OFF BCM2835_PUD_UP>;
362			};
363			uart0_gpio36: uart0_gpio36 {
364				brcm,pins = <36 37>;
365				brcm,function = <BCM2835_FSEL_ALT2>;
366			};
367			uart0_ctsrts_gpio38: uart0_ctsrts_gpio38 {
368				brcm,pins = <38 39>;
369				brcm,function = <BCM2835_FSEL_ALT2>;
370			};
371
372			uart1_gpio14: uart1_gpio14 {
373				brcm,pins = <14 15>;
374				brcm,function = <BCM2835_FSEL_ALT5>;
375			};
376			uart1_ctsrts_gpio16: uart1_ctsrts_gpio16 {
377				brcm,pins = <16 17>;
378				brcm,function = <BCM2835_FSEL_ALT5>;
379			};
380			uart1_gpio32: uart1_gpio32 {
381				brcm,pins = <32 33>;
382				brcm,function = <BCM2835_FSEL_ALT5>;
383			};
384			uart1_ctsrts_gpio30: uart1_ctsrts_gpio30 {
385				brcm,pins = <30 31>;
386				brcm,function = <BCM2835_FSEL_ALT5>;
387			};
388			uart1_gpio40: uart1_gpio40 {
389				brcm,pins = <40 41>;
390				brcm,function = <BCM2835_FSEL_ALT5>;
391			};
392			uart1_ctsrts_gpio42: uart1_ctsrts_gpio42 {
393				brcm,pins = <42 43>;
394				brcm,function = <BCM2835_FSEL_ALT5>;
395			};
396		};
397
398		uart0: serial@7e201000 {
399			compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
400			reg = <0x7e201000 0x200>;
401			interrupts = <2 25>;
402			clocks = <&clocks BCM2835_CLOCK_UART>,
403				 <&clocks BCM2835_CLOCK_VPU>;
404			clock-names = "uartclk", "apb_pclk";
405			arm,primecell-periphid = <0x00241011>;
406		};
407
408		sdhost: mmc@7e202000 {
409			compatible = "brcm,bcm2835-sdhost";
410			reg = <0x7e202000 0x100>;
411			interrupts = <2 24>;
412			clocks = <&clocks BCM2835_CLOCK_VPU>;
413			dmas = <&dma 13>;
414			dma-names = "rx-tx";
415			status = "disabled";
416		};
417
418		i2s: i2s@7e203000 {
419			compatible = "brcm,bcm2835-i2s";
420			reg = <0x7e203000 0x24>;
421			clocks = <&clocks BCM2835_CLOCK_PCM>;
422
423			dmas = <&dma 2>,
424			       <&dma 3>;
425			dma-names = "tx", "rx";
426			status = "disabled";
427		};
428
429		spi: spi@7e204000 {
430			compatible = "brcm,bcm2835-spi";
431			reg = <0x7e204000 0x200>;
432			interrupts = <2 22>;
433			clocks = <&clocks BCM2835_CLOCK_VPU>;
434			dmas = <&dma 6>, <&dma 7>;
435			dma-names = "tx", "rx";
436			#address-cells = <1>;
437			#size-cells = <0>;
438			status = "disabled";
439		};
440
441		i2c0: i2c@7e205000 {
442			compatible = "brcm,bcm2835-i2c";
443			reg = <0x7e205000 0x200>;
444			interrupts = <2 21>;
445			clocks = <&clocks BCM2835_CLOCK_VPU>;
446			#address-cells = <1>;
447			#size-cells = <0>;
448			status = "disabled";
449		};
450
451		pixelvalve@7e206000 {
452			compatible = "brcm,bcm2835-pixelvalve0";
453			reg = <0x7e206000 0x100>;
454			interrupts = <2 13>; /* pwa0 */
455		};
456
457		pixelvalve@7e207000 {
458			compatible = "brcm,bcm2835-pixelvalve1";
459			reg = <0x7e207000 0x100>;
460			interrupts = <2 14>; /* pwa1 */
461		};
462
463		dpi: dpi@7e208000 {
464			compatible = "brcm,bcm2835-dpi";
465			reg = <0x7e208000 0x8c>;
466			clocks = <&clocks BCM2835_CLOCK_VPU>,
467				 <&clocks BCM2835_CLOCK_DPI>;
468			clock-names = "core", "pixel";
469			#address-cells = <1>;
470			#size-cells = <0>;
471			status = "disabled";
472		};
473
474		dsi0: dsi@7e209000 {
475			compatible = "brcm,bcm2835-dsi0";
476			reg = <0x7e209000 0x78>;
477			interrupts = <2 4>;
478			#address-cells = <1>;
479			#size-cells = <0>;
480			#clock-cells = <1>;
481
482			clocks = <&clocks BCM2835_PLLA_DSI0>,
483				 <&clocks BCM2835_CLOCK_DSI0E>,
484				 <&clocks BCM2835_CLOCK_DSI0P>;
485			clock-names = "phy", "escape", "pixel";
486
487			clock-output-names = "dsi0_byte",
488					     "dsi0_ddr2",
489					     "dsi0_ddr";
490
491		};
492
493		thermal: thermal@7e212000 {
494			compatible = "brcm,bcm2835-thermal";
495			reg = <0x7e212000 0x8>;
496			clocks = <&clocks BCM2835_CLOCK_TSENS>;
497			#thermal-sensor-cells = <0>;
498			status = "disabled";
499		};
500
501		aux: aux@7e215000 {
502			compatible = "brcm,bcm2835-aux";
503			#clock-cells = <1>;
504			reg = <0x7e215000 0x8>;
505			clocks = <&clocks BCM2835_CLOCK_VPU>;
506		};
507
508		uart1: serial@7e215040 {
509			compatible = "brcm,bcm2835-aux-uart";
510			reg = <0x7e215040 0x40>;
511			interrupts = <1 29>;
512			clocks = <&aux BCM2835_AUX_CLOCK_UART>;
513			status = "disabled";
514		};
515
516		spi1: spi@7e215080 {
517			compatible = "brcm,bcm2835-aux-spi";
518			reg = <0x7e215080 0x40>;
519			interrupts = <1 29>;
520			clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
521			#address-cells = <1>;
522			#size-cells = <0>;
523			status = "disabled";
524		};
525
526		spi2: spi@7e2150c0 {
527			compatible = "brcm,bcm2835-aux-spi";
528			reg = <0x7e2150c0 0x40>;
529			interrupts = <1 29>;
530			clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
531			#address-cells = <1>;
532			#size-cells = <0>;
533			status = "disabled";
534		};
535
536		pwm: pwm@7e20c000 {
537			compatible = "brcm,bcm2835-pwm";
538			reg = <0x7e20c000 0x28>;
539			clocks = <&clocks BCM2835_CLOCK_PWM>;
540			assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
541			assigned-clock-rates = <10000000>;
542			#pwm-cells = <2>;
543			status = "disabled";
544		};
545
546		sdhci: sdhci@7e300000 {
547			compatible = "brcm,bcm2835-sdhci";
548			reg = <0x7e300000 0x100>;
549			interrupts = <2 30>;
550			clocks = <&clocks BCM2835_CLOCK_EMMC>;
551			status = "disabled";
552		};
553
554		hvs@7e400000 {
555			compatible = "brcm,bcm2835-hvs";
556			reg = <0x7e400000 0x6000>;
557			interrupts = <2 1>;
558		};
559
560		dsi1: dsi@7e700000 {
561			compatible = "brcm,bcm2835-dsi1";
562			reg = <0x7e700000 0x8c>;
563			interrupts = <2 12>;
564			#address-cells = <1>;
565			#size-cells = <0>;
566			#clock-cells = <1>;
567
568			clocks = <&clocks BCM2835_PLLD_DSI1>,
569				 <&clocks BCM2835_CLOCK_DSI1E>,
570				 <&clocks BCM2835_CLOCK_DSI1P>;
571			clock-names = "phy", "escape", "pixel";
572
573			clock-output-names = "dsi1_byte",
574					     "dsi1_ddr2",
575					     "dsi1_ddr";
576
577			status = "disabled";
578		};
579
580		i2c1: i2c@7e804000 {
581			compatible = "brcm,bcm2835-i2c";
582			reg = <0x7e804000 0x1000>;
583			interrupts = <2 21>;
584			clocks = <&clocks BCM2835_CLOCK_VPU>;
585			#address-cells = <1>;
586			#size-cells = <0>;
587			status = "disabled";
588		};
589
590		i2c2: i2c@7e805000 {
591			compatible = "brcm,bcm2835-i2c";
592			reg = <0x7e805000 0x1000>;
593			interrupts = <2 21>;
594			clocks = <&clocks BCM2835_CLOCK_VPU>;
595			#address-cells = <1>;
596			#size-cells = <0>;
597			status = "disabled";
598		};
599
600		vec: vec@7e806000 {
601			compatible = "brcm,bcm2835-vec";
602			reg = <0x7e806000 0x1000>;
603			clocks = <&clocks BCM2835_CLOCK_VEC>;
604			interrupts = <2 27>;
605			status = "disabled";
606		};
607
608		pixelvalve@7e807000 {
609			compatible = "brcm,bcm2835-pixelvalve2";
610			reg = <0x7e807000 0x100>;
611			interrupts = <2 10>; /* pixelvalve */
612		};
613
614		hdmi: hdmi@7e902000 {
615			compatible = "brcm,bcm2835-hdmi";
616			reg = <0x7e902000 0x600>,
617			      <0x7e808000 0x100>;
618			interrupts = <2 8>, <2 9>;
619			ddc = <&i2c2>;
620			clocks = <&clocks BCM2835_PLLH_PIX>,
621				 <&clocks BCM2835_CLOCK_HSM>;
622			clock-names = "pixel", "hdmi";
623			dmas = <&dma 17>;
624			dma-names = "audio-rx";
625			status = "disabled";
626		};
627
628		usb: usb@7e980000 {
629			compatible = "brcm,bcm2835-usb";
630			reg = <0x7e980000 0x10000>;
631			interrupts = <1 9>;
632			#address-cells = <1>;
633			#size-cells = <0>;
634			clocks = <&clk_usb>;
635			clock-names = "otg";
636			phys = <&usbphy>;
637			phy-names = "usb2-phy";
638		};
639
640		v3d: v3d@7ec00000 {
641			compatible = "brcm,bcm2835-v3d";
642			reg = <0x7ec00000 0x1000>;
643			interrupts = <1 10>;
644			power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
645		};
646
647		vc4: gpu {
648			compatible = "brcm,bcm2835-vc4";
649		};
650	};
651
652	clocks {
653		compatible = "simple-bus";
654		#address-cells = <1>;
655		#size-cells = <0>;
656
657		/* The oscillator is the root of the clock tree. */
658		clk_osc: clock@3 {
659			compatible = "fixed-clock";
660			reg = <3>;
661			#clock-cells = <0>;
662			clock-output-names = "osc";
663			clock-frequency = <19200000>;
664		};
665
666		clk_usb: clock@4 {
667			compatible = "fixed-clock";
668			reg = <4>;
669			#clock-cells = <0>;
670			clock-output-names = "otg";
671			clock-frequency = <480000000>;
672		};
673	};
674
675	usbphy: phy {
676		compatible = "usb-nop-xceiv";
677		#phy-cells = <0>;
678	};
679};
680