1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * at91rm9200.dtsi - Device Tree Include file for AT91RM9200 family SoC 4 * 5 * Copyright (C) 2011 Atmel, 6 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>, 7 * 2012 Joachim Eastwood <manabian@gmail.com> 8 * 9 * Based on at91sam9260.dtsi 10 */ 11 12#include <dt-bindings/pinctrl/at91.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/gpio/gpio.h> 15#include <dt-bindings/clock/at91.h> 16 17/ { 18 #address-cells = <1>; 19 #size-cells = <1>; 20 model = "Atmel AT91RM9200 family SoC"; 21 compatible = "atmel,at91rm9200"; 22 interrupt-parent = <&aic>; 23 24 aliases { 25 serial0 = &dbgu; 26 serial1 = &usart0; 27 serial2 = &usart1; 28 serial3 = &usart2; 29 serial4 = &usart3; 30 gpio0 = &pioA; 31 gpio1 = &pioB; 32 gpio2 = &pioC; 33 gpio3 = &pioD; 34 tcb0 = &tcb0; 35 tcb1 = &tcb1; 36 i2c0 = &i2c0; 37 ssc0 = &ssc0; 38 ssc1 = &ssc1; 39 ssc2 = &ssc2; 40 }; 41 cpus { 42 #address-cells = <0>; 43 #size-cells = <0>; 44 45 cpu { 46 compatible = "arm,arm920t"; 47 device_type = "cpu"; 48 }; 49 }; 50 51 memory { 52 device_type = "memory"; 53 reg = <0x20000000 0x04000000>; 54 }; 55 56 clocks { 57 slow_xtal: slow_xtal { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <0>; 61 }; 62 63 main_xtal: main_xtal { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <0>; 67 }; 68 }; 69 70 sram: sram@200000 { 71 compatible = "mmio-sram"; 72 reg = <0x00200000 0x4000>; 73 }; 74 75 ahb { 76 compatible = "simple-bus"; 77 #address-cells = <1>; 78 #size-cells = <1>; 79 ranges; 80 81 apb { 82 compatible = "simple-bus"; 83 #address-cells = <1>; 84 #size-cells = <1>; 85 ranges; 86 87 aic: interrupt-controller@fffff000 { 88 #interrupt-cells = <3>; 89 compatible = "atmel,at91rm9200-aic"; 90 interrupt-controller; 91 reg = <0xfffff000 0x200>; 92 atmel,external-irqs = <25 26 27 28 29 30 31>; 93 }; 94 95 ramc0: ramc@ffffff00 { 96 compatible = "atmel,at91rm9200-sdramc", "syscon"; 97 reg = <0xffffff00 0x100>; 98 }; 99 100 pmc: pmc@fffffc00 { 101 compatible = "atmel,at91rm9200-pmc", "syscon"; 102 reg = <0xfffffc00 0x100>; 103 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 104 interrupt-controller; 105 #address-cells = <1>; 106 #size-cells = <0>; 107 #interrupt-cells = <1>; 108 109 main_osc: main_osc { 110 compatible = "atmel,at91rm9200-clk-main-osc"; 111 #clock-cells = <0>; 112 interrupts-extended = <&pmc AT91_PMC_MOSCS>; 113 clocks = <&main_xtal>; 114 }; 115 116 main: mainck { 117 compatible = "atmel,at91rm9200-clk-main"; 118 #clock-cells = <0>; 119 clocks = <&main_osc>; 120 }; 121 122 plla: pllack { 123 compatible = "atmel,at91rm9200-clk-pll"; 124 #clock-cells = <0>; 125 interrupts-extended = <&pmc AT91_PMC_LOCKA>; 126 clocks = <&main>; 127 reg = <0>; 128 atmel,clk-input-range = <1000000 32000000>; 129 #atmel,pll-clk-output-range-cells = <3>; 130 atmel,pll-clk-output-ranges = <80000000 160000000 0>, 131 <150000000 180000000 2>; 132 }; 133 134 pllb: pllbck { 135 compatible = "atmel,at91rm9200-clk-pll"; 136 #clock-cells = <0>; 137 interrupts-extended = <&pmc AT91_PMC_LOCKB>; 138 clocks = <&main>; 139 reg = <1>; 140 atmel,clk-input-range = <1000000 32000000>; 141 #atmel,pll-clk-output-range-cells = <3>; 142 atmel,pll-clk-output-ranges = <80000000 160000000 0>, 143 <150000000 180000000 2>; 144 }; 145 146 mck: masterck { 147 compatible = "atmel,at91rm9200-clk-master"; 148 #clock-cells = <0>; 149 interrupts-extended = <&pmc AT91_PMC_MCKRDY>; 150 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; 151 atmel,clk-output-range = <0 80000000>; 152 atmel,clk-divisors = <1 2 3 4>; 153 }; 154 155 usb: usbck { 156 compatible = "atmel,at91rm9200-clk-usb"; 157 #clock-cells = <0>; 158 atmel,clk-divisors = <1 2 0 0>; 159 clocks = <&pllb>; 160 }; 161 162 prog: progck { 163 compatible = "atmel,at91rm9200-clk-programmable"; 164 #address-cells = <1>; 165 #size-cells = <0>; 166 interrupt-parent = <&pmc>; 167 clocks = <&slow_xtal>, <&main>, <&plla>, <&pllb>; 168 169 prog0: prog0 { 170 #clock-cells = <0>; 171 reg = <0>; 172 interrupts = <AT91_PMC_PCKRDY(0)>; 173 }; 174 175 prog1: prog1 { 176 #clock-cells = <0>; 177 reg = <1>; 178 interrupts = <AT91_PMC_PCKRDY(1)>; 179 }; 180 181 prog2: prog2 { 182 #clock-cells = <0>; 183 reg = <2>; 184 interrupts = <AT91_PMC_PCKRDY(2)>; 185 }; 186 187 prog3: prog3 { 188 #clock-cells = <0>; 189 reg = <3>; 190 interrupts = <AT91_PMC_PCKRDY(3)>; 191 }; 192 }; 193 194 systemck { 195 compatible = "atmel,at91rm9200-clk-system"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 199 udpck: udpck { 200 #clock-cells = <0>; 201 reg = <2>; 202 clocks = <&usb>; 203 }; 204 205 uhpck: uhpck { 206 #clock-cells = <0>; 207 reg = <4>; 208 clocks = <&usb>; 209 }; 210 211 pck0: pck0 { 212 #clock-cells = <0>; 213 reg = <8>; 214 clocks = <&prog0>; 215 }; 216 217 pck1: pck1 { 218 #clock-cells = <0>; 219 reg = <9>; 220 clocks = <&prog1>; 221 }; 222 223 pck2: pck2 { 224 #clock-cells = <0>; 225 reg = <10>; 226 clocks = <&prog2>; 227 }; 228 229 pck3: pck3 { 230 #clock-cells = <0>; 231 reg = <11>; 232 clocks = <&prog3>; 233 }; 234 }; 235 236 periphck { 237 compatible = "atmel,at91rm9200-clk-peripheral"; 238 #address-cells = <1>; 239 #size-cells = <0>; 240 clocks = <&mck>; 241 242 pioA_clk: pioA_clk { 243 #clock-cells = <0>; 244 reg = <2>; 245 }; 246 247 pioB_clk: pioB_clk { 248 #clock-cells = <0>; 249 reg = <3>; 250 }; 251 252 pioC_clk: pioC_clk { 253 #clock-cells = <0>; 254 reg = <4>; 255 }; 256 257 pioD_clk: pioD_clk { 258 #clock-cells = <0>; 259 reg = <5>; 260 }; 261 262 usart0_clk: usart0_clk { 263 #clock-cells = <0>; 264 reg = <6>; 265 }; 266 267 usart1_clk: usart1_clk { 268 #clock-cells = <0>; 269 reg = <7>; 270 }; 271 272 usart2_clk: usart2_clk { 273 #clock-cells = <0>; 274 reg = <8>; 275 }; 276 277 usart3_clk: usart3_clk { 278 #clock-cells = <0>; 279 reg = <9>; 280 }; 281 282 mci0_clk: mci0_clk { 283 #clock-cells = <0>; 284 reg = <10>; 285 }; 286 287 udc_clk: udc_clk { 288 #clock-cells = <0>; 289 reg = <11>; 290 }; 291 292 twi0_clk: twi0_clk { 293 reg = <12>; 294 #clock-cells = <0>; 295 }; 296 297 spi0_clk: spi0_clk { 298 #clock-cells = <0>; 299 reg = <13>; 300 }; 301 302 ssc0_clk: ssc0_clk { 303 #clock-cells = <0>; 304 reg = <14>; 305 }; 306 307 ssc1_clk: ssc1_clk { 308 #clock-cells = <0>; 309 reg = <15>; 310 }; 311 312 ssc2_clk: ssc2_clk { 313 #clock-cells = <0>; 314 reg = <16>; 315 }; 316 317 tc0_clk: tc0_clk { 318 #clock-cells = <0>; 319 reg = <17>; 320 }; 321 322 tc1_clk: tc1_clk { 323 #clock-cells = <0>; 324 reg = <18>; 325 }; 326 327 tc2_clk: tc2_clk { 328 #clock-cells = <0>; 329 reg = <19>; 330 }; 331 332 tc3_clk: tc3_clk { 333 #clock-cells = <0>; 334 reg = <20>; 335 }; 336 337 tc4_clk: tc4_clk { 338 #clock-cells = <0>; 339 reg = <21>; 340 }; 341 342 tc5_clk: tc5_clk { 343 #clock-cells = <0>; 344 reg = <22>; 345 }; 346 347 ohci_clk: ohci_clk { 348 #clock-cells = <0>; 349 reg = <23>; 350 }; 351 352 macb0_clk: macb0_clk { 353 #clock-cells = <0>; 354 reg = <24>; 355 }; 356 }; 357 }; 358 359 st: timer@fffffd00 { 360 compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; 361 reg = <0xfffffd00 0x100>; 362 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 363 clocks = <&slow_xtal>; 364 365 watchdog { 366 compatible = "atmel,at91rm9200-wdt"; 367 }; 368 }; 369 370 rtc: rtc@fffffe00 { 371 compatible = "atmel,at91rm9200-rtc"; 372 reg = <0xfffffe00 0x40>; 373 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 374 clocks = <&slow_xtal>; 375 status = "disabled"; 376 }; 377 378 tcb0: timer@fffa0000 { 379 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 380 #address-cells = <1>; 381 #size-cells = <0>; 382 reg = <0xfffa0000 0x100>; 383 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0 384 18 IRQ_TYPE_LEVEL_HIGH 0 385 19 IRQ_TYPE_LEVEL_HIGH 0>; 386 clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&slow_xtal>; 387 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 388 }; 389 390 tcb1: timer@fffa4000 { 391 compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 reg = <0xfffa4000 0x100>; 395 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0 396 21 IRQ_TYPE_LEVEL_HIGH 0 397 22 IRQ_TYPE_LEVEL_HIGH 0>; 398 clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&slow_xtal>; 399 clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk"; 400 }; 401 402 i2c0: i2c@fffb8000 { 403 compatible = "atmel,at91rm9200-i2c"; 404 reg = <0xfffb8000 0x4000>; 405 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>; 406 pinctrl-names = "default"; 407 pinctrl-0 = <&pinctrl_twi>; 408 clocks = <&twi0_clk>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 mmc0: mmc@fffb4000 { 415 compatible = "atmel,hsmci"; 416 reg = <0xfffb4000 0x4000>; 417 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>; 418 clocks = <&mci0_clk>; 419 clock-names = "mci_clk"; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 pinctrl-names = "default"; 423 status = "disabled"; 424 }; 425 426 ssc0: ssc@fffd0000 { 427 compatible = "atmel,at91rm9200-ssc"; 428 reg = <0xfffd0000 0x4000>; 429 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; 432 clocks = <&ssc0_clk>; 433 clock-names = "pclk"; 434 status = "disabled"; 435 }; 436 437 ssc1: ssc@fffd4000 { 438 compatible = "atmel,at91rm9200-ssc"; 439 reg = <0xfffd4000 0x4000>; 440 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; 441 pinctrl-names = "default"; 442 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; 443 clocks = <&ssc1_clk>; 444 clock-names = "pclk"; 445 status = "disabled"; 446 }; 447 448 ssc2: ssc@fffd8000 { 449 compatible = "atmel,at91rm9200-ssc"; 450 reg = <0xfffd8000 0x4000>; 451 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>; 452 pinctrl-names = "default"; 453 pinctrl-0 = <&pinctrl_ssc2_tx &pinctrl_ssc2_rx>; 454 clocks = <&ssc2_clk>; 455 clock-names = "pclk"; 456 status = "disabled"; 457 }; 458 459 macb0: ethernet@fffbc000 { 460 compatible = "cdns,at91rm9200-emac", "cdns,emac"; 461 reg = <0xfffbc000 0x4000>; 462 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; 463 phy-mode = "rmii"; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&pinctrl_macb_rmii>; 466 clocks = <&macb0_clk>; 467 clock-names = "ether_clk"; 468 status = "disabled"; 469 }; 470 471 pinctrl@fffff400 { 472 #address-cells = <1>; 473 #size-cells = <1>; 474 compatible = "atmel,at91rm9200-pinctrl", "simple-bus"; 475 ranges = <0xfffff400 0xfffff400 0x800>; 476 477 atmel,mux-mask = < 478 /* A B */ 479 0xffffffff 0xffffffff /* pioA */ 480 0xffffffff 0x083fffff /* pioB */ 481 0xffff3fff 0x00000000 /* pioC */ 482 0x03ff87ff 0x0fffff80 /* pioD */ 483 >; 484 485 /* shared pinctrl settings */ 486 dbgu { 487 pinctrl_dbgu: dbgu-0 { 488 atmel,pins = 489 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 490 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; 491 }; 492 }; 493 494 uart0 { 495 pinctrl_uart0: uart0-0 { 496 atmel,pins = 497 <AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE 498 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 499 }; 500 501 pinctrl_uart0_cts: uart0_cts-0 { 502 atmel,pins = 503 <AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA20 periph A */ 504 }; 505 506 pinctrl_uart0_rts: uart0_rts-0 { 507 atmel,pins = 508 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA21 periph A */ 509 }; 510 }; 511 512 uart1 { 513 pinctrl_uart1: uart1-0 { 514 atmel,pins = 515 <AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE 516 AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; 517 }; 518 519 pinctrl_uart1_rts: uart1_rts-0 { 520 atmel,pins = 521 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB24 periph A */ 522 }; 523 524 pinctrl_uart1_cts: uart1_cts-0 { 525 atmel,pins = 526 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB26 periph A */ 527 }; 528 529 pinctrl_uart1_dtr_dsr: uart1_dtr_dsr-0 { 530 atmel,pins = 531 <AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB19 periph A */ 532 AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB25 periph A */ 533 }; 534 535 pinctrl_uart1_dcd: uart1_dcd-0 { 536 atmel,pins = 537 <AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB23 periph A */ 538 }; 539 540 pinctrl_uart1_ri: uart1_ri-0 { 541 atmel,pins = 542 <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB18 periph A */ 543 }; 544 }; 545 546 uart2 { 547 pinctrl_uart2: uart2-0 { 548 atmel,pins = 549 <AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP 550 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; 551 }; 552 553 pinctrl_uart2_rts: uart2_rts-0 { 554 atmel,pins = 555 <AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA30 periph B */ 556 }; 557 558 pinctrl_uart2_cts: uart2_cts-0 { 559 atmel,pins = 560 <AT91_PIOA 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA31 periph B */ 561 }; 562 }; 563 564 uart3 { 565 pinctrl_uart3: uart3-0 { 566 atmel,pins = 567 <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE 568 AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; 569 }; 570 571 pinctrl_uart3_rts: uart3_rts-0 { 572 atmel,pins = 573 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB0 periph B */ 574 }; 575 576 pinctrl_uart3_cts: uart3_cts-0 { 577 atmel,pins = 578 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB1 periph B */ 579 }; 580 }; 581 582 nand { 583 pinctrl_nand: nand-0 { 584 atmel,pins = 585 <AT91_PIOC 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PC2 gpio RDY pin pull_up */ 586 AT91_PIOB 1 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PB1 gpio CD pin pull_up */ 587 }; 588 }; 589 590 macb { 591 pinctrl_macb_rmii: macb_rmii-0 { 592 atmel,pins = 593 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA7 periph A */ 594 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA8 periph A */ 595 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA9 periph A */ 596 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA10 periph A */ 597 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA11 periph A */ 598 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA12 periph A */ 599 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA13 periph A */ 600 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA14 periph A */ 601 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA15 periph A */ 602 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA16 periph A */ 603 }; 604 605 pinctrl_macb_rmii_mii: macb_rmii_mii-0 { 606 atmel,pins = 607 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB12 periph B */ 608 AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB13 periph B */ 609 AT91_PIOB 14 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB14 periph B */ 610 AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB15 periph B */ 611 AT91_PIOB 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB16 periph B */ 612 AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB17 periph B */ 613 AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB18 periph B */ 614 AT91_PIOB 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB19 periph B */ 615 }; 616 }; 617 618 mmc0 { 619 pinctrl_mmc0_clk: mmc0_clk-0 { 620 atmel,pins = 621 <AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */ 622 }; 623 624 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 { 625 atmel,pins = 626 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA28 periph A with pullup */ 627 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA29 periph A with pullup */ 628 }; 629 630 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 { 631 atmel,pins = 632 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB3 periph B with pullup */ 633 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PB4 periph B with pullup */ 634 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PB5 periph B with pullup */ 635 }; 636 637 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 { 638 atmel,pins = 639 <AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA8 periph B with pullup */ 640 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA9 periph B with pullup */ 641 }; 642 643 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 { 644 atmel,pins = 645 <AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA10 periph B with pullup */ 646 AT91_PIOA 11 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* PA11 periph B with pullup */ 647 AT91_PIOA 12 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PA12 periph B with pullup */ 648 }; 649 }; 650 651 ssc0 { 652 pinctrl_ssc0_tx: ssc0_tx-0 { 653 atmel,pins = 654 <AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB0 periph A */ 655 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB1 periph A */ 656 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB2 periph A */ 657 }; 658 659 pinctrl_ssc0_rx: ssc0_rx-0 { 660 atmel,pins = 661 <AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB3 periph A */ 662 AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB4 periph A */ 663 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB5 periph A */ 664 }; 665 }; 666 667 ssc1 { 668 pinctrl_ssc1_tx: ssc1_tx-0 { 669 atmel,pins = 670 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */ 671 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */ 672 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */ 673 }; 674 675 pinctrl_ssc1_rx: ssc1_rx-0 { 676 atmel,pins = 677 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */ 678 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */ 679 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */ 680 }; 681 }; 682 683 ssc2 { 684 pinctrl_ssc2_tx: ssc2_tx-0 { 685 atmel,pins = 686 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A */ 687 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A */ 688 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A */ 689 }; 690 691 pinctrl_ssc2_rx: ssc2_rx-0 { 692 atmel,pins = 693 <AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB15 periph A */ 694 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB16 periph A */ 695 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB17 periph A */ 696 }; 697 }; 698 699 twi { 700 pinctrl_twi: twi-0 { 701 atmel,pins = 702 <AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE /* PA25 periph A with multi drive */ 703 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_MULTI_DRIVE>; /* PA26 periph A with multi drive */ 704 }; 705 706 pinctrl_twi_gpio: twi_gpio-0 { 707 atmel,pins = 708 <AT91_PIOA 25 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE /* PA25 GPIO with multi drive */ 709 AT91_PIOA 26 AT91_PERIPH_GPIO AT91_PINCTRL_MULTI_DRIVE>; /* PA26 GPIO with multi drive */ 710 }; 711 }; 712 713 tcb0 { 714 pinctrl_tcb0_tclk0: tcb0_tclk0-0 { 715 atmel,pins = <AT91_PIOA 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; 716 }; 717 718 pinctrl_tcb0_tclk1: tcb0_tclk1-0 { 719 atmel,pins = <AT91_PIOA 14 AT91_PERIPH_B AT91_PINCTRL_NONE>; 720 }; 721 722 pinctrl_tcb0_tclk2: tcb0_tclk2-0 { 723 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_B AT91_PINCTRL_NONE>; 724 }; 725 726 pinctrl_tcb0_tioa0: tcb0_tioa0-0 { 727 atmel,pins = <AT91_PIOA 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; 728 }; 729 730 pinctrl_tcb0_tioa1: tcb0_tioa1-0 { 731 atmel,pins = <AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; 732 }; 733 734 pinctrl_tcb0_tioa2: tcb0_tioa2-0 { 735 atmel,pins = <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; 736 }; 737 738 pinctrl_tcb0_tiob0: tcb0_tiob0-0 { 739 atmel,pins = <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE>; 740 }; 741 742 pinctrl_tcb0_tiob1: tcb0_tiob1-0 { 743 atmel,pins = <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; 744 }; 745 746 pinctrl_tcb0_tiob2: tcb0_tiob2-0 { 747 atmel,pins = <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; 748 }; 749 }; 750 751 tcb1 { 752 pinctrl_tcb1_tclk0: tcb1_tclk0-0 { 753 atmel,pins = <AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; 754 }; 755 756 pinctrl_tcb1_tclk1: tcb1_tclk1-0 { 757 atmel,pins = <AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; 758 }; 759 760 pinctrl_tcb1_tclk2: tcb1_tclk2-0 { 761 atmel,pins = <AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; 762 }; 763 764 pinctrl_tcb1_tioa0: tcb1_tioa0-0 { 765 atmel,pins = <AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; 766 }; 767 768 pinctrl_tcb1_tioa1: tcb1_tioa1-0 { 769 atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; 770 }; 771 772 pinctrl_tcb1_tioa2: tcb1_tioa2-0 { 773 atmel,pins = <AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; 774 }; 775 776 pinctrl_tcb1_tiob0: tcb1_tiob0-0 { 777 atmel,pins = <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; 778 }; 779 780 pinctrl_tcb1_tiob1: tcb1_tiob1-0 { 781 atmel,pins = <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; 782 }; 783 784 pinctrl_tcb1_tiob2: tcb1_tiob2-0 { 785 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; 786 }; 787 }; 788 789 spi0 { 790 pinctrl_spi0: spi0-0 { 791 atmel,pins = 792 <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA0 periph A SPI0_MISO pin */ 793 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA1 periph A SPI0_MOSI pin */ 794 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA2 periph A SPI0_SPCK pin */ 795 }; 796 }; 797 798 pioA: gpio@fffff400 { 799 compatible = "atmel,at91rm9200-gpio"; 800 reg = <0xfffff400 0x200>; 801 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 802 #gpio-cells = <2>; 803 gpio-controller; 804 interrupt-controller; 805 #interrupt-cells = <2>; 806 clocks = <&pioA_clk>; 807 }; 808 809 pioB: gpio@fffff600 { 810 compatible = "atmel,at91rm9200-gpio"; 811 reg = <0xfffff600 0x200>; 812 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 813 #gpio-cells = <2>; 814 gpio-controller; 815 interrupt-controller; 816 #interrupt-cells = <2>; 817 clocks = <&pioB_clk>; 818 }; 819 820 pioC: gpio@fffff800 { 821 compatible = "atmel,at91rm9200-gpio"; 822 reg = <0xfffff800 0x200>; 823 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 824 #gpio-cells = <2>; 825 gpio-controller; 826 interrupt-controller; 827 #interrupt-cells = <2>; 828 clocks = <&pioC_clk>; 829 }; 830 831 pioD: gpio@fffffa00 { 832 compatible = "atmel,at91rm9200-gpio"; 833 reg = <0xfffffa00 0x200>; 834 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; 835 #gpio-cells = <2>; 836 gpio-controller; 837 interrupt-controller; 838 #interrupt-cells = <2>; 839 clocks = <&pioD_clk>; 840 }; 841 }; 842 843 dbgu: serial@fffff200 { 844 compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart"; 845 reg = <0xfffff200 0x200>; 846 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 847 pinctrl-names = "default"; 848 pinctrl-0 = <&pinctrl_dbgu>; 849 clocks = <&mck>; 850 clock-names = "usart"; 851 status = "disabled"; 852 }; 853 854 usart0: serial@fffc0000 { 855 compatible = "atmel,at91rm9200-usart"; 856 reg = <0xfffc0000 0x200>; 857 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>; 858 atmel,use-dma-rx; 859 atmel,use-dma-tx; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&pinctrl_uart0>; 862 clocks = <&usart0_clk>; 863 clock-names = "usart"; 864 status = "disabled"; 865 }; 866 867 usart1: serial@fffc4000 { 868 compatible = "atmel,at91rm9200-usart"; 869 reg = <0xfffc4000 0x200>; 870 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>; 871 atmel,use-dma-rx; 872 atmel,use-dma-tx; 873 pinctrl-names = "default"; 874 pinctrl-0 = <&pinctrl_uart1>; 875 clocks = <&usart1_clk>; 876 clock-names = "usart"; 877 status = "disabled"; 878 }; 879 880 usart2: serial@fffc8000 { 881 compatible = "atmel,at91rm9200-usart"; 882 reg = <0xfffc8000 0x200>; 883 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>; 884 atmel,use-dma-rx; 885 atmel,use-dma-tx; 886 pinctrl-names = "default"; 887 pinctrl-0 = <&pinctrl_uart2>; 888 clocks = <&usart2_clk>; 889 clock-names = "usart"; 890 status = "disabled"; 891 }; 892 893 usart3: serial@fffcc000 { 894 compatible = "atmel,at91rm9200-usart"; 895 reg = <0xfffcc000 0x200>; 896 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>; 897 atmel,use-dma-rx; 898 atmel,use-dma-tx; 899 pinctrl-names = "default"; 900 pinctrl-0 = <&pinctrl_uart3>; 901 clocks = <&usart3_clk>; 902 clock-names = "usart"; 903 status = "disabled"; 904 }; 905 906 usb1: gadget@fffb0000 { 907 compatible = "atmel,at91rm9200-udc"; 908 reg = <0xfffb0000 0x4000>; 909 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>; 910 clocks = <&udc_clk>, <&udpck>; 911 clock-names = "pclk", "hclk"; 912 status = "disabled"; 913 }; 914 915 spi0: spi@fffe0000 { 916 #address-cells = <1>; 917 #size-cells = <0>; 918 compatible = "atmel,at91rm9200-spi"; 919 reg = <0xfffe0000 0x200>; 920 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>; 921 pinctrl-names = "default"; 922 pinctrl-0 = <&pinctrl_spi0>; 923 clocks = <&spi0_clk>; 924 clock-names = "spi_clk"; 925 status = "disabled"; 926 }; 927 }; 928 929 nand0: nand@40000000 { 930 compatible = "atmel,at91rm9200-nand"; 931 #address-cells = <1>; 932 #size-cells = <1>; 933 reg = <0x40000000 0x10000000>; 934 atmel,nand-addr-offset = <21>; 935 atmel,nand-cmd-offset = <22>; 936 pinctrl-names = "default"; 937 pinctrl-0 = <&pinctrl_nand>; 938 nand-ecc-mode = "soft"; 939 gpios = <&pioC 2 GPIO_ACTIVE_HIGH 940 0 941 &pioB 1 GPIO_ACTIVE_HIGH 942 >; 943 status = "disabled"; 944 }; 945 946 usb0: ohci@300000 { 947 compatible = "atmel,at91rm9200-ohci", "usb-ohci"; 948 reg = <0x00300000 0x100000>; 949 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 2>; 950 clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>; 951 clock-names = "ohci_clk", "hclk", "uhpck"; 952 status = "disabled"; 953 }; 954 }; 955 956 i2c-gpio-0 { 957 compatible = "i2c-gpio"; 958 gpios = <&pioA 25 GPIO_ACTIVE_HIGH /* sda */ 959 &pioA 26 GPIO_ACTIVE_HIGH /* scl */ 960 >; 961 i2c-gpio,sda-open-drain; 962 i2c-gpio,scl-open-drain; 963 i2c-gpio,delay-us = <2>; /* ~100 kHz */ 964 pinctrl-names = "default"; 965 pinctrl-0 = <&pinctrl_twi_gpio>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 status = "disabled"; 969 }; 970}; 971
