1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/clock/aspeed-clock.h>
3
4/ {
5	model = "Aspeed BMC";
6	compatible = "aspeed,ast2400";
7	#address-cells = <1>;
8	#size-cells = <1>;
9	interrupt-parent = <&vic>;
10
11	aliases {
12		i2c0 = &i2c0;
13		i2c1 = &i2c1;
14		i2c2 = &i2c2;
15		i2c3 = &i2c3;
16		i2c4 = &i2c4;
17		i2c5 = &i2c5;
18		i2c6 = &i2c6;
19		i2c7 = &i2c7;
20		i2c8 = &i2c8;
21		i2c9 = &i2c9;
22		i2c10 = &i2c10;
23		i2c11 = &i2c11;
24		i2c12 = &i2c12;
25		i2c13 = &i2c13;
26		serial0 = &uart1;
27		serial1 = &uart2;
28		serial2 = &uart3;
29		serial3 = &uart4;
30		serial4 = &uart5;
31		serial5 = &vuart;
32	};
33
34	cpus {
35		#address-cells = <1>;
36		#size-cells = <0>;
37
38		cpu@0 {
39			compatible = "arm,arm926ej-s";
40			device_type = "cpu";
41			reg = <0>;
42		};
43	};
44
45	memory@40000000 {
46		device_type = "memory";
47		reg = <0x40000000 0>;
48	};
49
50	ahb {
51		compatible = "simple-bus";
52		#address-cells = <1>;
53		#size-cells = <1>;
54		ranges;
55
56		fmc: spi@1e620000 {
57			reg = < 0x1e620000 0x94
58				0x20000000 0x10000000 >;
59			#address-cells = <1>;
60			#size-cells = <0>;
61			compatible = "aspeed,ast2400-fmc";
62			clocks = <&syscon ASPEED_CLK_AHB>;
63			status = "disabled";
64			interrupts = <19>;
65			flash@0 {
66				reg = < 0 >;
67				compatible = "jedec,spi-nor";
68				status = "disabled";
69			};
70			flash@1 {
71				reg = < 1 >;
72				compatible = "jedec,spi-nor";
73				status = "disabled";
74			};
75			flash@2 {
76				reg = < 2 >;
77				compatible = "jedec,spi-nor";
78				status = "disabled";
79			};
80			flash@3 {
81				reg = < 3 >;
82				compatible = "jedec,spi-nor";
83				status = "disabled";
84			};
85			flash@4 {
86				reg = < 4 >;
87				compatible = "jedec,spi-nor";
88				status = "disabled";
89			};
90		};
91
92		spi: spi@1e630000 {
93			reg = < 0x1e630000 0x18
94				0x30000000 0x10000000 >;
95			#address-cells = <1>;
96			#size-cells = <0>;
97			compatible = "aspeed,ast2400-spi";
98			clocks = <&syscon ASPEED_CLK_AHB>;
99			status = "disabled";
100			flash@0 {
101				reg = < 0 >;
102				compatible = "jedec,spi-nor";
103				status = "disabled";
104			};
105		};
106
107		vic: interrupt-controller@1e6c0080 {
108			compatible = "aspeed,ast2400-vic";
109			interrupt-controller;
110			#interrupt-cells = <1>;
111			valid-sources = <0xffffffff 0x0007ffff>;
112			reg = <0x1e6c0080 0x80>;
113		};
114
115		cvic: copro-interrupt-controller@1e6c2000 {
116			compatible = "aspeed,ast2400-cvic", "aspeed-cvic";
117			valid-sources = <0x7fffffff>;
118			reg = <0x1e6c2000 0x80>;
119		};
120
121		mac0: ethernet@1e660000 {
122			compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
123			reg = <0x1e660000 0x180>;
124			interrupts = <2>;
125			clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
126			status = "disabled";
127		};
128
129		mac1: ethernet@1e680000 {
130			compatible = "aspeed,ast2400-mac", "faraday,ftgmac100";
131			reg = <0x1e680000 0x180>;
132			interrupts = <3>;
133			clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
134			status = "disabled";
135		};
136
137		ehci0: usb@1e6a1000 {
138			compatible = "aspeed,ast2400-ehci", "generic-ehci";
139			reg = <0x1e6a1000 0x100>;
140			interrupts = <5>;
141			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
142			pinctrl-names = "default";
143			pinctrl-0 = <&pinctrl_usb2h_default>;
144			status = "disabled";
145		};
146
147		uhci: usb@1e6b0000 {
148			compatible = "aspeed,ast2400-uhci", "generic-uhci";
149			reg = <0x1e6b0000 0x100>;
150			interrupts = <14>;
151			#ports = <3>;
152			clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
153			status = "disabled";
154			/*
155			 * No default pinmux, it will follow EHCI, use an explicit pinmux
156			 * override if you don't enable EHCI
157			 */
158		};
159
160		vhub: usb-vhub@1e6a0000 {
161			compatible = "aspeed,ast2400-usb-vhub";
162			reg = <0x1e6a0000 0x300>;
163			interrupts = <5>;
164			clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
165			pinctrl-names = "default";
166			pinctrl-0 = <&pinctrl_usb2d_default>;
167			status = "disabled";
168		};
169
170		apb {
171			compatible = "simple-bus";
172			#address-cells = <1>;
173			#size-cells = <1>;
174			ranges;
175
176			syscon: syscon@1e6e2000 {
177				compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
178				reg = <0x1e6e2000 0x1a8>;
179				#address-cells = <1>;
180				#size-cells = <0>;
181				#clock-cells = <1>;
182				#reset-cells = <1>;
183
184				pinctrl: pinctrl {
185					compatible = "aspeed,g4-pinctrl";
186				};
187
188				p2a: p2a-control {
189					compatible = "aspeed,ast2400-p2a-ctrl";
190					status = "disabled";
191				};
192			};
193
194			rng: hwrng@1e6e2078 {
195				compatible = "timeriomem_rng";
196				reg = <0x1e6e2078 0x4>;
197				period = <1>;
198				quality = <100>;
199			};
200
201			adc: adc@1e6e9000 {
202				compatible = "aspeed,ast2400-adc";
203				reg = <0x1e6e9000 0xb0>;
204				clocks = <&syscon ASPEED_CLK_APB>;
205				resets = <&syscon ASPEED_RESET_ADC>;
206				#io-channel-cells = <1>;
207				status = "disabled";
208			};
209
210			sram: sram@1e720000 {
211				compatible = "mmio-sram";
212				reg = <0x1e720000 0x8000>;	// 32K
213			};
214
215			sdmmc: sd-controller@1e740000 {
216				compatible = "aspeed,ast2400-sd-controller";
217				reg = <0x1e740000 0x100>;
218				#address-cells = <1>;
219				#size-cells = <1>;
220				ranges = <0 0x1e740000 0x10000>;
221				clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
222				status = "disabled";
223
224				sdhci0: sdhci@100 {
225					compatible = "aspeed,ast2400-sdhci";
226					reg = <0x100 0x100>;
227					interrupts = <26>;
228					sdhci,auto-cmd12;
229					clocks = <&syscon ASPEED_CLK_SDIO>;
230					status = "disabled";
231				};
232
233				sdhci1: sdhci@200 {
234					compatible = "aspeed,ast2400-sdhci";
235					reg = <0x200 0x100>;
236					interrupts = <26>;
237					sdhci,auto-cmd12;
238					clocks = <&syscon ASPEED_CLK_SDIO>;
239					status = "disabled";
240				};
241			};
242
243			gpio: gpio@1e780000 {
244				#gpio-cells = <2>;
245				gpio-controller;
246				compatible = "aspeed,ast2400-gpio";
247				reg = <0x1e780000 0x1000>;
248				interrupts = <20>;
249				gpio-ranges = <&pinctrl 0 0 220>;
250				clocks = <&syscon ASPEED_CLK_APB>;
251				interrupt-controller;
252				#interrupt-cells = <2>;
253			};
254
255			timer: timer@1e782000 {
256				/* This timer is a Faraday FTTMR010 derivative */
257				compatible = "aspeed,ast2400-timer";
258				reg = <0x1e782000 0x90>;
259				interrupts = <16 17 18 35 36 37 38 39>;
260				clocks = <&syscon ASPEED_CLK_APB>;
261				clock-names = "PCLK";
262			};
263
264			rtc: rtc@1e781000 {
265				compatible = "aspeed,ast2400-rtc";
266				reg = <0x1e781000 0x18>;
267				status = "disabled";
268			};
269
270			uart1: serial@1e783000 {
271				compatible = "ns16550a";
272				reg = <0x1e783000 0x20>;
273				reg-shift = <2>;
274				interrupts = <9>;
275				clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
276				resets = <&lpc_reset 4>;
277				no-loopback-test;
278				status = "disabled";
279			};
280
281			uart5: serial@1e784000 {
282				compatible = "ns16550a";
283				reg = <0x1e784000 0x20>;
284				reg-shift = <2>;
285				interrupts = <10>;
286				clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
287				no-loopback-test;
288				status = "disabled";
289			};
290
291			wdt1: watchdog@1e785000 {
292				compatible = "aspeed,ast2400-wdt";
293				reg = <0x1e785000 0x1c>;
294				clocks = <&syscon ASPEED_CLK_APB>;
295			};
296
297			wdt2: watchdog@1e785020 {
298				compatible = "aspeed,ast2400-wdt";
299				reg = <0x1e785020 0x1c>;
300				clocks = <&syscon ASPEED_CLK_APB>;
301			};
302
303			pwm_tacho: pwm-tacho-controller@1e786000 {
304				compatible = "aspeed,ast2400-pwm-tacho";
305				#address-cells = <1>;
306				#size-cells = <0>;
307				reg = <0x1e786000 0x1000>;
308				clocks = <&syscon ASPEED_CLK_24M>;
309				resets = <&syscon ASPEED_RESET_PWM>;
310				status = "disabled";
311			};
312
313			vuart: serial@1e787000 {
314				compatible = "aspeed,ast2400-vuart";
315				reg = <0x1e787000 0x40>;
316				reg-shift = <2>;
317				interrupts = <8>;
318				clocks = <&syscon ASPEED_CLK_APB>;
319				no-loopback-test;
320				status = "disabled";
321			};
322
323			lpc: lpc@1e789000 {
324				compatible = "aspeed,ast2400-lpc", "simple-mfd";
325				reg = <0x1e789000 0x1000>;
326
327				#address-cells = <1>;
328				#size-cells = <1>;
329				ranges = <0x0 0x1e789000 0x1000>;
330
331				lpc_bmc: lpc-bmc@0 {
332					compatible = "aspeed,ast2400-lpc-bmc";
333					reg = <0x0 0x80>;
334				};
335
336				lpc_host: lpc-host@80 {
337					compatible = "aspeed,ast2400-lpc-host", "simple-mfd", "syscon";
338					reg = <0x80 0x1e0>;
339					reg-io-width = <4>;
340
341					#address-cells = <1>;
342					#size-cells = <1>;
343					ranges = <0x0 0x80 0x1e0>;
344
345					lpc_ctrl: lpc-ctrl@0 {
346						compatible = "aspeed,ast2400-lpc-ctrl";
347						reg = <0x0 0x80>;
348						clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
349						status = "disabled";
350					};
351
352					lpc_snoop: lpc-snoop@0 {
353						compatible = "aspeed,ast2400-lpc-snoop";
354						reg = <0x0 0x80>;
355						interrupts = <8>;
356						status = "disabled";
357					};
358
359					lhc: lhc@20 {
360						compatible = "aspeed,ast2400-lhc";
361						reg = <0x20 0x24 0x48 0x8>;
362					};
363
364					lpc_reset: reset-controller@18 {
365						compatible = "aspeed,ast2400-lpc-reset";
366						reg = <0x18 0x4>;
367						#reset-cells = <1>;
368					};
369
370					ibt: ibt@c0  {
371						compatible = "aspeed,ast2400-ibt-bmc";
372						reg = <0xc0 0x18>;
373						interrupts = <8>;
374						status = "disabled";
375					};
376				};
377			};
378
379			uart2: serial@1e78d000 {
380				compatible = "ns16550a";
381				reg = <0x1e78d000 0x20>;
382				reg-shift = <2>;
383				interrupts = <32>;
384				clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
385				resets = <&lpc_reset 5>;
386				no-loopback-test;
387				status = "disabled";
388			};
389
390			uart3: serial@1e78e000 {
391				compatible = "ns16550a";
392				reg = <0x1e78e000 0x20>;
393				reg-shift = <2>;
394				interrupts = <33>;
395				clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
396				resets = <&lpc_reset 6>;
397				no-loopback-test;
398				status = "disabled";
399			};
400
401			uart4: serial@1e78f000 {
402				compatible = "ns16550a";
403				reg = <0x1e78f000 0x20>;
404				reg-shift = <2>;
405				interrupts = <34>;
406				clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
407				resets = <&lpc_reset 7>;
408				no-loopback-test;
409				status = "disabled";
410			};
411
412			i2c: bus@1e78a000 {
413				compatible = "simple-bus";
414				#address-cells = <1>;
415				#size-cells = <1>;
416				ranges = <0 0x1e78a000 0x1000>;
417			};
418		};
419	};
420};
421
422&i2c {
423	i2c_ic: interrupt-controller@0 {
424		#interrupt-cells = <1>;
425		compatible = "aspeed,ast2400-i2c-ic";
426		reg = <0x0 0x40>;
427		interrupts = <12>;
428		interrupt-controller;
429	};
430
431	i2c0: i2c-bus@40 {
432		#address-cells = <1>;
433		#size-cells = <0>;
434		#interrupt-cells = <1>;
435
436		reg = <0x40 0x40>;
437		compatible = "aspeed,ast2400-i2c-bus";
438		clocks = <&syscon ASPEED_CLK_APB>;
439		resets = <&syscon ASPEED_RESET_I2C>;
440		bus-frequency = <100000>;
441		interrupts = <0>;
442		interrupt-parent = <&i2c_ic>;
443		status = "disabled";
444		/* Does not need pinctrl properties */
445	};
446
447	i2c1: i2c-bus@80 {
448		#address-cells = <1>;
449		#size-cells = <0>;
450		#interrupt-cells = <1>;
451
452		reg = <0x80 0x40>;
453		compatible = "aspeed,ast2400-i2c-bus";
454		clocks = <&syscon ASPEED_CLK_APB>;
455		resets = <&syscon ASPEED_RESET_I2C>;
456		bus-frequency = <100000>;
457		interrupts = <1>;
458		interrupt-parent = <&i2c_ic>;
459		status = "disabled";
460		/* Does not need pinctrl properties */
461	};
462
463	i2c2: i2c-bus@c0 {
464		#address-cells = <1>;
465		#size-cells = <0>;
466		#interrupt-cells = <1>;
467
468		reg = <0xc0 0x40>;
469		compatible = "aspeed,ast2400-i2c-bus";
470		clocks = <&syscon ASPEED_CLK_APB>;
471		resets = <&syscon ASPEED_RESET_I2C>;
472		bus-frequency = <100000>;
473		interrupts = <2>;
474		interrupt-parent = <&i2c_ic>;
475		pinctrl-names = "default";
476		pinctrl-0 = <&pinctrl_i2c3_default>;
477		status = "disabled";
478	};
479
480	i2c3: i2c-bus@100 {
481		#address-cells = <1>;
482		#size-cells = <0>;
483		#interrupt-cells = <1>;
484
485		reg = <0x100 0x40>;
486		compatible = "aspeed,ast2400-i2c-bus";
487		clocks = <&syscon ASPEED_CLK_APB>;
488		resets = <&syscon ASPEED_RESET_I2C>;
489		bus-frequency = <100000>;
490		interrupts = <3>;
491		interrupt-parent = <&i2c_ic>;
492		pinctrl-names = "default";
493		pinctrl-0 = <&pinctrl_i2c4_default>;
494		status = "disabled";
495	};
496
497	i2c4: i2c-bus@140 {
498		#address-cells = <1>;
499		#size-cells = <0>;
500		#interrupt-cells = <1>;
501
502		reg = <0x140 0x40>;
503		compatible = "aspeed,ast2400-i2c-bus";
504		clocks = <&syscon ASPEED_CLK_APB>;
505		resets = <&syscon ASPEED_RESET_I2C>;
506		bus-frequency = <100000>;
507		interrupts = <4>;
508		interrupt-parent = <&i2c_ic>;
509		pinctrl-names = "default";
510		pinctrl-0 = <&pinctrl_i2c5_default>;
511		status = "disabled";
512	};
513
514	i2c5: i2c-bus@180 {
515		#address-cells = <1>;
516		#size-cells = <0>;
517		#interrupt-cells = <1>;
518
519		reg = <0x180 0x40>;
520		compatible = "aspeed,ast2400-i2c-bus";
521		clocks = <&syscon ASPEED_CLK_APB>;
522		resets = <&syscon ASPEED_RESET_I2C>;
523		bus-frequency = <100000>;
524		interrupts = <5>;
525		interrupt-parent = <&i2c_ic>;
526		pinctrl-names = "default";
527		pinctrl-0 = <&pinctrl_i2c6_default>;
528		status = "disabled";
529	};
530
531	i2c6: i2c-bus@1c0 {
532		#address-cells = <1>;
533		#size-cells = <0>;
534		#interrupt-cells = <1>;
535
536		reg = <0x1c0 0x40>;
537		compatible = "aspeed,ast2400-i2c-bus";
538		clocks = <&syscon ASPEED_CLK_APB>;
539		resets = <&syscon ASPEED_RESET_I2C>;
540		bus-frequency = <100000>;
541		interrupts = <6>;
542		interrupt-parent = <&i2c_ic>;
543		pinctrl-names = "default";
544		pinctrl-0 = <&pinctrl_i2c7_default>;
545		status = "disabled";
546	};
547
548	i2c7: i2c-bus@300 {
549		#address-cells = <1>;
550		#size-cells = <0>;
551		#interrupt-cells = <1>;
552
553		reg = <0x300 0x40>;
554		compatible = "aspeed,ast2400-i2c-bus";
555		clocks = <&syscon ASPEED_CLK_APB>;
556		resets = <&syscon ASPEED_RESET_I2C>;
557		bus-frequency = <100000>;
558		interrupts = <7>;
559		interrupt-parent = <&i2c_ic>;
560		pinctrl-names = "default";
561		pinctrl-0 = <&pinctrl_i2c8_default>;
562		status = "disabled";
563	};
564
565	i2c8: i2c-bus@340 {
566		#address-cells = <1>;
567		#size-cells = <0>;
568		#interrupt-cells = <1>;
569
570		reg = <0x340 0x40>;
571		compatible = "aspeed,ast2400-i2c-bus";
572		clocks = <&syscon ASPEED_CLK_APB>;
573		resets = <&syscon ASPEED_RESET_I2C>;
574		bus-frequency = <100000>;
575		interrupts = <8>;
576		interrupt-parent = <&i2c_ic>;
577		pinctrl-names = "default";
578		pinctrl-0 = <&pinctrl_i2c9_default>;
579		status = "disabled";
580	};
581
582	i2c9: i2c-bus@380 {
583		#address-cells = <1>;
584		#size-cells = <0>;
585		#interrupt-cells = <1>;
586
587		reg = <0x380 0x40>;
588		compatible = "aspeed,ast2400-i2c-bus";
589		clocks = <&syscon ASPEED_CLK_APB>;
590		resets = <&syscon ASPEED_RESET_I2C>;
591		bus-frequency = <100000>;
592		interrupts = <9>;
593		interrupt-parent = <&i2c_ic>;
594		pinctrl-names = "default";
595		pinctrl-0 = <&pinctrl_i2c10_default>;
596		status = "disabled";
597	};
598
599	i2c10: i2c-bus@3c0 {
600		#address-cells = <1>;
601		#size-cells = <0>;
602		#interrupt-cells = <1>;
603
604		reg = <0x3c0 0x40>;
605		compatible = "aspeed,ast2400-i2c-bus";
606		clocks = <&syscon ASPEED_CLK_APB>;
607		resets = <&syscon ASPEED_RESET_I2C>;
608		bus-frequency = <100000>;
609		interrupts = <10>;
610		interrupt-parent = <&i2c_ic>;
611		pinctrl-names = "default";
612		pinctrl-0 = <&pinctrl_i2c11_default>;
613		status = "disabled";
614	};
615
616	i2c11: i2c-bus@400 {
617		#address-cells = <1>;
618		#size-cells = <0>;
619		#interrupt-cells = <1>;
620
621		reg = <0x400 0x40>;
622		compatible = "aspeed,ast2400-i2c-bus";
623		clocks = <&syscon ASPEED_CLK_APB>;
624		resets = <&syscon ASPEED_RESET_I2C>;
625		bus-frequency = <100000>;
626		interrupts = <11>;
627		interrupt-parent = <&i2c_ic>;
628		pinctrl-names = "default";
629		pinctrl-0 = <&pinctrl_i2c12_default>;
630		status = "disabled";
631	};
632
633	i2c12: i2c-bus@440 {
634		#address-cells = <1>;
635		#size-cells = <0>;
636		#interrupt-cells = <1>;
637
638		reg = <0x440 0x40>;
639		compatible = "aspeed,ast2400-i2c-bus";
640		clocks = <&syscon ASPEED_CLK_APB>;
641		resets = <&syscon ASPEED_RESET_I2C>;
642		bus-frequency = <100000>;
643		interrupts = <12>;
644		interrupt-parent = <&i2c_ic>;
645		pinctrl-names = "default";
646		pinctrl-0 = <&pinctrl_i2c13_default>;
647		status = "disabled";
648	};
649
650	i2c13: i2c-bus@480 {
651		#address-cells = <1>;
652		#size-cells = <0>;
653		#interrupt-cells = <1>;
654
655		reg = <0x480 0x40>;
656		compatible = "aspeed,ast2400-i2c-bus";
657		clocks = <&syscon ASPEED_CLK_APB>;
658		resets = <&syscon ASPEED_RESET_I2C>;
659		bus-frequency = <100000>;
660		interrupts = <13>;
661		interrupt-parent = <&i2c_ic>;
662		pinctrl-names = "default";
663		pinctrl-0 = <&pinctrl_i2c14_default>;
664		status = "disabled";
665	};
666};
667
668&pinctrl {
669	pinctrl_acpi_default: acpi_default {
670		function = "ACPI";
671		groups = "ACPI";
672	};
673
674	pinctrl_adc0_default: adc0_default {
675		function = "ADC0";
676		groups = "ADC0";
677	};
678
679	pinctrl_adc1_default: adc1_default {
680		function = "ADC1";
681		groups = "ADC1";
682	};
683
684	pinctrl_adc10_default: adc10_default {
685		function = "ADC10";
686		groups = "ADC10";
687	};
688
689	pinctrl_adc11_default: adc11_default {
690		function = "ADC11";
691		groups = "ADC11";
692	};
693
694	pinctrl_adc12_default: adc12_default {
695		function = "ADC12";
696		groups = "ADC12";
697	};
698
699	pinctrl_adc13_default: adc13_default {
700		function = "ADC13";
701		groups = "ADC13";
702	};
703
704	pinctrl_adc14_default: adc14_default {
705		function = "ADC14";
706		groups = "ADC14";
707	};
708
709	pinctrl_adc15_default: adc15_default {
710		function = "ADC15";
711		groups = "ADC15";
712	};
713
714	pinctrl_adc2_default: adc2_default {
715		function = "ADC2";
716		groups = "ADC2";
717	};
718
719	pinctrl_adc3_default: adc3_default {
720		function = "ADC3";
721		groups = "ADC3";
722	};
723
724	pinctrl_adc4_default: adc4_default {
725		function = "ADC4";
726		groups = "ADC4";
727	};
728
729	pinctrl_adc5_default: adc5_default {
730		function = "ADC5";
731		groups = "ADC5";
732	};
733
734	pinctrl_adc6_default: adc6_default {
735		function = "ADC6";
736		groups = "ADC6";
737	};
738
739	pinctrl_adc7_default: adc7_default {
740		function = "ADC7";
741		groups = "ADC7";
742	};
743
744	pinctrl_adc8_default: adc8_default {
745		function = "ADC8";
746		groups = "ADC8";
747	};
748
749	pinctrl_adc9_default: adc9_default {
750		function = "ADC9";
751		groups = "ADC9";
752	};
753
754	pinctrl_bmcint_default: bmcint_default {
755		function = "BMCINT";
756		groups = "BMCINT";
757	};
758
759	pinctrl_ddcclk_default: ddcclk_default {
760		function = "DDCCLK";
761		groups = "DDCCLK";
762	};
763
764	pinctrl_ddcdat_default: ddcdat_default {
765		function = "DDCDAT";
766		groups = "DDCDAT";
767	};
768
769	pinctrl_extrst_default: extrst_default {
770		function = "EXTRST";
771		groups = "EXTRST";
772	};
773
774	pinctrl_flack_default: flack_default {
775		function = "FLACK";
776		groups = "FLACK";
777	};
778
779	pinctrl_flbusy_default: flbusy_default {
780		function = "FLBUSY";
781		groups = "FLBUSY";
782	};
783
784	pinctrl_flwp_default: flwp_default {
785		function = "FLWP";
786		groups = "FLWP";
787	};
788
789	pinctrl_gpid_default: gpid_default {
790		function = "GPID";
791		groups = "GPID";
792	};
793
794	pinctrl_gpid0_default: gpid0_default {
795		function = "GPID0";
796		groups = "GPID0";
797	};
798
799	pinctrl_gpid2_default: gpid2_default {
800		function = "GPID2";
801		groups = "GPID2";
802	};
803
804	pinctrl_gpid4_default: gpid4_default {
805		function = "GPID4";
806		groups = "GPID4";
807	};
808
809	pinctrl_gpid6_default: gpid6_default {
810		function = "GPID6";
811		groups = "GPID6";
812	};
813
814	pinctrl_gpie0_default: gpie0_default {
815		function = "GPIE0";
816		groups = "GPIE0";
817	};
818
819	pinctrl_gpie2_default: gpie2_default {
820		function = "GPIE2";
821		groups = "GPIE2";
822	};
823
824	pinctrl_gpie4_default: gpie4_default {
825		function = "GPIE4";
826		groups = "GPIE4";
827	};
828
829	pinctrl_gpie6_default: gpie6_default {
830		function = "GPIE6";
831		groups = "GPIE6";
832	};
833
834	pinctrl_i2c10_default: i2c10_default {
835		function = "I2C10";
836		groups = "I2C10";
837	};
838
839	pinctrl_i2c11_default: i2c11_default {
840		function = "I2C11";
841		groups = "I2C11";
842	};
843
844	pinctrl_i2c12_default: i2c12_default {
845		function = "I2C12";
846		groups = "I2C12";
847	};
848
849	pinctrl_i2c13_default: i2c13_default {
850		function = "I2C13";
851		groups = "I2C13";
852	};
853
854	pinctrl_i2c14_default: i2c14_default {
855		function = "I2C14";
856		groups = "I2C14";
857	};
858
859	pinctrl_i2c3_default: i2c3_default {
860		function = "I2C3";
861		groups = "I2C3";
862	};
863
864	pinctrl_i2c4_default: i2c4_default {
865		function = "I2C4";
866		groups = "I2C4";
867	};
868
869	pinctrl_i2c5_default: i2c5_default {
870		function = "I2C5";
871		groups = "I2C5";
872	};
873
874	pinctrl_i2c6_default: i2c6_default {
875		function = "I2C6";
876		groups = "I2C6";
877	};
878
879	pinctrl_i2c7_default: i2c7_default {
880		function = "I2C7";
881		groups = "I2C7";
882	};
883
884	pinctrl_i2c8_default: i2c8_default {
885		function = "I2C8";
886		groups = "I2C8";
887	};
888
889	pinctrl_i2c9_default: i2c9_default {
890		function = "I2C9";
891		groups = "I2C9";
892	};
893
894	pinctrl_lpcpd_default: lpcpd_default {
895		function = "LPCPD";
896		groups = "LPCPD";
897	};
898
899	pinctrl_lpcpme_default: lpcpme_default {
900		function = "LPCPME";
901		groups = "LPCPME";
902	};
903
904	pinctrl_lpcrst_default: lpcrst_default {
905		function = "LPCRST";
906		groups = "LPCRST";
907	};
908
909	pinctrl_lpcsmi_default: lpcsmi_default {
910		function = "LPCSMI";
911		groups = "LPCSMI";
912	};
913
914	pinctrl_mac1link_default: mac1link_default {
915		function = "MAC1LINK";
916		groups = "MAC1LINK";
917	};
918
919	pinctrl_mac2link_default: mac2link_default {
920		function = "MAC2LINK";
921		groups = "MAC2LINK";
922	};
923
924	pinctrl_mdio1_default: mdio1_default {
925		function = "MDIO1";
926		groups = "MDIO1";
927	};
928
929	pinctrl_mdio2_default: mdio2_default {
930		function = "MDIO2";
931		groups = "MDIO2";
932	};
933
934	pinctrl_ncts1_default: ncts1_default {
935		function = "NCTS1";
936		groups = "NCTS1";
937	};
938
939	pinctrl_ncts2_default: ncts2_default {
940		function = "NCTS2";
941		groups = "NCTS2";
942	};
943
944	pinctrl_ncts3_default: ncts3_default {
945		function = "NCTS3";
946		groups = "NCTS3";
947	};
948
949	pinctrl_ncts4_default: ncts4_default {
950		function = "NCTS4";
951		groups = "NCTS4";
952	};
953
954	pinctrl_ndcd1_default: ndcd1_default {
955		function = "NDCD1";
956		groups = "NDCD1";
957	};
958
959	pinctrl_ndcd2_default: ndcd2_default {
960		function = "NDCD2";
961		groups = "NDCD2";
962	};
963
964	pinctrl_ndcd3_default: ndcd3_default {
965		function = "NDCD3";
966		groups = "NDCD3";
967	};
968
969	pinctrl_ndcd4_default: ndcd4_default {
970		function = "NDCD4";
971		groups = "NDCD4";
972	};
973
974	pinctrl_ndsr1_default: ndsr1_default {
975		function = "NDSR1";
976		groups = "NDSR1";
977	};
978
979	pinctrl_ndsr2_default: ndsr2_default {
980		function = "NDSR2";
981		groups = "NDSR2";
982	};
983
984	pinctrl_ndsr3_default: ndsr3_default {
985		function = "NDSR3";
986		groups = "NDSR3";
987	};
988
989	pinctrl_ndsr4_default: ndsr4_default {
990		function = "NDSR4";
991		groups = "NDSR4";
992	};
993
994	pinctrl_ndtr1_default: ndtr1_default {
995		function = "NDTR1";
996		groups = "NDTR1";
997	};
998
999	pinctrl_ndtr2_default: ndtr2_default {
1000		function = "NDTR2";
1001		groups = "NDTR2";
1002	};
1003
1004	pinctrl_ndtr3_default: ndtr3_default {
1005		function = "NDTR3";
1006		groups = "NDTR3";
1007	};
1008
1009	pinctrl_ndtr4_default: ndtr4_default {
1010		function = "NDTR4";
1011		groups = "NDTR4";
1012	};
1013
1014	pinctrl_ndts4_default: ndts4_default {
1015		function = "NDTS4";
1016		groups = "NDTS4";
1017	};
1018
1019	pinctrl_nri1_default: nri1_default {
1020		function = "NRI1";
1021		groups = "NRI1";
1022	};
1023
1024	pinctrl_nri2_default: nri2_default {
1025		function = "NRI2";
1026		groups = "NRI2";
1027	};
1028
1029	pinctrl_nri3_default: nri3_default {
1030		function = "NRI3";
1031		groups = "NRI3";
1032	};
1033
1034	pinctrl_nri4_default: nri4_default {
1035		function = "NRI4";
1036		groups = "NRI4";
1037	};
1038
1039	pinctrl_nrts1_default: nrts1_default {
1040		function = "NRTS1";
1041		groups = "NRTS1";
1042	};
1043
1044	pinctrl_nrts2_default: nrts2_default {
1045		function = "NRTS2";
1046		groups = "NRTS2";
1047	};
1048
1049	pinctrl_nrts3_default: nrts3_default {
1050		function = "NRTS3";
1051		groups = "NRTS3";
1052	};
1053
1054	pinctrl_oscclk_default: oscclk_default {
1055		function = "OSCCLK";
1056		groups = "OSCCLK";
1057	};
1058
1059	pinctrl_pwm0_default: pwm0_default {
1060		function = "PWM0";
1061		groups = "PWM0";
1062	};
1063
1064	pinctrl_pwm1_default: pwm1_default {
1065		function = "PWM1";
1066		groups = "PWM1";
1067	};
1068
1069	pinctrl_pwm2_default: pwm2_default {
1070		function = "PWM2";
1071		groups = "PWM2";
1072	};
1073
1074	pinctrl_pwm3_default: pwm3_default {
1075		function = "PWM3";
1076		groups = "PWM3";
1077	};
1078
1079	pinctrl_pwm4_default: pwm4_default {
1080		function = "PWM4";
1081		groups = "PWM4";
1082	};
1083
1084	pinctrl_pwm5_default: pwm5_default {
1085		function = "PWM5";
1086		groups = "PWM5";
1087	};
1088
1089	pinctrl_pwm6_default: pwm6_default {
1090		function = "PWM6";
1091		groups = "PWM6";
1092	};
1093
1094	pinctrl_pwm7_default: pwm7_default {
1095		function = "PWM7";
1096		groups = "PWM7";
1097	};
1098
1099	pinctrl_rgmii1_default: rgmii1_default {
1100		function = "RGMII1";
1101		groups = "RGMII1";
1102	};
1103
1104	pinctrl_rgmii2_default: rgmii2_default {
1105		function = "RGMII2";
1106		groups = "RGMII2";
1107	};
1108
1109	pinctrl_rmii1_default: rmii1_default {
1110		function = "RMII1";
1111		groups = "RMII1";
1112	};
1113
1114	pinctrl_rmii2_default: rmii2_default {
1115		function = "RMII2";
1116		groups = "RMII2";
1117	};
1118
1119	pinctrl_rom16_default: rom16_default {
1120		function = "ROM16";
1121		groups = "ROM16";
1122	};
1123
1124	pinctrl_rom8_default: rom8_default {
1125		function = "ROM8";
1126		groups = "ROM8";
1127	};
1128
1129	pinctrl_romcs1_default: romcs1_default {
1130		function = "ROMCS1";
1131		groups = "ROMCS1";
1132	};
1133
1134	pinctrl_romcs2_default: romcs2_default {
1135		function = "ROMCS2";
1136		groups = "ROMCS2";
1137	};
1138
1139	pinctrl_romcs3_default: romcs3_default {
1140		function = "ROMCS3";
1141		groups = "ROMCS3";
1142	};
1143
1144	pinctrl_romcs4_default: romcs4_default {
1145		function = "ROMCS4";
1146		groups = "ROMCS4";
1147	};
1148
1149	pinctrl_rxd1_default: rxd1_default {
1150		function = "RXD1";
1151		groups = "RXD1";
1152	};
1153
1154	pinctrl_rxd2_default: rxd2_default {
1155		function = "RXD2";
1156		groups = "RXD2";
1157	};
1158
1159	pinctrl_rxd3_default: rxd3_default {
1160		function = "RXD3";
1161		groups = "RXD3";
1162	};
1163
1164	pinctrl_rxd4_default: rxd4_default {
1165		function = "RXD4";
1166		groups = "RXD4";
1167	};
1168
1169	pinctrl_salt1_default: salt1_default {
1170		function = "SALT1";
1171		groups = "SALT1";
1172	};
1173
1174	pinctrl_salt2_default: salt2_default {
1175		function = "SALT2";
1176		groups = "SALT2";
1177	};
1178
1179	pinctrl_salt3_default: salt3_default {
1180		function = "SALT3";
1181		groups = "SALT3";
1182	};
1183
1184	pinctrl_salt4_default: salt4_default {
1185		function = "SALT4";
1186		groups = "SALT4";
1187	};
1188
1189	pinctrl_sd1_default: sd1_default {
1190		function = "SD1";
1191		groups = "SD1";
1192	};
1193
1194	pinctrl_sd2_default: sd2_default {
1195		function = "SD2";
1196		groups = "SD2";
1197	};
1198
1199	pinctrl_sgpmck_default: sgpmck_default {
1200		function = "SGPMCK";
1201		groups = "SGPMCK";
1202	};
1203
1204	pinctrl_sgpmi_default: sgpmi_default {
1205		function = "SGPMI";
1206		groups = "SGPMI";
1207	};
1208
1209	pinctrl_sgpmld_default: sgpmld_default {
1210		function = "SGPMLD";
1211		groups = "SGPMLD";
1212	};
1213
1214	pinctrl_sgpmo_default: sgpmo_default {
1215		function = "SGPMO";
1216		groups = "SGPMO";
1217	};
1218
1219	pinctrl_sgpsck_default: sgpsck_default {
1220		function = "SGPSCK";
1221		groups = "SGPSCK";
1222	};
1223
1224	pinctrl_sgpsi0_default: sgpsi0_default {
1225		function = "SGPSI0";
1226		groups = "SGPSI0";
1227	};
1228
1229	pinctrl_sgpsi1_default: sgpsi1_default {
1230		function = "SGPSI1";
1231		groups = "SGPSI1";
1232	};
1233
1234	pinctrl_sgpsld_default: sgpsld_default {
1235		function = "SGPSLD";
1236		groups = "SGPSLD";
1237	};
1238
1239	pinctrl_sioonctrl_default: sioonctrl_default {
1240		function = "SIOONCTRL";
1241		groups = "SIOONCTRL";
1242	};
1243
1244	pinctrl_siopbi_default: siopbi_default {
1245		function = "SIOPBI";
1246		groups = "SIOPBI";
1247	};
1248
1249	pinctrl_siopbo_default: siopbo_default {
1250		function = "SIOPBO";
1251		groups = "SIOPBO";
1252	};
1253
1254	pinctrl_siopwreq_default: siopwreq_default {
1255		function = "SIOPWREQ";
1256		groups = "SIOPWREQ";
1257	};
1258
1259	pinctrl_siopwrgd_default: siopwrgd_default {
1260		function = "SIOPWRGD";
1261		groups = "SIOPWRGD";
1262	};
1263
1264	pinctrl_sios3_default: sios3_default {
1265		function = "SIOS3";
1266		groups = "SIOS3";
1267	};
1268
1269	pinctrl_sios5_default: sios5_default {
1270		function = "SIOS5";
1271		groups = "SIOS5";
1272	};
1273
1274	pinctrl_siosci_default: siosci_default {
1275		function = "SIOSCI";
1276		groups = "SIOSCI";
1277	};
1278
1279	pinctrl_spi1_default: spi1_default {
1280		function = "SPI1";
1281		groups = "SPI1";
1282	};
1283
1284	pinctrl_spi1debug_default: spi1debug_default {
1285		function = "SPI1DEBUG";
1286		groups = "SPI1DEBUG";
1287	};
1288
1289	pinctrl_spi1passthru_default: spi1passthru_default {
1290		function = "SPI1PASSTHRU";
1291		groups = "SPI1PASSTHRU";
1292	};
1293
1294	pinctrl_spics1_default: spics1_default {
1295		function = "SPICS1";
1296		groups = "SPICS1";
1297	};
1298
1299	pinctrl_timer3_default: timer3_default {
1300		function = "TIMER3";
1301		groups = "TIMER3";
1302	};
1303
1304	pinctrl_timer4_default: timer4_default {
1305		function = "TIMER4";
1306		groups = "TIMER4";
1307	};
1308
1309	pinctrl_timer5_default: timer5_default {
1310		function = "TIMER5";
1311		groups = "TIMER5";
1312	};
1313
1314	pinctrl_timer6_default: timer6_default {
1315		function = "TIMER6";
1316		groups = "TIMER6";
1317	};
1318
1319	pinctrl_timer7_default: timer7_default {
1320		function = "TIMER7";
1321		groups = "TIMER7";
1322	};
1323
1324	pinctrl_timer8_default: timer8_default {
1325		function = "TIMER8";
1326		groups = "TIMER8";
1327	};
1328
1329	pinctrl_txd1_default: txd1_default {
1330		function = "TXD1";
1331		groups = "TXD1";
1332	};
1333
1334	pinctrl_txd2_default: txd2_default {
1335		function = "TXD2";
1336		groups = "TXD2";
1337	};
1338
1339	pinctrl_txd3_default: txd3_default {
1340		function = "TXD3";
1341		groups = "TXD3";
1342	};
1343
1344	pinctrl_txd4_default: txd4_default {
1345		function = "TXD4";
1346		groups = "TXD4";
1347	};
1348
1349	pinctrl_uart6_default: uart6_default {
1350		function = "UART6";
1351		groups = "UART6";
1352	};
1353
1354	pinctrl_usbcki_default: usbcki_default {
1355		function = "USBCKI";
1356		groups = "USBCKI";
1357	};
1358
1359	pinctrl_usb2h_default: usb2h_default {
1360		function = "USB2H1";
1361		groups = "USB2H1";
1362	};
1363
1364	pinctrl_usb2d_default: usb2d_default {
1365		function = "USB2D1";
1366		groups = "USB2D1";
1367	};
1368
1369	pinctrl_vgabios_rom_default: vgabios_rom_default {
1370		function = "VGABIOS_ROM";
1371		groups = "VGABIOS_ROM";
1372	};
1373
1374	pinctrl_vgahs_default: vgahs_default {
1375		function = "VGAHS";
1376		groups = "VGAHS";
1377	};
1378
1379	pinctrl_vgavs_default: vgavs_default {
1380		function = "VGAVS";
1381		groups = "VGAVS";
1382	};
1383
1384	pinctrl_vpi18_default: vpi18_default {
1385		function = "VPI18";
1386		groups = "VPI18";
1387	};
1388
1389	pinctrl_vpi24_default: vpi24_default {
1390		function = "VPI24";
1391		groups = "VPI24";
1392	};
1393
1394	pinctrl_vpi30_default: vpi30_default {
1395		function = "VPI30";
1396		groups = "VPI30";
1397	};
1398
1399	pinctrl_vpo12_default: vpo12_default {
1400		function = "VPO12";
1401		groups = "VPO12";
1402	};
1403
1404	pinctrl_vpo24_default: vpo24_default {
1405		function = "VPO24";
1406		groups = "VPO24";
1407	};
1408
1409	pinctrl_wdtrst1_default: wdtrst1_default {
1410		function = "WDTRST1";
1411		groups = "WDTRST1";
1412	};
1413
1414	pinctrl_wdtrst2_default: wdtrst2_default {
1415		function = "WDTRST2";
1416		groups = "WDTRST2";
1417	};
1418};
1419