1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 4 */ 5 6/* AM43x EPOS EVM */ 7 8/dts-v1/; 9 10#include "am4372.dtsi" 11#include <dt-bindings/pinctrl/am43xx.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/pwm/pwm.h> 14#include <dt-bindings/sound/tlv320aic31xx-micbias.h> 15 16/ { 17 model = "TI AM43x EPOS EVM"; 18 compatible = "ti,am43x-epos-evm","ti,am438x","ti,am43"; 19 20 aliases { 21 display0 = &lcd0; 22 }; 23 24 chosen { 25 stdout-path = &uart0; 26 }; 27 28 vmmcsd_fixed: fixedregulator-sd { 29 compatible = "regulator-fixed"; 30 regulator-name = "vmmcsd_fixed"; 31 regulator-min-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>; 33 enable-active-high; 34 }; 35 36 vbat: fixedregulator0 { 37 compatible = "regulator-fixed"; 38 regulator-name = "vbat"; 39 regulator-min-microvolt = <5000000>; 40 regulator-max-microvolt = <5000000>; 41 regulator-boot-on; 42 }; 43 44 lcd0: display { 45 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; 46 label = "lcd"; 47 48 backlight = <&lcd_bl>; 49 50 panel-timing { 51 clock-frequency = <33000000>; 52 hactive = <800>; 53 vactive = <480>; 54 hfront-porch = <210>; 55 hback-porch = <16>; 56 hsync-len = <30>; 57 vback-porch = <10>; 58 vfront-porch = <22>; 59 vsync-len = <13>; 60 hsync-active = <0>; 61 vsync-active = <0>; 62 de-active = <1>; 63 pixelclk-active = <1>; 64 }; 65 66 port { 67 lcd_in: endpoint { 68 remote-endpoint = <&dpi_out>; 69 }; 70 }; 71 }; 72 73 matrix_keypad: matrix_keypad0 { 74 compatible = "gpio-matrix-keypad"; 75 debounce-delay-ms = <5>; 76 col-scan-delay-us = <2>; 77 pinctrl-names = "default", "sleep"; 78 pinctrl-0 = <&matrix_keypad_default>; 79 pinctrl-1 = <&matrix_keypad_sleep>; 80 wakeup-source; 81 82 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ 83 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ 84 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ 85 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ 86 87 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ 88 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ 89 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ 90 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ 91 92 linux,keymap = <0x00000201 /* P1 */ 93 0x01000204 /* P4 */ 94 0x02000207 /* P7 */ 95 0x0300020a /* NUMERIC_STAR */ 96 0x00010202 /* P2 */ 97 0x01010205 /* P5 */ 98 0x02010208 /* P8 */ 99 0x03010200 /* P0 */ 100 0x00020203 /* P3 */ 101 0x01020206 /* P6 */ 102 0x02020209 /* P9 */ 103 0x0302020b /* NUMERIC_POUND */ 104 0x00030067 /* UP */ 105 0x0103006a /* RIGHT */ 106 0x0203006c /* DOWN */ 107 0x03030069>; /* LEFT */ 108 }; 109 110 lcd_bl: backlight { 111 compatible = "pwm-backlight"; 112 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 113 brightness-levels = <0 51 53 56 62 75 101 152 255>; 114 default-brightness-level = <8>; 115 }; 116 117 sound0: sound0 { 118 compatible = "simple-audio-card"; 119 simple-audio-card,name = "AM43-EPOS-EVM"; 120 simple-audio-card,widgets = 121 "Microphone", "Microphone Jack", 122 "Headphone", "Headphone Jack", 123 "Speaker", "Speaker"; 124 simple-audio-card,routing = 125 "MIC1LP", "Microphone Jack", 126 "MIC1RP", "Microphone Jack", 127 "MIC1LP", "MICBIAS", 128 "MIC1RP", "MICBIAS", 129 "Headphone Jack", "HPL", 130 "Headphone Jack", "HPR", 131 "Speaker", "SPL", 132 "Speaker", "SPR"; 133 simple-audio-card,format = "dsp_b"; 134 simple-audio-card,bitclock-master = <&sound0_master>; 135 simple-audio-card,frame-master = <&sound0_master>; 136 simple-audio-card,bitclock-inversion; 137 138 simple-audio-card,cpu { 139 sound-dai = <&mcasp1>; 140 system-clock-frequency = <12000000>; 141 }; 142 143 sound0_master: simple-audio-card,codec { 144 sound-dai = <&tlv320aic3111>; 145 system-clock-frequency = <12000000>; 146 }; 147 }; 148}; 149 150&am43xx_pinmux { 151 pinctrl-names = "default"; 152 pinctrl-0 = <&unused_pins>; 153 154 unused_pins: unused_pins { 155 pinctrl-single,pins = < 156 AM4372_IOPAD(0x848, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 157 AM4372_IOPAD(0x850, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 158 AM4372_IOPAD(0x858, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 159 AM4372_IOPAD(0x860, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 160 AM4372_IOPAD(0x864, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 161 AM4372_IOPAD(0x868, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 162 AM4372_IOPAD(0x86c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 163 AM4372_IOPAD(0x878, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 164 AM4372_IOPAD(0x908, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) 165 AM4372_IOPAD(0x91c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 166 AM4372_IOPAD(0x920, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 167 AM4372_IOPAD(0x9e0, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) 168 AM4372_IOPAD(0xA0c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 169 AM4372_IOPAD(0xA38, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 170 AM4372_IOPAD(0xA3c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 171 AM4372_IOPAD(0xA40, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 172 AM4372_IOPAD(0xA44, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 173 AM4372_IOPAD(0xA48, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 174 AM4372_IOPAD(0xA4c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 175 AM4372_IOPAD(0xA50, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 176 AM4372_IOPAD(0xA54, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 177 AM4372_IOPAD(0xA58, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 178 AM4372_IOPAD(0xA5c, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 179 AM4372_IOPAD(0xA60, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 180 AM4372_IOPAD(0xA64, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 181 AM4372_IOPAD(0xA68, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 182 AM4372_IOPAD(0xA6C, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 183 AM4372_IOPAD(0xA74, DS0_PIN_INPUT_PULLDOWN | PIN_INPUT_PULLDOWN | MUX_MODE7) 184 AM4372_IOPAD(0xA78, DS0_PIN_INPUT | PIN_INPUT_PULLDOWN | MUX_MODE7) 185 >; 186 }; 187 188 cpsw_default: cpsw_default { 189 pinctrl-single,pins = < 190 /* Slave 1 */ 191 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ 192 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 193 AM4372_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ 194 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ 195 AM4372_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 196 AM4372_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 197 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 198 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 199 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ 200 >; 201 }; 202 203 cpsw_sleep: cpsw_sleep { 204 pinctrl-single,pins = < 205 /* Slave 1 reset value */ 206 AM4372_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) 207 AM4372_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) 208 AM4372_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) 209 AM4372_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7) 210 AM4372_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) 211 AM4372_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) 212 AM4372_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) 213 AM4372_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) 214 AM4372_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) 215 >; 216 }; 217 218 davinci_mdio_default: davinci_mdio_default { 219 pinctrl-single,pins = < 220 /* MDIO */ 221 AM4372_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 222 AM4372_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 223 >; 224 }; 225 226 davinci_mdio_sleep: davinci_mdio_sleep { 227 pinctrl-single,pins = < 228 /* MDIO reset value */ 229 AM4372_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7) 230 AM4372_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7) 231 >; 232 }; 233 234 i2c0_pins: pinmux_i2c0_pins { 235 pinctrl-single,pins = < 236 AM4372_IOPAD(0x988, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 237 AM4372_IOPAD(0x98c, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 238 >; 239 }; 240 241 nand_flash_x8_default: nand_flash_x8_default { 242 pinctrl-single,pins = < 243 AM4372_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ 244 AM4372_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 245 AM4372_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 246 AM4372_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 247 AM4372_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 248 AM4372_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 249 AM4372_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 250 AM4372_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 251 AM4372_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 252 AM4372_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 253 AM4372_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ 254 AM4372_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 255 AM4372_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 256 AM4372_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 257 AM4372_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 258 AM4372_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 259 >; 260 }; 261 262 nand_flash_x8_sleep: nand_flash_x8_sleep { 263 pinctrl-single,pins = < 264 AM4372_IOPAD(0x840, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 265 AM4372_IOPAD(0x800, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 266 AM4372_IOPAD(0x804, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 267 AM4372_IOPAD(0x808, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 268 AM4372_IOPAD(0x80c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 269 AM4372_IOPAD(0x810, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 270 AM4372_IOPAD(0x814, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 271 AM4372_IOPAD(0x818, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 272 AM4372_IOPAD(0x81c, DS0_PIN_OUTPUT_PULLDOWN | MUX_MODE7) 273 AM4372_IOPAD(0x870, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 274 AM4372_IOPAD(0x874, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 275 AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 276 AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 277 AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 278 AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 279 AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 280 >; 281 }; 282 283 ecap0_pins_default: backlight_pins_default { 284 pinctrl-single,pins = < 285 AM4372_IOPAD(0x964, MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 286 >; 287 }; 288 289 ecap0_pins_sleep: backlight_pins_sleep { 290 pinctrl-single,pins = < 291 AM4372_IOPAD(0x964, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 292 >; 293 }; 294 295 i2c2_pins: pinmux_i2c2_pins { 296 pinctrl-single,pins = < 297 AM4372_IOPAD(0x9c0, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ 298 AM4372_IOPAD(0x9c4, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ 299 >; 300 }; 301 302 spi0_pins_default: pinmux_spi0_pins_default { 303 pinctrl-single,pins = < 304 AM4372_IOPAD(0x950, PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ 305 AM4372_IOPAD(0x954, PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ 306 AM4372_IOPAD(0x958, PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ 307 AM4372_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ 308 >; 309 }; 310 311 spi0_pins_sleep: pinmux_spi0_pins_sleep { 312 pinctrl-single,pins = < 313 AM4372_IOPAD(0x950, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 314 AM4372_IOPAD(0x954, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 315 AM4372_IOPAD(0x958, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 316 AM4372_IOPAD(0x95c, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) 317 >; 318 }; 319 320 spi1_pins_default: pinmux_spi1_pins_default { 321 pinctrl-single,pins = < 322 AM4372_IOPAD(0x990, PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ 323 AM4372_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ 324 AM4372_IOPAD(0x998, PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ 325 AM4372_IOPAD(0x99c, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ 326 >; 327 }; 328 329 spi1_pins_sleep: pinmux_spi1_pins_sleep { 330 pinctrl-single,pins = < 331 AM4372_IOPAD(0x990, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 332 AM4372_IOPAD(0x994, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 333 AM4372_IOPAD(0x998, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 334 AM4372_IOPAD(0x99c, DS0_PIN_OUTPUT_PULLDOWN | PIN_OUTPUT_PULLDOWN | MUX_MODE7) 335 >; 336 }; 337 338 mmc1_pins_default: pinmux_mmc1_pins_default { 339 pinctrl-single,pins = < 340 AM4372_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 341 >; 342 }; 343 344 mmc1_pins_sleep: pinmux_mmc1_pins_sleep { 345 pinctrl-single,pins = < 346 AM4372_IOPAD(0x960, DS0_PIN_OUTPUT_PULLUP | PIN_INPUT | MUX_MODE7) 347 >; 348 }; 349 350 matrix_keypad_default: matrix_keypad_default { 351 pinctrl-single,pins = < 352 AM4372_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* mii1_tx_clk.gpio3_9 */ 353 AM4372_IOPAD(0x930, PIN_OUTPUT | MUX_MODE7) /* mii1_rx_clk.gpio3_10 */ 354 AM4372_IOPAD(0x934, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd3.gpio2_18 */ 355 AM4372_IOPAD(0x938, PIN_OUTPUT | MUX_MODE7) /* mii1_rxd2.gpio2_19 */ 356 AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn.gpio0_12 */ 357 AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn.gpio0_13 */ 358 AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_rxd.gpio0_14 */ 359 AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_txd.gpio0_15 */ 360 >; 361 }; 362 363 matrix_keypad_sleep: matrix_keypad_sleep { 364 pinctrl-single,pins = < 365 AM4372_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE7) 366 AM4372_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE7) 367 AM4372_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE7) 368 AM4372_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE7) 369 AM4372_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) 370 AM4372_IOPAD(0x97C, PIN_INPUT_PULLDOWN | MUX_MODE7) 371 AM4372_IOPAD(0x980, PIN_INPUT_PULLDOWN | MUX_MODE7) 372 AM4372_IOPAD(0x984, PIN_INPUT_PULLDOWN | MUX_MODE7) 373 >; 374 }; 375 376 qspi1_pins_default: qspi1_pins_default { 377 pinctrl-single,pins = < 378 AM4372_IOPAD(0x87c, PIN_INPUT_PULLUP | MUX_MODE3) 379 AM4372_IOPAD(0x888, PIN_INPUT_PULLUP | MUX_MODE2) 380 AM4372_IOPAD(0x890, PIN_INPUT_PULLUP | MUX_MODE3) 381 AM4372_IOPAD(0x894, PIN_INPUT_PULLUP | MUX_MODE3) 382 AM4372_IOPAD(0x898, PIN_INPUT_PULLUP | MUX_MODE3) 383 AM4372_IOPAD(0x89c, PIN_INPUT_PULLUP | MUX_MODE3) 384 >; 385 }; 386 387 qspi1_pins_sleep: qspi1_pins_sleep { 388 pinctrl-single,pins = < 389 AM4372_IOPAD(0x87c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 390 AM4372_IOPAD(0x888, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 391 AM4372_IOPAD(0x890, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 392 AM4372_IOPAD(0x894, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 393 AM4372_IOPAD(0x898, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 394 AM4372_IOPAD(0x89c, DS0_PIN_OUTPUT_PULLUP | MUX_MODE7) 395 >; 396 }; 397 398 pixcir_ts_pins_default: pixcir_ts_pins_default { 399 pinctrl-single,pins = < 400 AM4372_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ 401 >; 402 }; 403 404 pixcir_ts_pins_sleep: pixcir_ts_pins_sleep { 405 pinctrl-single,pins = < 406 AM4372_IOPAD(0x844, DS0_PIN_OUTPUT_PULLUP | PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ 407 >; 408 }; 409 410 hdq_pins: pinmux_hdq_pins { 411 pinctrl-single,pins = < 412 AM4372_IOPAD(0xa34, PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ 413 >; 414 }; 415 416 dss_pins: dss_pins { 417 pinctrl-single,pins = < 418 AM4372_IOPAD(0x820, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ 419 AM4372_IOPAD(0x824, PIN_OUTPUT_PULLUP | MUX_MODE1) 420 AM4372_IOPAD(0x828, PIN_OUTPUT_PULLUP | MUX_MODE1) 421 AM4372_IOPAD(0x82c, PIN_OUTPUT_PULLUP | MUX_MODE1) 422 AM4372_IOPAD(0x830, PIN_OUTPUT_PULLUP | MUX_MODE1) 423 AM4372_IOPAD(0x834, PIN_OUTPUT_PULLUP | MUX_MODE1) 424 AM4372_IOPAD(0x838, PIN_OUTPUT_PULLUP | MUX_MODE1) 425 AM4372_IOPAD(0x83c, PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ 426 AM4372_IOPAD(0x8a0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 427 AM4372_IOPAD(0x8a4, PIN_OUTPUT_PULLUP | MUX_MODE0) 428 AM4372_IOPAD(0x8a8, PIN_OUTPUT_PULLUP | MUX_MODE0) 429 AM4372_IOPAD(0x8ac, PIN_OUTPUT_PULLUP | MUX_MODE0) 430 AM4372_IOPAD(0x8b0, PIN_OUTPUT_PULLUP | MUX_MODE0) 431 AM4372_IOPAD(0x8b4, PIN_OUTPUT_PULLUP | MUX_MODE0) 432 AM4372_IOPAD(0x8B8, PIN_OUTPUT_PULLUP | MUX_MODE0) 433 AM4372_IOPAD(0x8bc, PIN_OUTPUT_PULLUP | MUX_MODE0) 434 AM4372_IOPAD(0x8c0, PIN_OUTPUT_PULLUP | MUX_MODE0) 435 AM4372_IOPAD(0x8c4, PIN_OUTPUT_PULLUP | MUX_MODE0) 436 AM4372_IOPAD(0x8c8, PIN_OUTPUT_PULLUP | MUX_MODE0) 437 AM4372_IOPAD(0x8cc, PIN_OUTPUT_PULLUP | MUX_MODE0) 438 AM4372_IOPAD(0x8d0, PIN_OUTPUT_PULLUP | MUX_MODE0) 439 AM4372_IOPAD(0x8d4, PIN_OUTPUT_PULLUP | MUX_MODE0) 440 AM4372_IOPAD(0x8d8, PIN_OUTPUT_PULLUP | MUX_MODE0) 441 AM4372_IOPAD(0x8dc, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 442 AM4372_IOPAD(0x8e0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 443 AM4372_IOPAD(0x8e4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 444 AM4372_IOPAD(0x8e8, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 445 AM4372_IOPAD(0x8ec, PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 446 >; 447 }; 448 449 display_mux_pins: display_mux_pins { 450 pinctrl-single,pins = < 451 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ 452 AM4372_IOPAD(0x88C, PIN_OUTPUT_PULLUP | MUX_MODE7) 453 >; 454 }; 455 456 vpfe1_pins_default: vpfe1_pins_default { 457 pinctrl-single,pins = < 458 AM4372_IOPAD(0x9cc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ 459 AM4372_IOPAD(0x9d0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ 460 AM4372_IOPAD(0x9d4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ 461 AM4372_IOPAD(0x9d8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ 462 AM4372_IOPAD(0x9dc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ 463 AM4372_IOPAD(0x9e8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ 464 AM4372_IOPAD(0x9ec, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ 465 AM4372_IOPAD(0x9f0, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ 466 AM4372_IOPAD(0x9f4, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ 467 AM4372_IOPAD(0x9f8, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ 468 AM4372_IOPAD(0x9fc, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ 469 AM4372_IOPAD(0xa00, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ 470 AM4372_IOPAD(0xa04, PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ 471 >; 472 }; 473 474 vpfe1_pins_sleep: vpfe1_pins_sleep { 475 pinctrl-single,pins = < 476 AM4372_IOPAD(0x9cc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 477 AM4372_IOPAD(0x9d0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 478 AM4372_IOPAD(0x9d4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 479 AM4372_IOPAD(0x9d8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 480 AM4372_IOPAD(0x9dc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 481 AM4372_IOPAD(0x9e8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 482 AM4372_IOPAD(0x9ec, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 483 AM4372_IOPAD(0x9f0, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 484 AM4372_IOPAD(0x9f4, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 485 AM4372_IOPAD(0x9f8, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 486 AM4372_IOPAD(0x9fc, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 487 AM4372_IOPAD(0xa00, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 488 AM4372_IOPAD(0xa04, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 489 >; 490 }; 491 492 uart0_pins_default: uart0_pins_default { 493 pinctrl-single,pins = < 494 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_ctsn.uart0_ctsn */ 495 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE0) /* uart0_rtsn.uart0_rtsn */ 496 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 497 AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) /* uart0_txd.uart0_txd */ 498 >; 499 }; 500 501 uart0_pins_sleep: uart0_pins_sleep { 502 pinctrl-single,pins = < 503 AM4372_IOPAD(0x968, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 504 AM4372_IOPAD(0x96C, DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 505 AM4372_IOPAD(0x970, PIN_INPUT_PULLUP | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) 506 AM4372_IOPAD(0x974, PIN_INPUT | SLEWCTRL_FAST | DS0_PULL_UP_DOWN_EN | MUX_MODE0) 507 >; 508 }; 509 510 usb2_phy1_default: usb2_phy1_default { 511 pinctrl-single,pins = < 512 AM4372_IOPAD(0xac0, PIN_INPUT_PULLDOWN | MUX_MODE0) 513 >; 514 }; 515 516 usb2_phy1_sleep: usb2_phy1_sleep { 517 pinctrl-single,pins = < 518 AM4372_IOPAD(0xac0, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) 519 >; 520 }; 521 522 usb2_phy2_default: usb2_phy2_default { 523 pinctrl-single,pins = < 524 AM4372_IOPAD(0xac4, PIN_INPUT_PULLDOWN | MUX_MODE0) 525 >; 526 }; 527 528 usb2_phy2_sleep: usb2_phy2_sleep { 529 pinctrl-single,pins = < 530 AM4372_IOPAD(0xac4, DS0_PULL_UP_DOWN_EN | PIN_INPUT_PULLDOWN | MUX_MODE7) 531 >; 532 }; 533 534 mcasp1_pins: mcasp1_pins { 535 pinctrl-single,pins = < 536 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_ACLKR/MCASP1_ACLKX */ 537 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_FSR/MCASP1_FSX */ 538 AM4372_IOPAD(0x9a8, PIN_OUTPUT_PULLDOWN | MUX_MODE3)/* MCASP0_AXR1/MCASP1_AXR0 */ 539 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE3) /* MCASP0_AHCLKX/MCASP1_AXR1 */ 540 >; 541 }; 542 543 mcasp1_sleep_pins: mcasp1_sleep_pins { 544 pinctrl-single,pins = < 545 AM4372_IOPAD(0x9a0, PIN_INPUT_PULLDOWN | MUX_MODE7) 546 AM4372_IOPAD(0x9a4, PIN_INPUT_PULLDOWN | MUX_MODE7) 547 AM4372_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7) 548 AM4372_IOPAD(0x9ac, PIN_INPUT_PULLDOWN | MUX_MODE7) 549 >; 550 }; 551}; 552 553&mmc1 { 554 status = "okay"; 555 vmmc-supply = <&vmmcsd_fixed>; 556 bus-width = <4>; 557 pinctrl-names = "default", "sleep"; 558 pinctrl-0 = <&mmc1_pins_default>; 559 pinctrl-1 = <&mmc1_pins_sleep>; 560 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 561}; 562 563&mac { 564 pinctrl-names = "default", "sleep"; 565 pinctrl-0 = <&cpsw_default>; 566 pinctrl-1 = <&cpsw_sleep>; 567 status = "okay"; 568 slaves = <1>; 569}; 570 571&davinci_mdio { 572 pinctrl-names = "default", "sleep"; 573 pinctrl-0 = <&davinci_mdio_default>; 574 pinctrl-1 = <&davinci_mdio_sleep>; 575 status = "okay"; 576 577 ethphy0: ethernet-phy@16 { 578 reg = <16>; 579 }; 580}; 581 582&cpsw_emac0 { 583 phy-handle = <ðphy0>; 584 phy-mode = "rmii"; 585 phys = <&phy_gmii_sel 1 1>; 586}; 587 588&i2c0 { 589 status = "okay"; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&i2c0_pins>; 592 clock-frequency = <400000>; 593 594 tps65218: tps65218@24 { 595 reg = <0x24>; 596 compatible = "ti,tps65218"; 597 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* NMIn */ 598 interrupt-controller; 599 #interrupt-cells = <2>; 600 601 dcdc1: regulator-dcdc1 { 602 regulator-name = "vdd_core"; 603 regulator-min-microvolt = <912000>; 604 regulator-max-microvolt = <1144000>; 605 regulator-boot-on; 606 regulator-always-on; 607 }; 608 609 dcdc2: regulator-dcdc2 { 610 regulator-name = "vdd_mpu"; 611 regulator-min-microvolt = <912000>; 612 regulator-max-microvolt = <1378000>; 613 regulator-boot-on; 614 regulator-always-on; 615 }; 616 617 dcdc3: regulator-dcdc3 { 618 regulator-name = "vdcdc3"; 619 regulator-boot-on; 620 regulator-always-on; 621 regulator-state-mem { 622 regulator-on-in-suspend; 623 }; 624 regulator-state-disk { 625 regulator-off-in-suspend; 626 }; 627 }; 628 629 dcdc4: regulator-dcdc4 { 630 regulator-name = "vdcdc4"; 631 regulator-min-microvolt = <3300000>; 632 regulator-max-microvolt = <3300000>; 633 regulator-boot-on; 634 regulator-always-on; 635 }; 636 637 dcdc5: regulator-dcdc5 { 638 regulator-name = "v1_0bat"; 639 regulator-min-microvolt = <1000000>; 640 regulator-max-microvolt = <1000000>; 641 regulator-boot-on; 642 regulator-always-on; 643 }; 644 645 dcdc6: regulator-dcdc6 { 646 regulator-name = "v1_8bat"; 647 regulator-min-microvolt = <1800000>; 648 regulator-max-microvolt = <1800000>; 649 regulator-boot-on; 650 regulator-always-on; 651 }; 652 653 ldo1: regulator-ldo1 { 654 regulator-min-microvolt = <1800000>; 655 regulator-max-microvolt = <1800000>; 656 regulator-boot-on; 657 regulator-always-on; 658 }; 659 }; 660 661 at24@50 { 662 compatible = "atmel,24c256"; 663 pagesize = <64>; 664 reg = <0x50>; 665 }; 666 667 pixcir_ts@5c { 668 compatible = "pixcir,pixcir_tangoc"; 669 pinctrl-names = "default", "sleep"; 670 pinctrl-0 = <&pixcir_ts_pins_default>; 671 pinctrl-1 = <&pixcir_ts_pins_sleep>; 672 673 reg = <0x5c>; 674 interrupt-parent = <&gpio1>; 675 interrupts = <17 IRQ_TYPE_EDGE_FALLING>; 676 677 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 678 679 touchscreen-size-x = <1024>; 680 touchscreen-size-y = <600>; 681 }; 682 683 tlv320aic3111: tlv320aic3111@18 { 684 #sound-dai-cells = <0>; 685 compatible = "ti,tlv320aic3111"; 686 reg = <0x18>; 687 status = "okay"; 688 689 ai31xx-micbias-vg = <MICBIAS_2_0V>; 690 691 /* Regulators */ 692 HPVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ 693 SPRVDD-supply = <&vbat>; /* vbat */ 694 SPLVDD-supply = <&vbat>; /* vbat */ 695 AVDD-supply = <&dcdc4>; /* v3_3AUD -> V3_3D -> DCDC4 */ 696 IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */ 697 DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */ 698 }; 699}; 700 701&i2c2 { 702 pinctrl-names = "default"; 703 pinctrl-0 = <&i2c2_pins>; 704 status = "okay"; 705}; 706 707&gpio0 { 708 status = "okay"; 709}; 710 711&gpio1 { 712 status = "okay"; 713}; 714 715&gpio2 { 716 pinctrl-names = "default"; 717 pinctrl-0 = <&display_mux_pins>; 718 status = "okay"; 719 720 p1 { 721 /* 722 * SelLCDorHDMI selects between display and audio paths: 723 * Low: HDMI display with audio via HDMI 724 * High: LCD display with analog audio via aic3111 codec 725 */ 726 gpio-hog; 727 gpios = <1 GPIO_ACTIVE_HIGH>; 728 output-high; 729 line-name = "SelLCDorHDMI"; 730 }; 731}; 732 733&gpio3 { 734 status = "okay"; 735}; 736 737&elm { 738 status = "okay"; 739}; 740 741&gpmc { 742 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 743 pinctrl-names = "default", "sleep"; 744 pinctrl-0 = <&nand_flash_x8_default>; 745 pinctrl-1 = <&nand_flash_x8_sleep>; 746 ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */ 747 nand@0,0 { 748 compatible = "ti,omap2-nand"; 749 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 750 interrupt-parent = <&gpmc>; 751 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 752 <1 IRQ_TYPE_NONE>; /* termcount */ 753 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 754 ti,nand-xfer-type = "prefetch-dma"; 755 ti,nand-ecc-opt = "bch16"; 756 ti,elm-id = <&elm>; 757 nand-bus-width = <8>; 758 gpmc,device-width = <1>; 759 gpmc,sync-clk-ps = <0>; 760 gpmc,cs-on-ns = <0>; 761 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ 762 gpmc,cs-wr-off-ns = <40>; 763 gpmc,adv-on-ns = <0>; /* cs-on-ns */ 764 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ 765 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ 766 gpmc,we-on-ns = <0>; /* cs-on-ns */ 767 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ 768 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ 769 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ 770 gpmc,access-ns = <30>; /* tCEA + 4*/ 771 gpmc,rd-cycle-ns = <40>; 772 gpmc,wr-cycle-ns = <40>; 773 gpmc,bus-turnaround-ns = <0>; 774 gpmc,cycle2cycle-delay-ns = <0>; 775 gpmc,clk-activation-ns = <0>; 776 gpmc,wr-access-ns = <40>; 777 gpmc,wr-data-mux-bus-ns = <0>; 778 /* MTD partition table */ 779 /* All SPL-* partitions are sized to minimal length 780 * which can be independently programmable. For 781 * NAND flash this is equal to size of erase-block */ 782 #address-cells = <1>; 783 #size-cells = <1>; 784 partition@0 { 785 label = "NAND.SPL"; 786 reg = <0x00000000 0x00040000>; 787 }; 788 partition@1 { 789 label = "NAND.SPL.backup1"; 790 reg = <0x00040000 0x00040000>; 791 }; 792 partition@2 { 793 label = "NAND.SPL.backup2"; 794 reg = <0x00080000 0x00040000>; 795 }; 796 partition@3 { 797 label = "NAND.SPL.backup3"; 798 reg = <0x000C0000 0x00040000>; 799 }; 800 partition@4 { 801 label = "NAND.u-boot-spl-os"; 802 reg = <0x00100000 0x00080000>; 803 }; 804 partition@5 { 805 label = "NAND.u-boot"; 806 reg = <0x00180000 0x00100000>; 807 }; 808 partition@6 { 809 label = "NAND.u-boot-env"; 810 reg = <0x00280000 0x00040000>; 811 }; 812 partition@7 { 813 label = "NAND.u-boot-env.backup1"; 814 reg = <0x002C0000 0x00040000>; 815 }; 816 partition@8 { 817 label = "NAND.kernel"; 818 reg = <0x00300000 0x00700000>; 819 }; 820 partition@9 { 821 label = "NAND.file-system"; 822 reg = <0x00a00000 0x1f600000>; 823 }; 824 }; 825}; 826 827&epwmss0 { 828 status = "okay"; 829}; 830 831&tscadc { 832 status = "okay"; 833 834 adc { 835 ti,adc-channels = <0 1 2 3 4 5 6 7>; 836 }; 837}; 838 839&ecap0 { 840 status = "okay"; 841 pinctrl-names = "default", "sleep"; 842 pinctrl-0 = <&ecap0_pins_default>; 843 pinctrl-1 = <&ecap0_pins_sleep>; 844}; 845 846&spi0 { 847 status = "okay"; 848 pinctrl-names = "default", "sleep"; 849 pinctrl-0 = <&spi0_pins_default>; 850 pinctrl-1 = <&spi0_pins_sleep>; 851}; 852 853&spi1 { 854 status = "okay"; 855 pinctrl-names = "default", "sleep"; 856 pinctrl-0 = <&spi1_pins_default>; 857 pinctrl-1 = <&spi1_pins_sleep>; 858}; 859 860&usb2_phy1 { 861 status = "okay"; 862 pinctrl-names = "default", "sleep"; 863 pinctrl-0 = <&usb2_phy1_default>; 864 pinctrl-1 = <&usb2_phy1_sleep>; 865}; 866 867&usb1 { 868 dr_mode = "otg"; 869 status = "okay"; 870}; 871 872&usb2_phy2 { 873 status = "okay"; 874 pinctrl-names = "default", "sleep"; 875 pinctrl-0 = <&usb2_phy2_default>; 876 pinctrl-1 = <&usb2_phy2_sleep>; 877}; 878 879&usb2 { 880 dr_mode = "host"; 881 status = "okay"; 882}; 883 884&qspi { 885 status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ 886 pinctrl-names = "default", "sleep"; 887 pinctrl-0 = <&qspi1_pins_default>; 888 pinctrl-1 = <&qspi1_pins_sleep>; 889 890 spi-max-frequency = <48000000>; 891 m25p80@0 { 892 compatible = "mx66l51235l"; 893 spi-max-frequency = <48000000>; 894 reg = <0>; 895 spi-cpol; 896 spi-cpha; 897 spi-tx-bus-width = <1>; 898 spi-rx-bus-width = <4>; 899 #address-cells = <1>; 900 #size-cells = <1>; 901 902 /* MTD partition table. 903 * The ROM checks the first 512KiB 904 * for a valid file to boot(XIP). 905 */ 906 partition@0 { 907 label = "QSPI.U_BOOT"; 908 reg = <0x00000000 0x000080000>; 909 }; 910 partition@1 { 911 label = "QSPI.U_BOOT.backup"; 912 reg = <0x00080000 0x00080000>; 913 }; 914 partition@2 { 915 label = "QSPI.U-BOOT-SPL_OS"; 916 reg = <0x00100000 0x00010000>; 917 }; 918 partition@3 { 919 label = "QSPI.U_BOOT_ENV"; 920 reg = <0x00110000 0x00010000>; 921 }; 922 partition@4 { 923 label = "QSPI.U-BOOT-ENV.backup"; 924 reg = <0x00120000 0x00010000>; 925 }; 926 partition@5 { 927 label = "QSPI.KERNEL"; 928 reg = <0x00130000 0x0800000>; 929 }; 930 partition@6 { 931 label = "QSPI.FILESYSTEM"; 932 reg = <0x00930000 0x36D0000>; 933 }; 934 }; 935}; 936 937&hdq { 938 status = "okay"; 939 pinctrl-names = "default"; 940 pinctrl-0 = <&hdq_pins>; 941}; 942 943&dss { 944 status = "ok"; 945 946 pinctrl-names = "default"; 947 pinctrl-0 = <&dss_pins>; 948 949 port { 950 dpi_out: endpoint { 951 remote-endpoint = <&lcd_in>; 952 data-lines = <24>; 953 }; 954 }; 955}; 956 957&vpfe1 { 958 status = "okay"; 959 pinctrl-names = "default", "sleep"; 960 pinctrl-0 = <&vpfe1_pins_default>; 961 pinctrl-1 = <&vpfe1_pins_sleep>; 962 963 port { 964 vpfe1_ep: endpoint { 965 /* remote-endpoint = <&sensor>; add once we have it */ 966 ti,am437x-vpfe-interface = <0>; 967 bus-width = <8>; 968 hsync-active = <0>; 969 vsync-active = <0>; 970 }; 971 }; 972}; 973 974&uart0 { 975 status = "okay"; 976 pinctrl-names = "default", "sleep"; 977 pinctrl-0 = <&uart0_pins_default>; 978 pinctrl-1 = <&uart0_pins_sleep>; 979}; 980 981&mcasp1 { 982 #sound-dai-cells = <0>; 983 pinctrl-names = "default", "sleep"; 984 pinctrl-0 = <&mcasp1_pins>; 985 pinctrl-1 = <&mcasp1_sleep_pins>; 986 987 status = "okay"; 988 989 op-mode = <0>; /* MCASP_IIS_MODE */ 990 tdm-slots = <2>; 991 /* 4 serializer */ 992 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 993 1 2 0 0 994 >; 995 tx-num-evt = <32>; 996 rx-num-evt = <32>; 997}; 998 999&mux_synctimer32k_ck { 1000 assigned-clocks = <&mux_synctimer32k_ck>; 1001 assigned-clock-parents = <&clkdiv32k_ick>; 1002}; 1003 1004&cpu { 1005 cpu0-supply = <&dcdc2>; 1006}; 1007
