1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/ 4 */ 5/dts-v1/; 6 7#include "am33xx.dtsi" 8 9/ { 10 model = "Newflow AM335x NanoBone"; 11 compatible = "ti,am33xx"; 12 13 cpus { 14 cpu@0 { 15 cpu0-supply = <&dcdc2_reg>; 16 }; 17 }; 18 19 memory@80000000 { 20 device_type = "memory"; 21 reg = <0x80000000 0x10000000>; /* 256 MB */ 22 }; 23 24 leds { 25 compatible = "gpio-leds"; 26 27 led0 { 28 label = "nanobone:green:usr1"; 29 gpios = <&gpio1 5 0>; 30 default-state = "off"; 31 }; 32 }; 33}; 34 35&am33xx_pinmux { 36 pinctrl-names = "default"; 37 pinctrl-0 = <&misc_pins>; 38 39 misc_pins: misc_pins { 40 pinctrl-single,pins = < 41 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7) /* spi0_cs0.gpio0_5 */ 42 >; 43 }; 44 45 gpmc_pins: gpmc_pins { 46 pinctrl-single,pins = < 47 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) 48 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) 49 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) 50 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) 51 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) 52 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) 53 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) 54 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) 55 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLUP, MUX_MODE0) 56 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLUP, MUX_MODE0) 57 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLUP, MUX_MODE0) 58 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLUP, MUX_MODE0) 59 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE0) 60 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE0) 61 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLUP, MUX_MODE0) 62 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE0) 63 64 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) 65 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) 66 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE0) 67 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_OUTPUT, MUX_MODE0) 68 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT, MUX_MODE0) 69 70 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) 71 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) 72 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) 73 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) 74 75 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE1) /* lcd_data1.gpmc_a1 */ 76 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE1) /* lcd_data2.gpmc_a2 */ 77 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE1) /* lcd_data3.gpmc_a3 */ 78 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE1) /* lcd_data4.gpmc_a4 */ 79 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE1) /* lcd_data5.gpmc_a5 */ 80 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE1) /* lcd_data6.gpmc_a6 */ 81 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE1) /* lcd_data7.gpmc_a7 */ 82 83 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_vsync.gpmc_a8 */ 84 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE1) /* lcd_hsync.gpmc_a9 */ 85 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE1) /* lcd_pclk.gpmc_a10 */ 86 >; 87 }; 88 89 i2c0_pins: i2c0_pins { 90 pinctrl-single,pins = < 91 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE0) 92 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLDOWN, MUX_MODE0) 93 >; 94 }; 95 96 uart0_pins: uart0_pins { 97 pinctrl-single,pins = < 98 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 99 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0) 100 >; 101 }; 102 103 uart1_pins: uart1_pins { 104 pinctrl-single,pins = < 105 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE7) 106 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE7) 107 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 108 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0) 109 >; 110 }; 111 112 uart2_pins: uart2_pins { 113 pinctrl-single,pins = < 114 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data8.gpio2[14] */ 115 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7) /* lcd_data9.gpio2[15] */ 116 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd */ 117 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd */ 118 >; 119 }; 120 121 uart3_pins: uart3_pins { 122 pinctrl-single,pins = < 123 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */ 124 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */ 125 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ 126 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ 127 >; 128 }; 129 130 uart4_pins: uart4_pins { 131 pinctrl-single,pins = < 132 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */ 133 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */ 134 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ 135 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ 136 >; 137 }; 138 139 uart5_pins: uart5_pins { 140 pinctrl-single,pins = < 141 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_INPUT, MUX_MODE4) /* lcd_data14.uart5_rxd */ 142 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT, MUX_MODE3) /* rmiii1_refclk.uart5_txd */ 143 >; 144 }; 145 146 mmc1_pins: mmc1_pins { 147 pinctrl-single,pins = < 148 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 149 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 150 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 151 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 152 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_clk.mmc0_clk */ 153 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) /* mmc0_cmd.mmc0_cmd */ 154 AM33XX_PADCONF(AM335X_PIN_EMU1, PIN_INPUT_PULLUP, MUX_MODE7) /* emu1.gpio3[8] */ 155 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */ 156 >; 157 }; 158}; 159 160&uart0 { 161 pinctrl-names = "default"; 162 pinctrl-0 = <&uart0_pins>; 163 status = "okay"; 164}; 165 166&uart1 { 167 pinctrl-names = "default"; 168 pinctrl-0 = <&uart1_pins>; 169 status = "okay"; 170 rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>; 171 rs485-rts-active-high; 172 rs485-rx-during-tx; 173 rs485-rts-delay = <1 1>; 174 linux,rs485-enabled-at-boot-time; 175}; 176 177&uart2 { 178 pinctrl-names = "default"; 179 pinctrl-0 = <&uart2_pins>; 180 status = "okay"; 181 rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>; 182 rs485-rts-active-high; 183 rs485-rts-delay = <1 1>; 184 linux,rs485-enabled-at-boot-time; 185}; 186 187&uart3 { 188 pinctrl-names = "default"; 189 pinctrl-0 = <&uart3_pins>; 190 status = "okay"; 191}; 192 193&uart4 { 194 pinctrl-names = "default"; 195 pinctrl-0 = <&uart4_pins>; 196 status = "okay"; 197}; 198 199&uart5 { 200 pinctrl-names = "default"; 201 pinctrl-0 = <&uart5_pins>; 202 status = "okay"; 203}; 204 205&i2c0 { 206 status = "okay"; 207 pinctrl-names = "default"; 208 clock-frequency = <400000>; 209 pinctrl-names = "default"; 210 pinctrl-0 = <&i2c0_pins>; 211 212 gpio@20 { 213 compatible = "microchip,mcp23017"; 214 gpio-controller; 215 #gpio-cells = <2>; 216 reg = <0x20>; 217 }; 218 219 tps: tps@24 { 220 reg = <0x24>; 221 }; 222 223 eeprom@53 { 224 compatible = "microchip,24c02", "atmel,24c02"; 225 reg = <0x53>; 226 pagesize = <8>; 227 }; 228 229 rtc@68 { 230 compatible = "dallas,ds1307"; 231 reg = <0x68>; 232 }; 233}; 234 235&elm { 236 status = "okay"; 237}; 238 239&gpmc { 240 compatible = "ti,am3352-gpmc"; 241 ti,hwmods = "gpmc"; 242 status = "okay"; 243 gpmc,num-waitpins = <2>; 244 pinctrl-names = "default"; 245 pinctrl-0 = <&gpmc_pins>; 246 247 #address-cells = <2>; 248 #size-cells = <1>; 249 ranges = <0 0 0x08000000 0x08000000>, /* CS0: NOR 128M */ 250 <1 0 0x1c000000 0x01000000>; /* CS1: FRAM 16M */ 251 252 nor@0,0 { 253 reg = <0 0x00000000 0x08000000>; 254 compatible = "cfi-flash"; 255 linux,mtd-name = "spansion,s29gl010p11t"; 256 bank-width = <2>; 257 258 gpmc,mux-add-data = <2>; 259 260 gpmc,sync-clk-ps = <0>; 261 gpmc,cs-on-ns = <0>; 262 gpmc,cs-rd-off-ns = <160>; 263 gpmc,cs-wr-off-ns = <160>; 264 gpmc,adv-on-ns = <10>; 265 gpmc,adv-rd-off-ns = <30>; 266 gpmc,adv-wr-off-ns = <30>; 267 gpmc,oe-on-ns = <40>; 268 gpmc,oe-off-ns = <160>; 269 gpmc,we-on-ns = <40>; 270 gpmc,we-off-ns = <160>; 271 gpmc,rd-cycle-ns = <160>; 272 gpmc,wr-cycle-ns = <160>; 273 gpmc,access-ns = <150>; 274 gpmc,page-burst-access-ns = <10>; 275 gpmc,cycle2cycle-samecsen; 276 gpmc,cycle2cycle-delay-ns = <20>; 277 gpmc,wr-data-mux-bus-ns = <70>; 278 gpmc,wr-access-ns = <80>; 279 280 #address-cells = <1>; 281 #size-cells = <1>; 282 283 /* 284 MTD partition table 285 =================== 286 +------------+-->0x00000000-> U-Boot start 287 | | 288 | |-->0x000BFFFF-> U-Boot end 289 | |-->0x000C0000-> ENV1 start 290 | | 291 | |-->0x000DFFFF-> ENV1 end 292 | |-->0x000E0000-> ENV2 start 293 | | 294 | |-->0x000FFFFF-> ENV2 end 295 | |-->0x00100000-> Kernel start 296 | | 297 | |-->0x004FFFFF-> Kernel end 298 | |-->0x00500000-> File system start 299 | | 300 | |-->0x01FFFFFF-> File system end 301 | |-->0x02000000-> User data start 302 | | 303 | |-->0x03FFFFFF-> User data end 304 | |-->0x04000000-> Data storage start 305 | | 306 +------------+-->0x08000000-> NOR end (Free end) 307 */ 308 partition@0 { 309 label = "boot"; 310 reg = <0x00000000 0x000c0000>; /* 768KB */ 311 }; 312 313 partition@1 { 314 label = "env1"; 315 reg = <0x000c0000 0x00020000>; /* 128KB */ 316 }; 317 318 partition@2 { 319 label = "env2"; 320 reg = <0x000e0000 0x00020000>; /* 128KB */ 321 }; 322 323 partition@3 { 324 label = "kernel"; 325 reg = <0x00100000 0x00400000>; /* 4MB */ 326 }; 327 328 partition@4 { 329 label = "rootfs"; 330 reg = <0x00500000 0x01b00000>; /* 27MB */ 331 }; 332 333 partition@5 { 334 label = "user"; 335 reg = <0x02000000 0x02000000>; /* 32MB */ 336 }; 337 338 partition@6 { 339 label = "data"; 340 reg = <0x04000000 0x04000000>; /* 64MB */ 341 }; 342 }; 343 344 fram@1,0 { 345 reg = <1 0x00000000 0x01000000>; 346 bank-width = <2>; 347 348 gpmc,mux-add-data = <2>; 349 350 gpmc,sync-clk-ps = <0>; 351 gpmc,cs-on-ns = <0>; 352 gpmc,cs-rd-off-ns = <160>; 353 gpmc,cs-wr-off-ns = <160>; 354 gpmc,adv-on-ns = <10>; 355 gpmc,adv-rd-off-ns = <20>; 356 gpmc,adv-wr-off-ns = <20>; 357 gpmc,oe-on-ns = <30>; 358 gpmc,oe-off-ns = <150>; 359 gpmc,we-on-ns = <30>; 360 gpmc,we-off-ns = <150>; 361 gpmc,rd-cycle-ns = <160>; 362 gpmc,wr-cycle-ns = <160>; 363 gpmc,access-ns = <130>; 364 gpmc,page-burst-access-ns = <10>; 365 gpmc,cycle2cycle-samecsen; 366 gpmc,cycle2cycle-diffcsen; 367 gpmc,cycle2cycle-delay-ns = <10>; 368 gpmc,wr-data-mux-bus-ns = <30>; 369 gpmc,wr-access-ns = <0>; 370 }; 371}; 372 373&mac { 374 dual_emac; 375 status = "okay"; 376}; 377 378&davinci_mdio { 379 status = "okay"; 380 381 ethphy0: ethernet-phy@0 { 382 reg = <0>; 383 }; 384 385 ethphy1: ethernet-phy@1 { 386 reg = <1>; 387 }; 388}; 389 390&cpsw_emac0 { 391 phy-handle = <ðphy0>; 392 phy-mode = "mii"; 393 dual_emac_res_vlan = <1>; 394}; 395 396&cpsw_emac1 { 397 phy-handle = <ðphy1>; 398 phy-mode = "mii"; 399 dual_emac_res_vlan = <2>; 400}; 401 402&mmc1 { 403 status = "okay"; 404 vmmc-supply = <&ldo4_reg>; 405 pinctrl-names = "default"; 406 pinctrl-0 = <&mmc1_pins>; 407 bus-width = <4>; 408 cd-gpios = <&gpio3 8 0>; 409 wp-gpios = <&gpio3 18 0>; 410}; 411 412#include "tps65217.dtsi" 413 414&tps { 415 regulators { 416 dcdc1_reg: regulator@0 { 417 /* +1.5V voltage with ±4% tolerance */ 418 regulator-min-microvolt = <1450000>; 419 regulator-max-microvolt = <1550000>; 420 regulator-boot-on; 421 regulator-always-on; 422 }; 423 424 dcdc2_reg: regulator@1 { 425 /* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */ 426 regulator-name = "vdd_mpu"; 427 regulator-min-microvolt = <915000>; 428 regulator-max-microvolt = <1140000>; 429 regulator-boot-on; 430 regulator-always-on; 431 }; 432 433 dcdc3_reg: regulator@2 { 434 /* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */ 435 regulator-name = "vdd_core"; 436 regulator-min-microvolt = <915000>; 437 regulator-max-microvolt = <1140000>; 438 regulator-boot-on; 439 regulator-always-on; 440 }; 441 442 ldo1_reg: regulator@3 { 443 /* +1.8V voltage with ±4% tolerance */ 444 regulator-min-microvolt = <1750000>; 445 regulator-max-microvolt = <1870000>; 446 regulator-boot-on; 447 regulator-always-on; 448 }; 449 450 ldo2_reg: regulator@4 { 451 /* +3.3V voltage with ±4% tolerance */ 452 regulator-min-microvolt = <3175000>; 453 regulator-max-microvolt = <3430000>; 454 regulator-boot-on; 455 regulator-always-on; 456 }; 457 458 ldo3_reg: regulator@5 { 459 /* +1.8V voltage with ±4% tolerance */ 460 regulator-min-microvolt = <1750000>; 461 regulator-max-microvolt = <1870000>; 462 regulator-boot-on; 463 regulator-always-on; 464 }; 465 466 ldo4_reg: regulator@6 { 467 /* +3.3V voltage with ±4% tolerance */ 468 regulator-min-microvolt = <3175000>; 469 regulator-max-microvolt = <3430000>; 470 regulator-boot-on; 471 regulator-always-on; 472 }; 473 }; 474}; 475
