1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 4 */ 5/dts-v1/; 6 7#include "am33xx.dtsi" 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 model = "TI AM335x EVM"; 12 compatible = "ti,am335x-evm", "ti,am33xx"; 13 14 cpus { 15 cpu@0 { 16 cpu0-supply = <&vdd1_reg>; 17 }; 18 }; 19 20 memory@80000000 { 21 device_type = "memory"; 22 reg = <0x80000000 0x10000000>; /* 256 MB */ 23 }; 24 25 chosen { 26 stdout-path = &uart0; 27 }; 28 29 vbat: fixedregulator0 { 30 compatible = "regulator-fixed"; 31 regulator-name = "vbat"; 32 regulator-min-microvolt = <5000000>; 33 regulator-max-microvolt = <5000000>; 34 regulator-boot-on; 35 }; 36 37 lis3_reg: fixedregulator1 { 38 compatible = "regulator-fixed"; 39 regulator-name = "lis3_reg"; 40 regulator-boot-on; 41 }; 42 43 wlan_en_reg: fixedregulator2 { 44 compatible = "regulator-fixed"; 45 regulator-name = "wlan-en-regulator"; 46 regulator-min-microvolt = <1800000>; 47 regulator-max-microvolt = <1800000>; 48 49 /* WLAN_EN GPIO for this board - Bank1, pin16 */ 50 gpio = <&gpio1 16 0>; 51 52 /* WLAN card specific delay */ 53 startup-delay-us = <70000>; 54 enable-active-high; 55 }; 56 57 /* TPS79501 */ 58 v1_8d_reg: fixedregulator-v1_8d { 59 compatible = "regulator-fixed"; 60 regulator-name = "v1_8d"; 61 vin-supply = <&vbat>; 62 regulator-min-microvolt = <1800000>; 63 regulator-max-microvolt = <1800000>; 64 }; 65 66 /* TPS79501 */ 67 v3_3d_reg: fixedregulator-v3_3d { 68 compatible = "regulator-fixed"; 69 regulator-name = "v3_3d"; 70 vin-supply = <&vbat>; 71 regulator-min-microvolt = <3300000>; 72 regulator-max-microvolt = <3300000>; 73 }; 74 75 matrix_keypad: matrix_keypad0 { 76 compatible = "gpio-matrix-keypad"; 77 debounce-delay-ms = <5>; 78 col-scan-delay-us = <2>; 79 80 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ 81 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ 82 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ 83 84 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ 85 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ 86 87 linux,keymap = <0x0000008b /* MENU */ 88 0x0100009e /* BACK */ 89 0x02000069 /* LEFT */ 90 0x0001006a /* RIGHT */ 91 0x0101001c /* ENTER */ 92 0x0201006c>; /* DOWN */ 93 }; 94 95 gpio_keys: volume_keys0 { 96 compatible = "gpio-keys"; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 autorepeat; 100 101 switch9 { 102 label = "volume-up"; 103 linux,code = <115>; 104 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 105 wakeup-source; 106 }; 107 108 switch10 { 109 label = "volume-down"; 110 linux,code = <114>; 111 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 112 wakeup-source; 113 }; 114 }; 115 116 backlight { 117 compatible = "pwm-backlight"; 118 pwms = <&ecap0 0 50000 0>; 119 brightness-levels = <0 51 53 56 62 75 101 152 255>; 120 default-brightness-level = <8>; 121 }; 122 123 panel { 124 compatible = "ti,tilcdc,panel"; 125 status = "okay"; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&lcd_pins_s0>; 128 panel-info { 129 ac-bias = <255>; 130 ac-bias-intrpt = <0>; 131 dma-burst-sz = <16>; 132 bpp = <32>; 133 fdd = <0x80>; 134 sync-edge = <0>; 135 sync-ctrl = <1>; 136 raster-order = <0>; 137 fifo-th = <0>; 138 }; 139 140 display-timings { 141 800x480p62 { 142 clock-frequency = <30000000>; 143 hactive = <800>; 144 vactive = <480>; 145 hfront-porch = <39>; 146 hback-porch = <39>; 147 hsync-len = <47>; 148 vback-porch = <29>; 149 vfront-porch = <13>; 150 vsync-len = <2>; 151 hsync-active = <1>; 152 vsync-active = <1>; 153 }; 154 }; 155 }; 156 157 sound { 158 compatible = "simple-audio-card"; 159 simple-audio-card,name = "AM335x-EVM"; 160 simple-audio-card,widgets = 161 "Headphone", "Headphone Jack", 162 "Line", "Line In"; 163 simple-audio-card,routing = 164 "Headphone Jack", "HPLOUT", 165 "Headphone Jack", "HPROUT", 166 "LINE1L", "Line In", 167 "LINE1R", "Line In"; 168 simple-audio-card,format = "dsp_b"; 169 simple-audio-card,bitclock-master = <&sound_master>; 170 simple-audio-card,frame-master = <&sound_master>; 171 simple-audio-card,bitclock-inversion; 172 173 simple-audio-card,cpu { 174 sound-dai = <&mcasp1>; 175 }; 176 177 sound_master: simple-audio-card,codec { 178 sound-dai = <&tlv320aic3106>; 179 system-clock-frequency = <12000000>; 180 }; 181 }; 182}; 183 184&am33xx_pinmux { 185 pinctrl-names = "default"; 186 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; 187 188 matrix_keypad_s0: matrix_keypad_s0 { 189 pinctrl-single,pins = < 190 AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a5.gpio1_21 */ 191 AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a6.gpio1_22 */ 192 AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a9.gpio1_25 */ 193 AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a10.gpio1_26 */ 194 AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_a11.gpio1_27 */ 195 >; 196 }; 197 198 volume_keys_s0: volume_keys_s0 { 199 pinctrl-single,pins = < 200 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_sclk.gpio0_2 */ 201 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7) /* spi0_d0.gpio0_3 */ 202 >; 203 }; 204 205 i2c0_pins: pinmux_i2c0_pins { 206 pinctrl-single,pins = < 207 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_sda.i2c0_sda */ 208 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) /* i2c0_scl.i2c0_scl */ 209 >; 210 }; 211 212 i2c1_pins: pinmux_i2c1_pins { 213 pinctrl-single,pins = < 214 AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_d1.i2c1_sda */ 215 AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2) /* spi0_cs0.i2c1_scl */ 216 >; 217 }; 218 219 uart0_pins: pinmux_uart0_pins { 220 pinctrl-single,pins = < 221 AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 222 AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 223 >; 224 }; 225 226 uart1_pins: pinmux_uart1_pins { 227 pinctrl-single,pins = < 228 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0) 229 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 230 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0) 231 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0) 232 >; 233 }; 234 235 clkout2_pin: pinmux_clkout2_pin { 236 pinctrl-single,pins = < 237 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */ 238 >; 239 }; 240 241 nandflash_pins_s0: nandflash_pins_s0 { 242 pinctrl-single,pins = < 243 AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0) 244 AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0) 245 AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0) 246 AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0) 247 AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0) 248 AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0) 249 AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0) 250 AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0) 251 AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0) 252 AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_30 */ 253 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0) 254 AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0) 255 AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0) 256 AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0) 257 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0) 258 >; 259 }; 260 261 ecap0_pins: backlight_pins { 262 pinctrl-single,pins = < 263 AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0) 264 >; 265 }; 266 267 cpsw_default: cpsw_default { 268 pinctrl-single,pins = < 269 /* Slave 1 */ 270 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 271 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 272 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 273 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 274 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 275 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 276 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 277 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 278 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 279 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 280 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 281 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 282 >; 283 }; 284 285 cpsw_sleep: cpsw_sleep { 286 pinctrl-single,pins = < 287 /* Slave 1 reset value */ 288 AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) 289 AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7) 290 AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 291 AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 292 AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 293 AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 294 AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 295 AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 296 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7) 297 AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7) 298 AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7) 299 AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7) 300 >; 301 }; 302 303 davinci_mdio_default: davinci_mdio_default { 304 pinctrl-single,pins = < 305 /* MDIO */ 306 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0) 307 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0) 308 >; 309 }; 310 311 davinci_mdio_sleep: davinci_mdio_sleep { 312 pinctrl-single,pins = < 313 /* MDIO reset value */ 314 AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7) 315 AM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7) 316 >; 317 }; 318 319 mmc1_pins: pinmux_mmc1_pins { 320 pinctrl-single,pins = < 321 AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */ 322 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0) 323 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0) 324 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0) 325 AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0) 326 AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0) 327 AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0) 328 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT, MUX_MODE4) /* mcasp0_aclkr.mmc0_sdwp */ 329 >; 330 }; 331 332 mmc3_pins: pinmux_mmc3_pins { 333 pinctrl-single,pins = < 334 AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */ 335 AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */ 336 AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */ 337 AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */ 338 AM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */ 339 AM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3) /* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */ 340 >; 341 }; 342 343 wlan_pins: pinmux_wlan_pins { 344 pinctrl-single,pins = < 345 AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_a0.gpio1_16 */ 346 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7) /* mcasp0_ahclkr.gpio3_17 */ 347 AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_ahclkx.gpio3_21 */ 348 >; 349 }; 350 351 lcd_pins_s0: lcd_pins_s0 { 352 pinctrl-single,pins = < 353 AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad8.lcd_data23 */ 354 AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad9.lcd_data22 */ 355 AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad10.lcd_data21 */ 356 AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad11.lcd_data20 */ 357 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad12.lcd_data19 */ 358 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad13.lcd_data18 */ 359 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad14.lcd_data17 */ 360 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1) /* gpmc_ad15.lcd_data16 */ 361 AM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0) 362 AM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0) 363 AM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0) 364 AM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0) 365 AM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0) 366 AM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0) 367 AM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0) 368 AM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0) 369 AM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0) 370 AM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0) 371 AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0) 372 AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0) 373 AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0) 374 AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0) 375 AM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0) 376 AM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0) 377 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0) 378 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0) 379 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0) 380 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0) 381 >; 382 }; 383 384 mcasp1_pins: mcasp1_pins { 385 pinctrl-single,pins = < 386 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 387 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ 388 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 389 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 390 >; 391 }; 392 393 mcasp1_pins_sleep: mcasp1_pins_sleep { 394 pinctrl-single,pins = < 395 AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7) 396 AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7) 397 AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7) 398 AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) 399 >; 400 }; 401 402 dcan1_pins_default: dcan1_pins_default { 403 pinctrl-single,pins = < 404 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */ 405 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */ 406 >; 407 }; 408}; 409 410&uart0 { 411 pinctrl-names = "default"; 412 pinctrl-0 = <&uart0_pins>; 413 414 status = "okay"; 415}; 416 417&uart1 { 418 pinctrl-names = "default"; 419 pinctrl-0 = <&uart1_pins>; 420 421 status = "okay"; 422}; 423 424&i2c0 { 425 pinctrl-names = "default"; 426 pinctrl-0 = <&i2c0_pins>; 427 428 status = "okay"; 429 clock-frequency = <400000>; 430 431 tps: tps@2d { 432 reg = <0x2d>; 433 }; 434}; 435 436&usb { 437 status = "okay"; 438}; 439 440&usb_ctrl_mod { 441 status = "okay"; 442}; 443 444&usb0_phy { 445 status = "okay"; 446}; 447 448&usb1_phy { 449 status = "okay"; 450}; 451 452&usb0 { 453 status = "okay"; 454}; 455 456&usb1 { 457 status = "okay"; 458 dr_mode = "host"; 459}; 460 461&cppi41dma { 462 status = "okay"; 463}; 464 465&i2c1 { 466 pinctrl-names = "default"; 467 pinctrl-0 = <&i2c1_pins>; 468 469 status = "okay"; 470 clock-frequency = <100000>; 471 472 lis331dlh: lis331dlh@18 { 473 compatible = "st,lis331dlh", "st,lis3lv02d"; 474 reg = <0x18>; 475 Vdd-supply = <&lis3_reg>; 476 Vdd_IO-supply = <&lis3_reg>; 477 478 st,click-single-x; 479 st,click-single-y; 480 st,click-single-z; 481 st,click-thresh-x = <10>; 482 st,click-thresh-y = <10>; 483 st,click-thresh-z = <10>; 484 st,irq1-click; 485 st,irq2-click; 486 st,wakeup-x-lo; 487 st,wakeup-x-hi; 488 st,wakeup-y-lo; 489 st,wakeup-y-hi; 490 st,wakeup-z-lo; 491 st,wakeup-z-hi; 492 st,min-limit-x = <120>; 493 st,min-limit-y = <120>; 494 st,min-limit-z = <140>; 495 st,max-limit-x = <550>; 496 st,max-limit-y = <550>; 497 st,max-limit-z = <750>; 498 }; 499 500 tsl2550: tsl2550@39 { 501 compatible = "taos,tsl2550"; 502 reg = <0x39>; 503 }; 504 505 tmp275: tmp275@48 { 506 compatible = "ti,tmp275"; 507 reg = <0x48>; 508 }; 509 510 tlv320aic3106: tlv320aic3106@1b { 511 #sound-dai-cells = <0>; 512 compatible = "ti,tlv320aic3106"; 513 reg = <0x1b>; 514 status = "okay"; 515 516 /* Regulators */ 517 AVDD-supply = <&v3_3d_reg>; 518 IOVDD-supply = <&v3_3d_reg>; 519 DRVDD-supply = <&v3_3d_reg>; 520 DVDD-supply = <&v1_8d_reg>; 521 }; 522}; 523 524&lcdc { 525 status = "okay"; 526 527 blue-and-red-wiring = "crossed"; 528}; 529 530&elm { 531 status = "okay"; 532}; 533 534&epwmss0 { 535 status = "okay"; 536 537 ecap0: ecap@100 { 538 status = "okay"; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&ecap0_pins>; 541 }; 542}; 543 544&gpmc { 545 status = "okay"; 546 pinctrl-names = "default"; 547 pinctrl-0 = <&nandflash_pins_s0>; 548 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 549 nand@0,0 { 550 compatible = "ti,omap2-nand"; 551 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 552 interrupt-parent = <&gpmc>; 553 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ 554 <1 IRQ_TYPE_NONE>; /* termcount */ 555 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ 556 ti,nand-xfer-type = "prefetch-dma"; 557 ti,nand-ecc-opt = "bch8"; 558 ti,elm-id = <&elm>; 559 nand-bus-width = <8>; 560 gpmc,device-width = <1>; 561 gpmc,sync-clk-ps = <0>; 562 gpmc,cs-on-ns = <0>; 563 gpmc,cs-rd-off-ns = <44>; 564 gpmc,cs-wr-off-ns = <44>; 565 gpmc,adv-on-ns = <6>; 566 gpmc,adv-rd-off-ns = <34>; 567 gpmc,adv-wr-off-ns = <44>; 568 gpmc,we-on-ns = <0>; 569 gpmc,we-off-ns = <40>; 570 gpmc,oe-on-ns = <0>; 571 gpmc,oe-off-ns = <54>; 572 gpmc,access-ns = <64>; 573 gpmc,rd-cycle-ns = <82>; 574 gpmc,wr-cycle-ns = <82>; 575 gpmc,bus-turnaround-ns = <0>; 576 gpmc,cycle2cycle-delay-ns = <0>; 577 gpmc,clk-activation-ns = <0>; 578 gpmc,wr-access-ns = <40>; 579 gpmc,wr-data-mux-bus-ns = <0>; 580 /* MTD partition table */ 581 /* All SPL-* partitions are sized to minimal length 582 * which can be independently programmable. For 583 * NAND flash this is equal to size of erase-block */ 584 #address-cells = <1>; 585 #size-cells = <1>; 586 partition@0 { 587 label = "NAND.SPL"; 588 reg = <0x00000000 0x000020000>; 589 }; 590 partition@1 { 591 label = "NAND.SPL.backup1"; 592 reg = <0x00020000 0x00020000>; 593 }; 594 partition@2 { 595 label = "NAND.SPL.backup2"; 596 reg = <0x00040000 0x00020000>; 597 }; 598 partition@3 { 599 label = "NAND.SPL.backup3"; 600 reg = <0x00060000 0x00020000>; 601 }; 602 partition@4 { 603 label = "NAND.u-boot-spl-os"; 604 reg = <0x00080000 0x00040000>; 605 }; 606 partition@5 { 607 label = "NAND.u-boot"; 608 reg = <0x000C0000 0x00100000>; 609 }; 610 partition@6 { 611 label = "NAND.u-boot-env"; 612 reg = <0x001C0000 0x00020000>; 613 }; 614 partition@7 { 615 label = "NAND.u-boot-env.backup1"; 616 reg = <0x001E0000 0x00020000>; 617 }; 618 partition@8 { 619 label = "NAND.kernel"; 620 reg = <0x00200000 0x00800000>; 621 }; 622 partition@9 { 623 label = "NAND.file-system"; 624 reg = <0x00A00000 0x0F600000>; 625 }; 626 }; 627}; 628 629#include "tps65910.dtsi" 630 631&mcasp1 { 632 #sound-dai-cells = <0>; 633 pinctrl-names = "default", "sleep"; 634 pinctrl-0 = <&mcasp1_pins>; 635 pinctrl-1 = <&mcasp1_pins_sleep>; 636 637 status = "okay"; 638 639 op-mode = <0>; /* MCASP_IIS_MODE */ 640 tdm-slots = <2>; 641 /* 4 serializers */ 642 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 643 0 0 1 2 644 >; 645 tx-num-evt = <32>; 646 rx-num-evt = <32>; 647}; 648 649&tps { 650 vcc1-supply = <&vbat>; 651 vcc2-supply = <&vbat>; 652 vcc3-supply = <&vbat>; 653 vcc4-supply = <&vbat>; 654 vcc5-supply = <&vbat>; 655 vcc6-supply = <&vbat>; 656 vcc7-supply = <&vbat>; 657 vccio-supply = <&vbat>; 658 659 regulators { 660 vrtc_reg: regulator@0 { 661 regulator-always-on; 662 }; 663 664 vio_reg: regulator@1 { 665 regulator-always-on; 666 }; 667 668 vdd1_reg: regulator@2 { 669 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 670 regulator-name = "vdd_mpu"; 671 regulator-min-microvolt = <912500>; 672 regulator-max-microvolt = <1351500>; 673 regulator-boot-on; 674 regulator-always-on; 675 }; 676 677 vdd2_reg: regulator@3 { 678 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 679 regulator-name = "vdd_core"; 680 regulator-min-microvolt = <912500>; 681 regulator-max-microvolt = <1150000>; 682 regulator-boot-on; 683 regulator-always-on; 684 }; 685 686 vdd3_reg: regulator@4 { 687 regulator-always-on; 688 }; 689 690 vdig1_reg: regulator@5 { 691 regulator-always-on; 692 }; 693 694 vdig2_reg: regulator@6 { 695 regulator-always-on; 696 }; 697 698 vpll_reg: regulator@7 { 699 regulator-always-on; 700 }; 701 702 vdac_reg: regulator@8 { 703 regulator-always-on; 704 }; 705 706 vaux1_reg: regulator@9 { 707 regulator-always-on; 708 }; 709 710 vaux2_reg: regulator@10 { 711 regulator-always-on; 712 }; 713 714 vaux33_reg: regulator@11 { 715 regulator-always-on; 716 }; 717 718 vmmc_reg: regulator@12 { 719 regulator-min-microvolt = <1800000>; 720 regulator-max-microvolt = <3300000>; 721 regulator-always-on; 722 }; 723 }; 724}; 725 726&mac { 727 pinctrl-names = "default", "sleep"; 728 pinctrl-0 = <&cpsw_default>; 729 pinctrl-1 = <&cpsw_sleep>; 730 status = "okay"; 731 slaves = <1>; 732}; 733 734&davinci_mdio { 735 pinctrl-names = "default", "sleep"; 736 pinctrl-0 = <&davinci_mdio_default>; 737 pinctrl-1 = <&davinci_mdio_sleep>; 738 status = "okay"; 739 740 ethphy0: ethernet-phy@0 { 741 reg = <0>; 742 }; 743}; 744 745&cpsw_emac0 { 746 phy-handle = <ðphy0>; 747 phy-mode = "rgmii-id"; 748}; 749 750&tscadc { 751 status = "okay"; 752 tsc { 753 ti,wires = <4>; 754 ti,x-plate-resistance = <200>; 755 ti,coordinate-readouts = <5>; 756 ti,wire-config = <0x00 0x11 0x22 0x33>; 757 ti,charge-delay = <0x400>; 758 }; 759 760 adc { 761 ti,adc-channels = <4 5 6 7>; 762 }; 763}; 764 765&mmc1 { 766 status = "okay"; 767 vmmc-supply = <&vmmc_reg>; 768 bus-width = <4>; 769 pinctrl-names = "default"; 770 pinctrl-0 = <&mmc1_pins>; 771 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 772}; 773 774&mmc3 { 775 /* these are on the crossbar and are outlined in the 776 xbar-event-map element */ 777 dmas = <&edma_xbar 12 0 1 778 &edma_xbar 13 0 2>; 779 dma-names = "tx", "rx"; 780 status = "okay"; 781 vmmc-supply = <&wlan_en_reg>; 782 bus-width = <4>; 783 pinctrl-names = "default"; 784 pinctrl-0 = <&mmc3_pins &wlan_pins>; 785 ti,non-removable; 786 ti,needs-special-hs-handling; 787 cap-power-off-card; 788 keep-power-in-suspend; 789 790 #address-cells = <1>; 791 #size-cells = <0>; 792 wlcore: wlcore@0 { 793 compatible = "ti,wl1835"; 794 reg = <2>; 795 interrupt-parent = <&gpio3>; 796 interrupts = <17 IRQ_TYPE_EDGE_RISING>; 797 }; 798}; 799 800&sham { 801 status = "okay"; 802}; 803 804&aes { 805 status = "okay"; 806}; 807 808&dcan1 { 809 status = "disabled"; /* Enable only if Profile 1 is selected */ 810 pinctrl-names = "default"; 811 pinctrl-0 = <&dcan1_pins_default>; 812}; 813 814&rtc { 815 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>; 816 clock-names = "ext-clk", "int-clk"; 817}; 818
