1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2019 NXP.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/init.h>
8 #include <linux/io.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/platform_device.h>
13 #include <linux/reboot.h>
14 #include <linux/watchdog.h>
15
16 #define WDOG_CS 0x0
17 #define WDOG_CS_CMD32EN BIT(13)
18 #define WDOG_CS_ULK BIT(11)
19 #define WDOG_CS_RCS BIT(10)
20 #define WDOG_CS_EN BIT(7)
21 #define WDOG_CS_UPDATE BIT(5)
22
23 #define WDOG_CNT 0x4
24 #define WDOG_TOVAL 0x8
25
26 #define REFRESH_SEQ0 0xA602
27 #define REFRESH_SEQ1 0xB480
28 #define REFRESH ((REFRESH_SEQ1 << 16) | REFRESH_SEQ0)
29
30 #define UNLOCK_SEQ0 0xC520
31 #define UNLOCK_SEQ1 0xD928
32 #define UNLOCK ((UNLOCK_SEQ1 << 16) | UNLOCK_SEQ0)
33
34 #define DEFAULT_TIMEOUT 60
35 #define MAX_TIMEOUT 128
36 #define WDOG_CLOCK_RATE 1000
37
38 static bool nowayout = WATCHDOG_NOWAYOUT;
39 module_param(nowayout, bool, 0000);
40 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
41 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
42
43 struct imx7ulp_wdt_device {
44 struct notifier_block restart_handler;
45 struct watchdog_device wdd;
46 void __iomem *base;
47 struct clk *clk;
48 };
49
imx7ulp_wdt_enable(void __iomem * base,bool enable)50 static inline void imx7ulp_wdt_enable(void __iomem *base, bool enable)
51 {
52 u32 val = readl(base + WDOG_CS);
53
54 writel(UNLOCK, base + WDOG_CNT);
55 if (enable)
56 writel(val | WDOG_CS_EN, base + WDOG_CS);
57 else
58 writel(val & ~WDOG_CS_EN, base + WDOG_CS);
59 }
60
imx7ulp_wdt_is_enabled(void __iomem * base)61 static inline bool imx7ulp_wdt_is_enabled(void __iomem *base)
62 {
63 u32 val = readl(base + WDOG_CS);
64
65 return val & WDOG_CS_EN;
66 }
67
imx7ulp_wdt_ping(struct watchdog_device * wdog)68 static int imx7ulp_wdt_ping(struct watchdog_device *wdog)
69 {
70 struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
71
72 writel(REFRESH, wdt->base + WDOG_CNT);
73
74 return 0;
75 }
76
imx7ulp_wdt_start(struct watchdog_device * wdog)77 static int imx7ulp_wdt_start(struct watchdog_device *wdog)
78 {
79 struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
80
81 imx7ulp_wdt_enable(wdt->base, true);
82
83 return 0;
84 }
85
imx7ulp_wdt_stop(struct watchdog_device * wdog)86 static int imx7ulp_wdt_stop(struct watchdog_device *wdog)
87 {
88 struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
89
90 imx7ulp_wdt_enable(wdt->base, false);
91
92 return 0;
93 }
94
imx7ulp_wdt_set_timeout(struct watchdog_device * wdog,unsigned int timeout)95 static int imx7ulp_wdt_set_timeout(struct watchdog_device *wdog,
96 unsigned int timeout)
97 {
98 struct imx7ulp_wdt_device *wdt = watchdog_get_drvdata(wdog);
99 u32 val = WDOG_CLOCK_RATE * timeout;
100
101 writel(UNLOCK, wdt->base + WDOG_CNT);
102 writel(val, wdt->base + WDOG_TOVAL);
103
104 wdog->timeout = timeout;
105
106 return 0;
107 }
108
109 static const struct watchdog_ops imx7ulp_wdt_ops = {
110 .owner = THIS_MODULE,
111 .start = imx7ulp_wdt_start,
112 .stop = imx7ulp_wdt_stop,
113 .ping = imx7ulp_wdt_ping,
114 .set_timeout = imx7ulp_wdt_set_timeout,
115 };
116
117 static const struct watchdog_info imx7ulp_wdt_info = {
118 .identity = "i.MX7ULP watchdog timer",
119 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING |
120 WDIOF_MAGICCLOSE,
121 };
122
imx7ulp_wdt_init(void __iomem * base,unsigned int timeout)123 static inline void imx7ulp_wdt_init(void __iomem *base, unsigned int timeout)
124 {
125 u32 val;
126
127 /* unlock the wdog for reconfiguration */
128 writel_relaxed(UNLOCK_SEQ0, base + WDOG_CNT);
129 writel_relaxed(UNLOCK_SEQ1, base + WDOG_CNT);
130
131 /* set an initial timeout value in TOVAL */
132 writel(timeout, base + WDOG_TOVAL);
133 /* enable 32bit command sequence and reconfigure */
134 val = BIT(13) | BIT(8) | BIT(5);
135 writel(val, base + WDOG_CS);
136 }
137
imx7ulp_wdt_action(void * data)138 static void imx7ulp_wdt_action(void *data)
139 {
140 clk_disable_unprepare(data);
141 }
142
imx7ulp_wdt_probe(struct platform_device * pdev)143 static int imx7ulp_wdt_probe(struct platform_device *pdev)
144 {
145 struct imx7ulp_wdt_device *imx7ulp_wdt;
146 struct device *dev = &pdev->dev;
147 struct watchdog_device *wdog;
148 int ret;
149
150 imx7ulp_wdt = devm_kzalloc(dev, sizeof(*imx7ulp_wdt), GFP_KERNEL);
151 if (!imx7ulp_wdt)
152 return -ENOMEM;
153
154 platform_set_drvdata(pdev, imx7ulp_wdt);
155
156 imx7ulp_wdt->base = devm_platform_ioremap_resource(pdev, 0);
157 if (IS_ERR(imx7ulp_wdt->base))
158 return PTR_ERR(imx7ulp_wdt->base);
159
160 imx7ulp_wdt->clk = devm_clk_get(dev, NULL);
161 if (IS_ERR(imx7ulp_wdt->clk)) {
162 dev_err(dev, "Failed to get watchdog clock\n");
163 return PTR_ERR(imx7ulp_wdt->clk);
164 }
165
166 ret = clk_prepare_enable(imx7ulp_wdt->clk);
167 if (ret)
168 return ret;
169
170 ret = devm_add_action_or_reset(dev, imx7ulp_wdt_action, imx7ulp_wdt->clk);
171 if (ret)
172 return ret;
173
174 wdog = &imx7ulp_wdt->wdd;
175 wdog->info = &imx7ulp_wdt_info;
176 wdog->ops = &imx7ulp_wdt_ops;
177 wdog->min_timeout = 1;
178 wdog->max_timeout = MAX_TIMEOUT;
179 wdog->parent = dev;
180 wdog->timeout = DEFAULT_TIMEOUT;
181
182 watchdog_init_timeout(wdog, 0, dev);
183 watchdog_stop_on_reboot(wdog);
184 watchdog_stop_on_unregister(wdog);
185 watchdog_set_drvdata(wdog, imx7ulp_wdt);
186 imx7ulp_wdt_init(imx7ulp_wdt->base, wdog->timeout * WDOG_CLOCK_RATE);
187
188 return devm_watchdog_register_device(dev, wdog);
189 }
190
imx7ulp_wdt_suspend(struct device * dev)191 static int __maybe_unused imx7ulp_wdt_suspend(struct device *dev)
192 {
193 struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
194
195 if (watchdog_active(&imx7ulp_wdt->wdd))
196 imx7ulp_wdt_stop(&imx7ulp_wdt->wdd);
197
198 clk_disable_unprepare(imx7ulp_wdt->clk);
199
200 return 0;
201 }
202
imx7ulp_wdt_resume(struct device * dev)203 static int __maybe_unused imx7ulp_wdt_resume(struct device *dev)
204 {
205 struct imx7ulp_wdt_device *imx7ulp_wdt = dev_get_drvdata(dev);
206 u32 timeout = imx7ulp_wdt->wdd.timeout * WDOG_CLOCK_RATE;
207 int ret;
208
209 ret = clk_prepare_enable(imx7ulp_wdt->clk);
210 if (ret)
211 return ret;
212
213 if (imx7ulp_wdt_is_enabled(imx7ulp_wdt->base))
214 imx7ulp_wdt_init(imx7ulp_wdt->base, timeout);
215
216 if (watchdog_active(&imx7ulp_wdt->wdd))
217 imx7ulp_wdt_start(&imx7ulp_wdt->wdd);
218
219 return 0;
220 }
221
222 static SIMPLE_DEV_PM_OPS(imx7ulp_wdt_pm_ops, imx7ulp_wdt_suspend,
223 imx7ulp_wdt_resume);
224
225 static const struct of_device_id imx7ulp_wdt_dt_ids[] = {
226 { .compatible = "fsl,imx7ulp-wdt", },
227 { /* sentinel */ }
228 };
229 MODULE_DEVICE_TABLE(of, imx7ulp_wdt_dt_ids);
230
231 static struct platform_driver imx7ulp_wdt_driver = {
232 .probe = imx7ulp_wdt_probe,
233 .driver = {
234 .name = "imx7ulp-wdt",
235 .pm = &imx7ulp_wdt_pm_ops,
236 .of_match_table = imx7ulp_wdt_dt_ids,
237 },
238 };
239 module_platform_driver(imx7ulp_wdt_driver);
240
241 MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>");
242 MODULE_DESCRIPTION("Freescale i.MX7ULP watchdog driver");
243 MODULE_LICENSE("GPL v2");
244
