1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Watchdog driver for IMX2 and later processors
4 *
5 * Copyright (C) 2010 Wolfram Sang, Pengutronix e.K. <w.sang@pengutronix.de>
6 * Copyright (C) 2014 Freescale Semiconductor, Inc.
7 *
8 * some parts adapted by similar drivers from Darius Augulis and Vladimir
9 * Zapolskiy, additional improvements by Wim Van Sebroeck.
10 *
11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
12 *
13 * MX1: MX2+:
14 * ---- -----
15 * Registers: 32-bit 16-bit
16 * Stopable timer: Yes No
17 * Need to enable clk: No Yes
18 * Halt on suspend: Manual Can be automatic
19 */
20
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/of_address.h>
30 #include <linux/platform_device.h>
31 #include <linux/regmap.h>
32 #include <linux/watchdog.h>
33
34 #define DRIVER_NAME "imx2-wdt"
35
36 #define IMX2_WDT_WCR 0x00 /* Control Register */
37 #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38 #define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */
39 #define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */
40 #define IMX2_WDT_WCR_WRE BIT(3) /* -> WDOG Reset Enable */
41 #define IMX2_WDT_WCR_WDE BIT(2) /* -> Watchdog Enable */
42 #define IMX2_WDT_WCR_WDZST BIT(0) /* -> Watchdog timer Suspend */
43
44 #define IMX2_WDT_WSR 0x02 /* Service Register */
45 #define IMX2_WDT_SEQ1 0x5555 /* -> service sequence 1 */
46 #define IMX2_WDT_SEQ2 0xAAAA /* -> service sequence 2 */
47
48 #define IMX2_WDT_WRSR 0x04 /* Reset Status Register */
49 #define IMX2_WDT_WRSR_TOUT BIT(1) /* -> Reset due to Timeout */
50
51 #define IMX2_WDT_WICR 0x06 /* Interrupt Control Register */
52 #define IMX2_WDT_WICR_WIE BIT(15) /* -> Interrupt Enable */
53 #define IMX2_WDT_WICR_WTIS BIT(14) /* -> Interrupt Status */
54 #define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
55
56 #define IMX2_WDT_WMCR 0x08 /* Misc Register */
57
58 #define IMX2_WDT_MAX_TIME 128U
59 #define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
60
61 #define WDOG_SEC_TO_COUNT(s) ((s * 2 - 1) << 8)
62
63 struct imx2_wdt_device {
64 struct clk *clk;
65 struct regmap *regmap;
66 struct watchdog_device wdog;
67 bool ext_reset;
68 };
69
70 static bool nowayout = WATCHDOG_NOWAYOUT;
71 module_param(nowayout, bool, 0);
72 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
73 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
74
75
76 static unsigned timeout;
77 module_param(timeout, uint, 0);
78 MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default="
79 __MODULE_STRING(IMX2_WDT_DEFAULT_TIME) ")");
80
81 static const struct watchdog_info imx2_wdt_info = {
82 .identity = "imx2+ watchdog",
83 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE,
84 };
85
86 static const struct watchdog_info imx2_wdt_pretimeout_info = {
87 .identity = "imx2+ watchdog",
88 .options = WDIOF_KEEPALIVEPING | WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
89 WDIOF_PRETIMEOUT,
90 };
91
imx2_wdt_restart(struct watchdog_device * wdog,unsigned long action,void * data)92 static int imx2_wdt_restart(struct watchdog_device *wdog, unsigned long action,
93 void *data)
94 {
95 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
96 unsigned int wcr_enable = IMX2_WDT_WCR_WDE;
97
98 /* Use internal reset or external - not both */
99 if (wdev->ext_reset)
100 wcr_enable |= IMX2_WDT_WCR_SRS; /* do not assert int reset */
101 else
102 wcr_enable |= IMX2_WDT_WCR_WDA; /* do not assert ext-reset */
103
104 /* Assert SRS signal */
105 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
106 /*
107 * Due to imx6q errata ERR004346 (WDOG: WDOG SRS bit requires to be
108 * written twice), we add another two writes to ensure there must be at
109 * least two writes happen in the same one 32kHz clock period. We save
110 * the target check here, since the writes shouldn't be a huge burden
111 * for other platforms.
112 */
113 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
114 regmap_write(wdev->regmap, IMX2_WDT_WCR, wcr_enable);
115
116 /* wait for reset to assert... */
117 mdelay(500);
118
119 return 0;
120 }
121
imx2_wdt_setup(struct watchdog_device * wdog)122 static inline void imx2_wdt_setup(struct watchdog_device *wdog)
123 {
124 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
125 u32 val;
126
127 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
128
129 /* Suspend timer in low power mode, write once-only */
130 val |= IMX2_WDT_WCR_WDZST;
131 /* Strip the old watchdog Time-Out value */
132 val &= ~IMX2_WDT_WCR_WT;
133 /* Generate internal chip-level reset if WDOG times out */
134 if (!wdev->ext_reset)
135 val &= ~IMX2_WDT_WCR_WRE;
136 /* Or if external-reset assert WDOG_B reset only on time-out */
137 else
138 val |= IMX2_WDT_WCR_WRE;
139 /* Keep Watchdog Disabled */
140 val &= ~IMX2_WDT_WCR_WDE;
141 /* Set the watchdog's Time-Out value */
142 val |= WDOG_SEC_TO_COUNT(wdog->timeout);
143
144 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
145
146 /* enable the watchdog */
147 val |= IMX2_WDT_WCR_WDE;
148 regmap_write(wdev->regmap, IMX2_WDT_WCR, val);
149 }
150
imx2_wdt_is_running(struct imx2_wdt_device * wdev)151 static inline bool imx2_wdt_is_running(struct imx2_wdt_device *wdev)
152 {
153 u32 val;
154
155 regmap_read(wdev->regmap, IMX2_WDT_WCR, &val);
156
157 return val & IMX2_WDT_WCR_WDE;
158 }
159
imx2_wdt_ping(struct watchdog_device * wdog)160 static int imx2_wdt_ping(struct watchdog_device *wdog)
161 {
162 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
163
164 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ1);
165 regmap_write(wdev->regmap, IMX2_WDT_WSR, IMX2_WDT_SEQ2);
166 return 0;
167 }
168
__imx2_wdt_set_timeout(struct watchdog_device * wdog,unsigned int new_timeout)169 static void __imx2_wdt_set_timeout(struct watchdog_device *wdog,
170 unsigned int new_timeout)
171 {
172 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
173
174 regmap_update_bits(wdev->regmap, IMX2_WDT_WCR, IMX2_WDT_WCR_WT,
175 WDOG_SEC_TO_COUNT(new_timeout));
176 }
177
imx2_wdt_set_timeout(struct watchdog_device * wdog,unsigned int new_timeout)178 static int imx2_wdt_set_timeout(struct watchdog_device *wdog,
179 unsigned int new_timeout)
180 {
181 unsigned int actual;
182
183 actual = min(new_timeout, IMX2_WDT_MAX_TIME);
184 __imx2_wdt_set_timeout(wdog, actual);
185 wdog->timeout = new_timeout;
186 return 0;
187 }
188
imx2_wdt_set_pretimeout(struct watchdog_device * wdog,unsigned int new_pretimeout)189 static int imx2_wdt_set_pretimeout(struct watchdog_device *wdog,
190 unsigned int new_pretimeout)
191 {
192 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
193
194 if (new_pretimeout >= IMX2_WDT_MAX_TIME)
195 return -EINVAL;
196
197 wdog->pretimeout = new_pretimeout;
198
199 regmap_update_bits(wdev->regmap, IMX2_WDT_WICR,
200 IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT,
201 IMX2_WDT_WICR_WIE | (new_pretimeout << 1));
202 return 0;
203 }
204
imx2_wdt_isr(int irq,void * wdog_arg)205 static irqreturn_t imx2_wdt_isr(int irq, void *wdog_arg)
206 {
207 struct watchdog_device *wdog = wdog_arg;
208 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
209
210 regmap_write_bits(wdev->regmap, IMX2_WDT_WICR,
211 IMX2_WDT_WICR_WTIS, IMX2_WDT_WICR_WTIS);
212
213 watchdog_notify_pretimeout(wdog);
214
215 return IRQ_HANDLED;
216 }
217
imx2_wdt_start(struct watchdog_device * wdog)218 static int imx2_wdt_start(struct watchdog_device *wdog)
219 {
220 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
221
222 if (imx2_wdt_is_running(wdev))
223 imx2_wdt_set_timeout(wdog, wdog->timeout);
224 else
225 imx2_wdt_setup(wdog);
226
227 set_bit(WDOG_HW_RUNNING, &wdog->status);
228
229 return imx2_wdt_ping(wdog);
230 }
231
232 static const struct watchdog_ops imx2_wdt_ops = {
233 .owner = THIS_MODULE,
234 .start = imx2_wdt_start,
235 .ping = imx2_wdt_ping,
236 .set_timeout = imx2_wdt_set_timeout,
237 .set_pretimeout = imx2_wdt_set_pretimeout,
238 .restart = imx2_wdt_restart,
239 };
240
241 static const struct regmap_config imx2_wdt_regmap_config = {
242 .reg_bits = 16,
243 .reg_stride = 2,
244 .val_bits = 16,
245 .max_register = 0x8,
246 };
247
imx2_wdt_probe(struct platform_device * pdev)248 static int __init imx2_wdt_probe(struct platform_device *pdev)
249 {
250 struct imx2_wdt_device *wdev;
251 struct watchdog_device *wdog;
252 void __iomem *base;
253 int ret;
254 u32 val;
255
256 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
257 if (!wdev)
258 return -ENOMEM;
259
260 base = devm_platform_ioremap_resource(pdev, 0);
261 if (IS_ERR(base))
262 return PTR_ERR(base);
263
264 wdev->regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
265 &imx2_wdt_regmap_config);
266 if (IS_ERR(wdev->regmap)) {
267 dev_err(&pdev->dev, "regmap init failed\n");
268 return PTR_ERR(wdev->regmap);
269 }
270
271 wdev->clk = devm_clk_get(&pdev->dev, NULL);
272 if (IS_ERR(wdev->clk)) {
273 dev_err(&pdev->dev, "can't get Watchdog clock\n");
274 return PTR_ERR(wdev->clk);
275 }
276
277 wdog = &wdev->wdog;
278 wdog->info = &imx2_wdt_info;
279 wdog->ops = &imx2_wdt_ops;
280 wdog->min_timeout = 1;
281 wdog->timeout = IMX2_WDT_DEFAULT_TIME;
282 wdog->max_hw_heartbeat_ms = IMX2_WDT_MAX_TIME * 1000;
283 wdog->parent = &pdev->dev;
284
285 ret = platform_get_irq(pdev, 0);
286 if (ret > 0)
287 if (!devm_request_irq(&pdev->dev, ret, imx2_wdt_isr, 0,
288 dev_name(&pdev->dev), wdog))
289 wdog->info = &imx2_wdt_pretimeout_info;
290
291 ret = clk_prepare_enable(wdev->clk);
292 if (ret)
293 return ret;
294
295 regmap_read(wdev->regmap, IMX2_WDT_WRSR, &val);
296 wdog->bootstatus = val & IMX2_WDT_WRSR_TOUT ? WDIOF_CARDRESET : 0;
297
298 wdev->ext_reset = of_property_read_bool(pdev->dev.of_node,
299 "fsl,ext-reset-output");
300 platform_set_drvdata(pdev, wdog);
301 watchdog_set_drvdata(wdog, wdev);
302 watchdog_set_nowayout(wdog, nowayout);
303 watchdog_set_restart_priority(wdog, 128);
304 watchdog_init_timeout(wdog, timeout, &pdev->dev);
305
306 if (imx2_wdt_is_running(wdev)) {
307 imx2_wdt_set_timeout(wdog, wdog->timeout);
308 set_bit(WDOG_HW_RUNNING, &wdog->status);
309 }
310
311 /*
312 * Disable the watchdog power down counter at boot. Otherwise the power
313 * down counter will pull down the #WDOG interrupt line for one clock
314 * cycle.
315 */
316 regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
317
318 ret = watchdog_register_device(wdog);
319 if (ret)
320 goto disable_clk;
321
322 dev_info(&pdev->dev, "timeout %d sec (nowayout=%d)\n",
323 wdog->timeout, nowayout);
324
325 return 0;
326
327 disable_clk:
328 clk_disable_unprepare(wdev->clk);
329 return ret;
330 }
331
imx2_wdt_remove(struct platform_device * pdev)332 static int __exit imx2_wdt_remove(struct platform_device *pdev)
333 {
334 struct watchdog_device *wdog = platform_get_drvdata(pdev);
335 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
336
337 watchdog_unregister_device(wdog);
338
339 if (imx2_wdt_is_running(wdev)) {
340 imx2_wdt_ping(wdog);
341 dev_crit(&pdev->dev, "Device removed: Expect reboot!\n");
342 }
343 return 0;
344 }
345
imx2_wdt_shutdown(struct platform_device * pdev)346 static void imx2_wdt_shutdown(struct platform_device *pdev)
347 {
348 struct watchdog_device *wdog = platform_get_drvdata(pdev);
349 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
350
351 if (imx2_wdt_is_running(wdev)) {
352 /*
353 * We are running, configure max timeout before reboot
354 * will take place.
355 */
356 imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
357 imx2_wdt_ping(wdog);
358 dev_crit(&pdev->dev, "Device shutdown: Expect reboot!\n");
359 }
360 }
361
362 #ifdef CONFIG_PM_SLEEP
363 /* Disable watchdog if it is active or non-active but still running */
imx2_wdt_suspend(struct device * dev)364 static int imx2_wdt_suspend(struct device *dev)
365 {
366 struct watchdog_device *wdog = dev_get_drvdata(dev);
367 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
368
369 /* The watchdog IP block is running */
370 if (imx2_wdt_is_running(wdev)) {
371 /*
372 * Don't update wdog->timeout, we'll restore the current value
373 * during resume.
374 */
375 __imx2_wdt_set_timeout(wdog, IMX2_WDT_MAX_TIME);
376 imx2_wdt_ping(wdog);
377 }
378
379 clk_disable_unprepare(wdev->clk);
380
381 return 0;
382 }
383
384 /* Enable watchdog and configure it if necessary */
imx2_wdt_resume(struct device * dev)385 static int imx2_wdt_resume(struct device *dev)
386 {
387 struct watchdog_device *wdog = dev_get_drvdata(dev);
388 struct imx2_wdt_device *wdev = watchdog_get_drvdata(wdog);
389 int ret;
390
391 ret = clk_prepare_enable(wdev->clk);
392 if (ret)
393 return ret;
394
395 if (watchdog_active(wdog) && !imx2_wdt_is_running(wdev)) {
396 /*
397 * If the watchdog is still active and resumes
398 * from deep sleep state, need to restart the
399 * watchdog again.
400 */
401 imx2_wdt_setup(wdog);
402 }
403 if (imx2_wdt_is_running(wdev)) {
404 imx2_wdt_set_timeout(wdog, wdog->timeout);
405 imx2_wdt_ping(wdog);
406 }
407
408 return 0;
409 }
410 #endif
411
412 static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
413 imx2_wdt_resume);
414
415 static const struct of_device_id imx2_wdt_dt_ids[] = {
416 { .compatible = "fsl,imx21-wdt", },
417 { /* sentinel */ }
418 };
419 MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
420
421 static struct platform_driver imx2_wdt_driver = {
422 .remove = __exit_p(imx2_wdt_remove),
423 .shutdown = imx2_wdt_shutdown,
424 .driver = {
425 .name = DRIVER_NAME,
426 .pm = &imx2_wdt_pm_ops,
427 .of_match_table = imx2_wdt_dt_ids,
428 },
429 };
430
431 module_platform_driver_probe(imx2_wdt_driver, imx2_wdt_probe);
432
433 MODULE_AUTHOR("Wolfram Sang");
434 MODULE_DESCRIPTION("Watchdog driver for IMX2 and later");
435 MODULE_LICENSE("GPL v2");
436 MODULE_ALIAS("platform:" DRIVER_NAME);
437
