1 /*
2 * Xilinx TFT frame buffer driver
3 *
4 * Author: MontaVista Software, Inc.
5 * source@mvista.com
6 *
7 * 2002-2007 (c) MontaVista Software, Inc.
8 * 2007 (c) Secret Lab Technologies, Ltd.
9 * 2009 (c) Xilinx Inc.
10 *
11 * This file is licensed under the terms of the GNU General Public License
12 * version 2. This program is licensed "as is" without any warranty of any
13 * kind, whether express or implied.
14 */
15
16 /*
17 * This driver was based on au1100fb.c by MontaVista rewritten for 2.6
18 * by Embedded Alley Solutions <source@embeddedalley.com>, which in turn
19 * was based on skeletonfb.c, Skeleton for a frame buffer device by
20 * Geert Uytterhoeven.
21 */
22
23 #include <linux/device.h>
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/errno.h>
27 #include <linux/string.h>
28 #include <linux/mm.h>
29 #include <linux/fb.h>
30 #include <linux/init.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/of_device.h>
33 #include <linux/of_platform.h>
34 #include <linux/of_address.h>
35 #include <linux/io.h>
36 #include <linux/slab.h>
37
38 #ifdef CONFIG_PPC_DCR
39 #include <asm/dcr.h>
40 #endif
41
42 #define DRIVER_NAME "xilinxfb"
43
44 /*
45 * Xilinx calls it "TFT LCD Controller" though it can also be used for
46 * the VGA port on the Xilinx ML40x board. This is a hardware display
47 * controller for a 640x480 resolution TFT or VGA screen.
48 *
49 * The interface to the framebuffer is nice and simple. There are two
50 * control registers. The first tells the LCD interface where in memory
51 * the frame buffer is (only the 11 most significant bits are used, so
52 * don't start thinking about scrolling). The second allows the LCD to
53 * be turned on or off as well as rotated 180 degrees.
54 *
55 * In case of direct BUS access the second control register will be at
56 * an offset of 4 as compared to the DCR access where the offset is 1
57 * i.e. REG_CTRL. So this is taken care in the function
58 * xilinx_fb_out32 where it left shifts the offset 2 times in case of
59 * direct BUS access.
60 */
61 #define NUM_REGS 2
62 #define REG_FB_ADDR 0
63 #define REG_CTRL 1
64 #define REG_CTRL_ENABLE 0x0001
65 #define REG_CTRL_ROTATE 0x0002
66
67 /*
68 * The hardware only handles a single mode: 640x480 24 bit true
69 * color. Each pixel gets a word (32 bits) of memory. Within each word,
70 * the 8 most significant bits are ignored, the next 8 bits are the red
71 * level, the next 8 bits are the green level and the 8 least
72 * significant bits are the blue level. Each row of the LCD uses 1024
73 * words, but only the first 640 pixels are displayed with the other 384
74 * words being ignored. There are 480 rows.
75 */
76 #define BYTES_PER_PIXEL 4
77 #define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
78
79 #define RED_SHIFT 16
80 #define GREEN_SHIFT 8
81 #define BLUE_SHIFT 0
82
83 #define PALETTE_ENTRIES_NO 16 /* passed to fb_alloc_cmap() */
84
85 /* ML300/403 reference design framebuffer driver platform data struct */
86 struct xilinxfb_platform_data {
87 u32 rotate_screen; /* Flag to rotate display 180 degrees */
88 u32 screen_height_mm; /* Physical dimensions of screen in mm */
89 u32 screen_width_mm;
90 u32 xres, yres; /* resolution of screen in pixels */
91 u32 xvirt, yvirt; /* resolution of memory buffer */
92
93 /* Physical address of framebuffer memory; If non-zero, driver
94 * will use provided memory address instead of allocating one from
95 * the consistent pool.
96 */
97 u32 fb_phys;
98 };
99
100 /*
101 * Default xilinxfb configuration
102 */
103 static const struct xilinxfb_platform_data xilinx_fb_default_pdata = {
104 .xres = 640,
105 .yres = 480,
106 .xvirt = 1024,
107 .yvirt = 480,
108 };
109
110 /*
111 * Here are the default fb_fix_screeninfo and fb_var_screeninfo structures
112 */
113 static const struct fb_fix_screeninfo xilinx_fb_fix = {
114 .id = "Xilinx",
115 .type = FB_TYPE_PACKED_PIXELS,
116 .visual = FB_VISUAL_TRUECOLOR,
117 .accel = FB_ACCEL_NONE
118 };
119
120 static const struct fb_var_screeninfo xilinx_fb_var = {
121 .bits_per_pixel = BITS_PER_PIXEL,
122
123 .red = { RED_SHIFT, 8, 0 },
124 .green = { GREEN_SHIFT, 8, 0 },
125 .blue = { BLUE_SHIFT, 8, 0 },
126 .transp = { 0, 0, 0 },
127
128 .activate = FB_ACTIVATE_NOW
129 };
130
131 #define BUS_ACCESS_FLAG 0x1 /* 1 = BUS, 0 = DCR */
132 #define LITTLE_ENDIAN_ACCESS 0x2 /* LITTLE ENDIAN IO functions */
133
134 struct xilinxfb_drvdata {
135 struct fb_info info; /* FB driver info record */
136
137 phys_addr_t regs_phys; /* phys. address of the control
138 * registers
139 */
140 void __iomem *regs; /* virt. address of the control
141 * registers
142 */
143 #ifdef CONFIG_PPC_DCR
144 dcr_host_t dcr_host;
145 unsigned int dcr_len;
146 #endif
147 void *fb_virt; /* virt. address of the frame buffer */
148 dma_addr_t fb_phys; /* phys. address of the frame buffer */
149 int fb_alloced; /* Flag, was the fb memory alloced? */
150
151 u8 flags; /* features of the driver */
152
153 u32 reg_ctrl_default;
154
155 u32 pseudo_palette[PALETTE_ENTRIES_NO];
156 /* Fake palette of 16 colors */
157 };
158
159 #define to_xilinxfb_drvdata(_info) \
160 container_of(_info, struct xilinxfb_drvdata, info)
161
162 /*
163 * The XPS TFT Controller can be accessed through BUS or DCR interface.
164 * To perform the read/write on the registers we need to check on
165 * which bus its connected and call the appropriate write API.
166 */
xilinx_fb_out32(struct xilinxfb_drvdata * drvdata,u32 offset,u32 val)167 static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
168 u32 val)
169 {
170 if (drvdata->flags & BUS_ACCESS_FLAG) {
171 if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
172 iowrite32(val, drvdata->regs + (offset << 2));
173 else
174 iowrite32be(val, drvdata->regs + (offset << 2));
175 }
176 #ifdef CONFIG_PPC_DCR
177 else
178 dcr_write(drvdata->dcr_host, offset, val);
179 #endif
180 }
181
xilinx_fb_in32(struct xilinxfb_drvdata * drvdata,u32 offset)182 static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset)
183 {
184 if (drvdata->flags & BUS_ACCESS_FLAG) {
185 if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
186 return ioread32(drvdata->regs + (offset << 2));
187 else
188 return ioread32be(drvdata->regs + (offset << 2));
189 }
190 #ifdef CONFIG_PPC_DCR
191 else
192 return dcr_read(drvdata->dcr_host, offset);
193 #endif
194 return 0;
195 }
196
197 static int
xilinx_fb_setcolreg(unsigned int regno,unsigned int red,unsigned int green,unsigned int blue,unsigned int transp,struct fb_info * fbi)198 xilinx_fb_setcolreg(unsigned int regno, unsigned int red, unsigned int green,
199 unsigned int blue, unsigned int transp, struct fb_info *fbi)
200 {
201 u32 *palette = fbi->pseudo_palette;
202
203 if (regno >= PALETTE_ENTRIES_NO)
204 return -EINVAL;
205
206 if (fbi->var.grayscale) {
207 /* Convert color to grayscale.
208 * grayscale = 0.30*R + 0.59*G + 0.11*B
209 */
210 blue = (red * 77 + green * 151 + blue * 28 + 127) >> 8;
211 green = blue;
212 red = green;
213 }
214
215 /* fbi->fix.visual is always FB_VISUAL_TRUECOLOR */
216
217 /* We only handle 8 bits of each color. */
218 red >>= 8;
219 green >>= 8;
220 blue >>= 8;
221 palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
222 (blue << BLUE_SHIFT);
223
224 return 0;
225 }
226
227 static int
xilinx_fb_blank(int blank_mode,struct fb_info * fbi)228 xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
229 {
230 struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
231
232 switch (blank_mode) {
233 case FB_BLANK_UNBLANK:
234 /* turn on panel */
235 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
236 break;
237
238 case FB_BLANK_NORMAL:
239 case FB_BLANK_VSYNC_SUSPEND:
240 case FB_BLANK_HSYNC_SUSPEND:
241 case FB_BLANK_POWERDOWN:
242 /* turn off panel */
243 xilinx_fb_out32(drvdata, REG_CTRL, 0);
244 default:
245 break;
246 }
247 return 0; /* success */
248 }
249
250 static struct fb_ops xilinxfb_ops = {
251 .owner = THIS_MODULE,
252 .fb_setcolreg = xilinx_fb_setcolreg,
253 .fb_blank = xilinx_fb_blank,
254 .fb_fillrect = cfb_fillrect,
255 .fb_copyarea = cfb_copyarea,
256 .fb_imageblit = cfb_imageblit,
257 };
258
259 /* ---------------------------------------------------------------------
260 * Bus independent setup/teardown
261 */
262
xilinxfb_assign(struct platform_device * pdev,struct xilinxfb_drvdata * drvdata,struct xilinxfb_platform_data * pdata)263 static int xilinxfb_assign(struct platform_device *pdev,
264 struct xilinxfb_drvdata *drvdata,
265 struct xilinxfb_platform_data *pdata)
266 {
267 int rc;
268 struct device *dev = &pdev->dev;
269 int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
270
271 if (drvdata->flags & BUS_ACCESS_FLAG) {
272 struct resource *res;
273
274 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
275 drvdata->regs = devm_ioremap_resource(&pdev->dev, res);
276 if (IS_ERR(drvdata->regs))
277 return PTR_ERR(drvdata->regs);
278
279 drvdata->regs_phys = res->start;
280 }
281
282 /* Allocate the framebuffer memory */
283 if (pdata->fb_phys) {
284 drvdata->fb_phys = pdata->fb_phys;
285 drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
286 } else {
287 drvdata->fb_alloced = 1;
288 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
289 &drvdata->fb_phys,
290 GFP_KERNEL);
291 }
292
293 if (!drvdata->fb_virt) {
294 dev_err(dev, "Could not allocate frame buffer memory\n");
295 return -ENOMEM;
296 }
297
298 /* Clear (turn to black) the framebuffer */
299 memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
300
301 /* Tell the hardware where the frame buffer is */
302 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
303 rc = xilinx_fb_in32(drvdata, REG_FB_ADDR);
304 /* Endianness detection */
305 if (rc != drvdata->fb_phys) {
306 drvdata->flags |= LITTLE_ENDIAN_ACCESS;
307 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
308 }
309
310 /* Turn on the display */
311 drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
312 if (pdata->rotate_screen)
313 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
314 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
315
316 /* Fill struct fb_info */
317 drvdata->info.device = dev;
318 drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
319 drvdata->info.fbops = &xilinxfb_ops;
320 drvdata->info.fix = xilinx_fb_fix;
321 drvdata->info.fix.smem_start = drvdata->fb_phys;
322 drvdata->info.fix.smem_len = fbsize;
323 drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
324
325 drvdata->info.pseudo_palette = drvdata->pseudo_palette;
326 drvdata->info.flags = FBINFO_DEFAULT;
327 drvdata->info.var = xilinx_fb_var;
328 drvdata->info.var.height = pdata->screen_height_mm;
329 drvdata->info.var.width = pdata->screen_width_mm;
330 drvdata->info.var.xres = pdata->xres;
331 drvdata->info.var.yres = pdata->yres;
332 drvdata->info.var.xres_virtual = pdata->xvirt;
333 drvdata->info.var.yres_virtual = pdata->yvirt;
334
335 /* Allocate a colour map */
336 rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
337 if (rc) {
338 dev_err(dev, "Fail to allocate colormap (%d entries)\n",
339 PALETTE_ENTRIES_NO);
340 goto err_cmap;
341 }
342
343 /* Register new frame buffer */
344 rc = register_framebuffer(&drvdata->info);
345 if (rc) {
346 dev_err(dev, "Could not register frame buffer\n");
347 goto err_regfb;
348 }
349
350 if (drvdata->flags & BUS_ACCESS_FLAG) {
351 /* Put a banner in the log (for DEBUG) */
352 dev_dbg(dev, "regs: phys=%pa, virt=%p\n",
353 &drvdata->regs_phys, drvdata->regs);
354 }
355 /* Put a banner in the log (for DEBUG) */
356 dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
357 (unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize);
358
359 return 0; /* success */
360
361 err_regfb:
362 fb_dealloc_cmap(&drvdata->info.cmap);
363
364 err_cmap:
365 if (drvdata->fb_alloced)
366 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
367 drvdata->fb_phys);
368 else
369 iounmap(drvdata->fb_virt);
370
371 /* Turn off the display */
372 xilinx_fb_out32(drvdata, REG_CTRL, 0);
373
374 return rc;
375 }
376
xilinxfb_release(struct device * dev)377 static int xilinxfb_release(struct device *dev)
378 {
379 struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
380
381 #if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
382 xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
383 #endif
384
385 unregister_framebuffer(&drvdata->info);
386
387 fb_dealloc_cmap(&drvdata->info.cmap);
388
389 if (drvdata->fb_alloced)
390 dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
391 drvdata->fb_virt, drvdata->fb_phys);
392 else
393 iounmap(drvdata->fb_virt);
394
395 /* Turn off the display */
396 xilinx_fb_out32(drvdata, REG_CTRL, 0);
397
398 #ifdef CONFIG_PPC_DCR
399 /* Release the resources, as allocated based on interface */
400 if (!(drvdata->flags & BUS_ACCESS_FLAG))
401 dcr_unmap(drvdata->dcr_host, drvdata->dcr_len);
402 #endif
403
404 return 0;
405 }
406
407 /* ---------------------------------------------------------------------
408 * OF bus binding
409 */
410
xilinxfb_of_probe(struct platform_device * pdev)411 static int xilinxfb_of_probe(struct platform_device *pdev)
412 {
413 const u32 *prop;
414 u32 tft_access = 0;
415 struct xilinxfb_platform_data pdata;
416 int size;
417 struct xilinxfb_drvdata *drvdata;
418
419 /* Copy with the default pdata (not a ptr reference!) */
420 pdata = xilinx_fb_default_pdata;
421
422 /* Allocate the driver data region */
423 drvdata = devm_kzalloc(&pdev->dev, sizeof(*drvdata), GFP_KERNEL);
424 if (!drvdata)
425 return -ENOMEM;
426
427 /*
428 * To check whether the core is connected directly to DCR or BUS
429 * interface and initialize the tft_access accordingly.
430 */
431 of_property_read_u32(pdev->dev.of_node, "xlnx,dcr-splb-slave-if",
432 &tft_access);
433
434 /*
435 * Fill the resource structure if its direct BUS interface
436 * otherwise fill the dcr_host structure.
437 */
438 if (tft_access)
439 drvdata->flags |= BUS_ACCESS_FLAG;
440 #ifdef CONFIG_PPC_DCR
441 else {
442 int start;
443
444 start = dcr_resource_start(pdev->dev.of_node, 0);
445 drvdata->dcr_len = dcr_resource_len(pdev->dev.of_node, 0);
446 drvdata->dcr_host = dcr_map(pdev->dev.of_node, start, drvdata->dcr_len);
447 if (!DCR_MAP_OK(drvdata->dcr_host)) {
448 dev_err(&pdev->dev, "invalid DCR address\n");
449 return -ENODEV;
450 }
451 }
452 #endif
453
454 prop = of_get_property(pdev->dev.of_node, "phys-size", &size);
455 if ((prop) && (size >= sizeof(u32) * 2)) {
456 pdata.screen_width_mm = prop[0];
457 pdata.screen_height_mm = prop[1];
458 }
459
460 prop = of_get_property(pdev->dev.of_node, "resolution", &size);
461 if ((prop) && (size >= sizeof(u32) * 2)) {
462 pdata.xres = prop[0];
463 pdata.yres = prop[1];
464 }
465
466 prop = of_get_property(pdev->dev.of_node, "virtual-resolution", &size);
467 if ((prop) && (size >= sizeof(u32) * 2)) {
468 pdata.xvirt = prop[0];
469 pdata.yvirt = prop[1];
470 }
471
472 if (of_find_property(pdev->dev.of_node, "rotate-display", NULL))
473 pdata.rotate_screen = 1;
474
475 dev_set_drvdata(&pdev->dev, drvdata);
476 return xilinxfb_assign(pdev, drvdata, &pdata);
477 }
478
xilinxfb_of_remove(struct platform_device * op)479 static int xilinxfb_of_remove(struct platform_device *op)
480 {
481 return xilinxfb_release(&op->dev);
482 }
483
484 /* Match table for of_platform binding */
485 static const struct of_device_id xilinxfb_of_match[] = {
486 { .compatible = "xlnx,xps-tft-1.00.a", },
487 { .compatible = "xlnx,xps-tft-2.00.a", },
488 { .compatible = "xlnx,xps-tft-2.01.a", },
489 { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
490 { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
491 {},
492 };
493 MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
494
495 static struct platform_driver xilinxfb_of_driver = {
496 .probe = xilinxfb_of_probe,
497 .remove = xilinxfb_of_remove,
498 .driver = {
499 .name = DRIVER_NAME,
500 .of_match_table = xilinxfb_of_match,
501 },
502 };
503
504 module_platform_driver(xilinxfb_of_driver);
505
506 MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
507 MODULE_DESCRIPTION("Xilinx TFT frame buffer driver");
508 MODULE_LICENSE("GPL");
509
