1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
21
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24
25 #include "8250.h"
26
27 /*
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
32 */
33 struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44 };
45
46 struct f815xxa_data {
47 spinlock_t lock;
48 int idx;
49 };
50
51 #define PCI_NUM_BAR_RESOURCES 6
52
53 struct serial_private {
54 struct pci_dev *dev;
55 unsigned int nr;
56 struct pci_serial_quirk *quirk;
57 const struct pciserial_board *board;
58 int line[0];
59 };
60
61 static const struct pci_device_id pci_use_msi[] = {
62 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
63 0xA000, 0x1000) },
64 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
65 0xA000, 0x1000) },
66 { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
67 0xA000, 0x1000) },
68 { }
69 };
70
71 static int pci_default_setup(struct serial_private*,
72 const struct pciserial_board*, struct uart_8250_port *, int);
73
moan_device(const char * str,struct pci_dev * dev)74 static void moan_device(const char *str, struct pci_dev *dev)
75 {
76 dev_err(&dev->dev,
77 "%s: %s\n"
78 "Please send the output of lspci -vv, this\n"
79 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
80 "manufacturer and name of serial board or\n"
81 "modem board to <linux-serial@vger.kernel.org>.\n",
82 pci_name(dev), str, dev->vendor, dev->device,
83 dev->subsystem_vendor, dev->subsystem_device);
84 }
85
86 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,int bar,int offset,int regshift)87 setup_port(struct serial_private *priv, struct uart_8250_port *port,
88 int bar, int offset, int regshift)
89 {
90 struct pci_dev *dev = priv->dev;
91
92 if (bar >= PCI_NUM_BAR_RESOURCES)
93 return -EINVAL;
94
95 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
96 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
97 return -ENOMEM;
98
99 port->port.iotype = UPIO_MEM;
100 port->port.iobase = 0;
101 port->port.mapbase = pci_resource_start(dev, bar) + offset;
102 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
103 port->port.regshift = regshift;
104 } else {
105 port->port.iotype = UPIO_PORT;
106 port->port.iobase = pci_resource_start(dev, bar) + offset;
107 port->port.mapbase = 0;
108 port->port.membase = NULL;
109 port->port.regshift = 0;
110 }
111 return 0;
112 }
113
114 /*
115 * ADDI-DATA GmbH communication cards <info@addi-data.com>
116 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)117 static int addidata_apci7800_setup(struct serial_private *priv,
118 const struct pciserial_board *board,
119 struct uart_8250_port *port, int idx)
120 {
121 unsigned int bar = 0, offset = board->first_offset;
122 bar = FL_GET_BASE(board->flags);
123
124 if (idx < 2) {
125 offset += idx * board->uart_offset;
126 } else if ((idx >= 2) && (idx < 4)) {
127 bar += 1;
128 offset += ((idx - 2) * board->uart_offset);
129 } else if ((idx >= 4) && (idx < 6)) {
130 bar += 2;
131 offset += ((idx - 4) * board->uart_offset);
132 } else if (idx >= 6) {
133 bar += 3;
134 offset += ((idx - 6) * board->uart_offset);
135 }
136
137 return setup_port(priv, port, bar, offset, board->reg_shift);
138 }
139
140 /*
141 * AFAVLAB uses a different mixture of BARs and offsets
142 * Not that ugly ;) -- HW
143 */
144 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)145 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
146 struct uart_8250_port *port, int idx)
147 {
148 unsigned int bar, offset = board->first_offset;
149
150 bar = FL_GET_BASE(board->flags);
151 if (idx < 4)
152 bar += idx;
153 else {
154 bar = 4;
155 offset += (idx - 4) * board->uart_offset;
156 }
157
158 return setup_port(priv, port, bar, offset, board->reg_shift);
159 }
160
161 /*
162 * HP's Remote Management Console. The Diva chip came in several
163 * different versions. N-class, L2000 and A500 have two Diva chips, each
164 * with 3 UARTs (the third UART on the second chip is unused). Superdome
165 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
166 * one Diva chip, but it has been expanded to 5 UARTs.
167 */
pci_hp_diva_init(struct pci_dev * dev)168 static int pci_hp_diva_init(struct pci_dev *dev)
169 {
170 int rc = 0;
171
172 switch (dev->subsystem_device) {
173 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
174 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
175 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
176 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
177 rc = 3;
178 break;
179 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
180 rc = 2;
181 break;
182 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
183 rc = 4;
184 break;
185 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
186 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
187 rc = 1;
188 break;
189 }
190
191 return rc;
192 }
193
194 /*
195 * HP's Diva chip puts the 4th/5th serial port further out, and
196 * some serial ports are supposed to be hidden on certain models.
197 */
198 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)199 pci_hp_diva_setup(struct serial_private *priv,
200 const struct pciserial_board *board,
201 struct uart_8250_port *port, int idx)
202 {
203 unsigned int offset = board->first_offset;
204 unsigned int bar = FL_GET_BASE(board->flags);
205
206 switch (priv->dev->subsystem_device) {
207 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
208 if (idx == 3)
209 idx++;
210 break;
211 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
212 if (idx > 0)
213 idx++;
214 if (idx > 2)
215 idx++;
216 break;
217 }
218 if (idx > 2)
219 offset = 0x18;
220
221 offset += idx * board->uart_offset;
222
223 return setup_port(priv, port, bar, offset, board->reg_shift);
224 }
225
226 /*
227 * Added for EKF Intel i960 serial boards
228 */
pci_inteli960ni_init(struct pci_dev * dev)229 static int pci_inteli960ni_init(struct pci_dev *dev)
230 {
231 u32 oldval;
232
233 if (!(dev->subsystem_device & 0x1000))
234 return -ENODEV;
235
236 /* is firmware started? */
237 pci_read_config_dword(dev, 0x44, &oldval);
238 if (oldval == 0x00001000L) { /* RESET value */
239 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
240 return -ENODEV;
241 }
242 return 0;
243 }
244
245 /*
246 * Some PCI serial cards using the PLX 9050 PCI interface chip require
247 * that the card interrupt be explicitly enabled or disabled. This
248 * seems to be mainly needed on card using the PLX which also use I/O
249 * mapped memory.
250 */
pci_plx9050_init(struct pci_dev * dev)251 static int pci_plx9050_init(struct pci_dev *dev)
252 {
253 u8 irq_config;
254 void __iomem *p;
255
256 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
257 moan_device("no memory in bar 0", dev);
258 return 0;
259 }
260
261 irq_config = 0x41;
262 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
263 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
264 irq_config = 0x43;
265
266 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
267 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
268 /*
269 * As the megawolf cards have the int pins active
270 * high, and have 2 UART chips, both ints must be
271 * enabled on the 9050. Also, the UARTS are set in
272 * 16450 mode by default, so we have to enable the
273 * 16C950 'enhanced' mode so that we can use the
274 * deep FIFOs
275 */
276 irq_config = 0x5b;
277 /*
278 * enable/disable interrupts
279 */
280 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
281 if (p == NULL)
282 return -ENOMEM;
283 writel(irq_config, p + 0x4c);
284
285 /*
286 * Read the register back to ensure that it took effect.
287 */
288 readl(p + 0x4c);
289 iounmap(p);
290
291 return 0;
292 }
293
pci_plx9050_exit(struct pci_dev * dev)294 static void pci_plx9050_exit(struct pci_dev *dev)
295 {
296 u8 __iomem *p;
297
298 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
299 return;
300
301 /*
302 * disable interrupts
303 */
304 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
305 if (p != NULL) {
306 writel(0, p + 0x4c);
307
308 /*
309 * Read the register back to ensure that it took effect.
310 */
311 readl(p + 0x4c);
312 iounmap(p);
313 }
314 }
315
316 #define NI8420_INT_ENABLE_REG 0x38
317 #define NI8420_INT_ENABLE_BIT 0x2000
318
pci_ni8420_exit(struct pci_dev * dev)319 static void pci_ni8420_exit(struct pci_dev *dev)
320 {
321 void __iomem *p;
322 unsigned int bar = 0;
323
324 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
325 moan_device("no memory in bar", dev);
326 return;
327 }
328
329 p = pci_ioremap_bar(dev, bar);
330 if (p == NULL)
331 return;
332
333 /* Disable the CPU Interrupt */
334 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
335 p + NI8420_INT_ENABLE_REG);
336 iounmap(p);
337 }
338
339
340 /* MITE registers */
341 #define MITE_IOWBSR1 0xc4
342 #define MITE_IOWCR1 0xf4
343 #define MITE_LCIMR1 0x08
344 #define MITE_LCIMR2 0x10
345
346 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
347
pci_ni8430_exit(struct pci_dev * dev)348 static void pci_ni8430_exit(struct pci_dev *dev)
349 {
350 void __iomem *p;
351 unsigned int bar = 0;
352
353 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
354 moan_device("no memory in bar", dev);
355 return;
356 }
357
358 p = pci_ioremap_bar(dev, bar);
359 if (p == NULL)
360 return;
361
362 /* Disable the CPU Interrupt */
363 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
364 iounmap(p);
365 }
366
367 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
368 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)369 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
370 struct uart_8250_port *port, int idx)
371 {
372 unsigned int bar, offset = board->first_offset;
373
374 bar = 0;
375
376 if (idx < 4) {
377 /* first four channels map to 0, 0x100, 0x200, 0x300 */
378 offset += idx * board->uart_offset;
379 } else if (idx < 8) {
380 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
381 offset += idx * board->uart_offset + 0xC00;
382 } else /* we have only 8 ports on PMC-OCTALPRO */
383 return 1;
384
385 return setup_port(priv, port, bar, offset, board->reg_shift);
386 }
387
388 /*
389 * This does initialization for PMC OCTALPRO cards:
390 * maps the device memory, resets the UARTs (needed, bc
391 * if the module is removed and inserted again, the card
392 * is in the sleep mode) and enables global interrupt.
393 */
394
395 /* global control register offset for SBS PMC-OctalPro */
396 #define OCT_REG_CR_OFF 0x500
397
sbs_init(struct pci_dev * dev)398 static int sbs_init(struct pci_dev *dev)
399 {
400 u8 __iomem *p;
401
402 p = pci_ioremap_bar(dev, 0);
403
404 if (p == NULL)
405 return -ENOMEM;
406 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
407 writeb(0x10, p + OCT_REG_CR_OFF);
408 udelay(50);
409 writeb(0x0, p + OCT_REG_CR_OFF);
410
411 /* Set bit-2 (INTENABLE) of Control Register */
412 writeb(0x4, p + OCT_REG_CR_OFF);
413 iounmap(p);
414
415 return 0;
416 }
417
418 /*
419 * Disables the global interrupt of PMC-OctalPro
420 */
421
sbs_exit(struct pci_dev * dev)422 static void sbs_exit(struct pci_dev *dev)
423 {
424 u8 __iomem *p;
425
426 p = pci_ioremap_bar(dev, 0);
427 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
428 if (p != NULL)
429 writeb(0, p + OCT_REG_CR_OFF);
430 iounmap(p);
431 }
432
433 /*
434 * SIIG serial cards have an PCI interface chip which also controls
435 * the UART clocking frequency. Each UART can be clocked independently
436 * (except cards equipped with 4 UARTs) and initial clocking settings
437 * are stored in the EEPROM chip. It can cause problems because this
438 * version of serial driver doesn't support differently clocked UART's
439 * on single PCI card. To prevent this, initialization functions set
440 * high frequency clocking for all UART's on given card. It is safe (I
441 * hope) because it doesn't touch EEPROM settings to prevent conflicts
442 * with other OSes (like M$ DOS).
443 *
444 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
445 *
446 * There is two family of SIIG serial cards with different PCI
447 * interface chip and different configuration methods:
448 * - 10x cards have control registers in IO and/or memory space;
449 * - 20x cards have control registers in standard PCI configuration space.
450 *
451 * Note: all 10x cards have PCI device ids 0x10..
452 * all 20x cards have PCI device ids 0x20..
453 *
454 * There are also Quartet Serial cards which use Oxford Semiconductor
455 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
456 *
457 * Note: some SIIG cards are probed by the parport_serial object.
458 */
459
460 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
461 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
462
pci_siig10x_init(struct pci_dev * dev)463 static int pci_siig10x_init(struct pci_dev *dev)
464 {
465 u16 data;
466 void __iomem *p;
467
468 switch (dev->device & 0xfff8) {
469 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
470 data = 0xffdf;
471 break;
472 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
473 data = 0xf7ff;
474 break;
475 default: /* 1S1P, 4S */
476 data = 0xfffb;
477 break;
478 }
479
480 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
481 if (p == NULL)
482 return -ENOMEM;
483
484 writew(readw(p + 0x28) & data, p + 0x28);
485 readw(p + 0x28);
486 iounmap(p);
487 return 0;
488 }
489
490 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
491 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
492
pci_siig20x_init(struct pci_dev * dev)493 static int pci_siig20x_init(struct pci_dev *dev)
494 {
495 u8 data;
496
497 /* Change clock frequency for the first UART. */
498 pci_read_config_byte(dev, 0x6f, &data);
499 pci_write_config_byte(dev, 0x6f, data & 0xef);
500
501 /* If this card has 2 UART, we have to do the same with second UART. */
502 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
503 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
504 pci_read_config_byte(dev, 0x73, &data);
505 pci_write_config_byte(dev, 0x73, data & 0xef);
506 }
507 return 0;
508 }
509
pci_siig_init(struct pci_dev * dev)510 static int pci_siig_init(struct pci_dev *dev)
511 {
512 unsigned int type = dev->device & 0xff00;
513
514 if (type == 0x1000)
515 return pci_siig10x_init(dev);
516 else if (type == 0x2000)
517 return pci_siig20x_init(dev);
518
519 moan_device("Unknown SIIG card", dev);
520 return -ENODEV;
521 }
522
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)523 static int pci_siig_setup(struct serial_private *priv,
524 const struct pciserial_board *board,
525 struct uart_8250_port *port, int idx)
526 {
527 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
528
529 if (idx > 3) {
530 bar = 4;
531 offset = (idx - 4) * 8;
532 }
533
534 return setup_port(priv, port, bar, offset, 0);
535 }
536
537 /*
538 * Timedia has an explosion of boards, and to avoid the PCI table from
539 * growing *huge*, we use this function to collapse some 70 entries
540 * in the PCI table into one, for sanity's and compactness's sake.
541 */
542 static const unsigned short timedia_single_port[] = {
543 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
544 };
545
546 static const unsigned short timedia_dual_port[] = {
547 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
548 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
549 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
550 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
551 0xD079, 0
552 };
553
554 static const unsigned short timedia_quad_port[] = {
555 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
556 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
557 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
558 0xB157, 0
559 };
560
561 static const unsigned short timedia_eight_port[] = {
562 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
563 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
564 };
565
566 static const struct timedia_struct {
567 int num;
568 const unsigned short *ids;
569 } timedia_data[] = {
570 { 1, timedia_single_port },
571 { 2, timedia_dual_port },
572 { 4, timedia_quad_port },
573 { 8, timedia_eight_port }
574 };
575
576 /*
577 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
578 * listing them individually, this driver merely grabs them all with
579 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
580 * and should be left free to be claimed by parport_serial instead.
581 */
pci_timedia_probe(struct pci_dev * dev)582 static int pci_timedia_probe(struct pci_dev *dev)
583 {
584 /*
585 * Check the third digit of the subdevice ID
586 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
587 */
588 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
589 dev_info(&dev->dev,
590 "ignoring Timedia subdevice %04x for parport_serial\n",
591 dev->subsystem_device);
592 return -ENODEV;
593 }
594
595 return 0;
596 }
597
pci_timedia_init(struct pci_dev * dev)598 static int pci_timedia_init(struct pci_dev *dev)
599 {
600 const unsigned short *ids;
601 int i, j;
602
603 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
604 ids = timedia_data[i].ids;
605 for (j = 0; ids[j]; j++)
606 if (dev->subsystem_device == ids[j])
607 return timedia_data[i].num;
608 }
609 return 0;
610 }
611
612 /*
613 * Timedia/SUNIX uses a mixture of BARs and offsets
614 * Ugh, this is ugly as all hell --- TYT
615 */
616 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)617 pci_timedia_setup(struct serial_private *priv,
618 const struct pciserial_board *board,
619 struct uart_8250_port *port, int idx)
620 {
621 unsigned int bar = 0, offset = board->first_offset;
622
623 switch (idx) {
624 case 0:
625 bar = 0;
626 break;
627 case 1:
628 offset = board->uart_offset;
629 bar = 0;
630 break;
631 case 2:
632 bar = 1;
633 break;
634 case 3:
635 offset = board->uart_offset;
636 /* FALLTHROUGH */
637 case 4: /* BAR 2 */
638 case 5: /* BAR 3 */
639 case 6: /* BAR 4 */
640 case 7: /* BAR 5 */
641 bar = idx - 2;
642 }
643
644 return setup_port(priv, port, bar, offset, board->reg_shift);
645 }
646
647 /*
648 * Some Titan cards are also a little weird
649 */
650 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)651 titan_400l_800l_setup(struct serial_private *priv,
652 const struct pciserial_board *board,
653 struct uart_8250_port *port, int idx)
654 {
655 unsigned int bar, offset = board->first_offset;
656
657 switch (idx) {
658 case 0:
659 bar = 1;
660 break;
661 case 1:
662 bar = 2;
663 break;
664 default:
665 bar = 4;
666 offset = (idx - 2) * board->uart_offset;
667 }
668
669 return setup_port(priv, port, bar, offset, board->reg_shift);
670 }
671
pci_xircom_init(struct pci_dev * dev)672 static int pci_xircom_init(struct pci_dev *dev)
673 {
674 msleep(100);
675 return 0;
676 }
677
pci_ni8420_init(struct pci_dev * dev)678 static int pci_ni8420_init(struct pci_dev *dev)
679 {
680 void __iomem *p;
681 unsigned int bar = 0;
682
683 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
684 moan_device("no memory in bar", dev);
685 return 0;
686 }
687
688 p = pci_ioremap_bar(dev, bar);
689 if (p == NULL)
690 return -ENOMEM;
691
692 /* Enable CPU Interrupt */
693 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
694 p + NI8420_INT_ENABLE_REG);
695
696 iounmap(p);
697 return 0;
698 }
699
700 #define MITE_IOWBSR1_WSIZE 0xa
701 #define MITE_IOWBSR1_WIN_OFFSET 0x800
702 #define MITE_IOWBSR1_WENAB (1 << 7)
703 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
704 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
705 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
706
pci_ni8430_init(struct pci_dev * dev)707 static int pci_ni8430_init(struct pci_dev *dev)
708 {
709 void __iomem *p;
710 struct pci_bus_region region;
711 u32 device_window;
712 unsigned int bar = 0;
713
714 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
715 moan_device("no memory in bar", dev);
716 return 0;
717 }
718
719 p = pci_ioremap_bar(dev, bar);
720 if (p == NULL)
721 return -ENOMEM;
722
723 /*
724 * Set device window address and size in BAR0, while acknowledging that
725 * the resource structure may contain a translated address that differs
726 * from the address the device responds to.
727 */
728 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
729 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
730 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
731 writel(device_window, p + MITE_IOWBSR1);
732
733 /* Set window access to go to RAMSEL IO address space */
734 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
735 p + MITE_IOWCR1);
736
737 /* Enable IO Bus Interrupt 0 */
738 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
739
740 /* Enable CPU Interrupt */
741 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
742
743 iounmap(p);
744 return 0;
745 }
746
747 /* UART Port Control Register */
748 #define NI16550_PCR_OFFSET 0x0f
749 #define NI16550_PCR_RS422 0x00
750 #define NI16550_PCR_ECHO_RS485 0x01
751 #define NI16550_PCR_DTR_RS485 0x02
752 #define NI16550_PCR_AUTO_RS485 0x03
753 #define NI16550_PCR_WIRE_MODE_MASK 0x03
754 #define NI16550_PCR_TXVR_ENABLE_BIT BIT(3)
755 #define NI16550_PCR_RS485_TERMINATION_BIT BIT(6)
756 #define NI16550_ACR_DTR_AUTO_DTR (0x2 << 3)
757 #define NI16550_ACR_DTR_MANUAL_DTR (0x0 << 3)
758
759 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)760 pci_ni8430_setup(struct serial_private *priv,
761 const struct pciserial_board *board,
762 struct uart_8250_port *port, int idx)
763 {
764 struct pci_dev *dev = priv->dev;
765 void __iomem *p;
766 unsigned int bar, offset = board->first_offset;
767
768 if (idx >= board->num_ports)
769 return 1;
770
771 bar = FL_GET_BASE(board->flags);
772 offset += idx * board->uart_offset;
773
774 p = pci_ioremap_bar(dev, bar);
775 if (!p)
776 return -ENOMEM;
777
778 /* enable the transceiver */
779 writeb(readb(p + offset + NI16550_PCR_OFFSET) | NI16550_PCR_TXVR_ENABLE_BIT,
780 p + offset + NI16550_PCR_OFFSET);
781
782 iounmap(p);
783
784 return setup_port(priv, port, bar, offset, board->reg_shift);
785 }
786
pci_ni8431_config_rs485(struct uart_port * port,struct serial_rs485 * rs485)787 static int pci_ni8431_config_rs485(struct uart_port *port,
788 struct serial_rs485 *rs485)
789 {
790 u8 pcr, acr;
791 struct uart_8250_port *up;
792
793 up = container_of(port, struct uart_8250_port, port);
794 acr = up->acr;
795 pcr = port->serial_in(port, NI16550_PCR_OFFSET);
796 pcr &= ~NI16550_PCR_WIRE_MODE_MASK;
797
798 if (rs485->flags & SER_RS485_ENABLED) {
799 /* RS-485 */
800 if ((rs485->flags & SER_RS485_RX_DURING_TX) &&
801 (rs485->flags & SER_RS485_RTS_ON_SEND)) {
802 dev_dbg(port->dev, "Invalid 2-wire mode\n");
803 return -EINVAL;
804 }
805
806 if (rs485->flags & SER_RS485_RX_DURING_TX) {
807 /* Echo */
808 dev_vdbg(port->dev, "2-wire DTR with echo\n");
809 pcr |= NI16550_PCR_ECHO_RS485;
810 acr |= NI16550_ACR_DTR_MANUAL_DTR;
811 } else {
812 /* Auto or DTR */
813 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
814 /* Auto */
815 dev_vdbg(port->dev, "2-wire Auto\n");
816 pcr |= NI16550_PCR_AUTO_RS485;
817 acr |= NI16550_ACR_DTR_AUTO_DTR;
818 } else {
819 /* DTR-controlled */
820 /* No Echo */
821 dev_vdbg(port->dev, "2-wire DTR no echo\n");
822 pcr |= NI16550_PCR_DTR_RS485;
823 acr |= NI16550_ACR_DTR_MANUAL_DTR;
824 }
825 }
826 } else {
827 /* RS-422 */
828 dev_vdbg(port->dev, "4-wire\n");
829 pcr |= NI16550_PCR_RS422;
830 acr |= NI16550_ACR_DTR_MANUAL_DTR;
831 }
832
833 dev_dbg(port->dev, "write pcr: 0x%08x\n", pcr);
834 port->serial_out(port, NI16550_PCR_OFFSET, pcr);
835
836 up->acr = acr;
837 port->serial_out(port, UART_SCR, UART_ACR);
838 port->serial_out(port, UART_ICR, up->acr);
839
840 /* Update the cache. */
841 port->rs485 = *rs485;
842
843 return 0;
844 }
845
pci_ni8431_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * uart,int idx)846 static int pci_ni8431_setup(struct serial_private *priv,
847 const struct pciserial_board *board,
848 struct uart_8250_port *uart, int idx)
849 {
850 u8 pcr, acr;
851 struct pci_dev *dev = priv->dev;
852 void __iomem *addr;
853 unsigned int bar, offset = board->first_offset;
854
855 if (idx >= board->num_ports)
856 return 1;
857
858 bar = FL_GET_BASE(board->flags);
859 offset += idx * board->uart_offset;
860
861 addr = pci_ioremap_bar(dev, bar);
862 if (!addr)
863 return -ENOMEM;
864
865 /* enable the transceiver */
866 writeb(readb(addr + NI16550_PCR_OFFSET) | NI16550_PCR_TXVR_ENABLE_BIT,
867 addr + NI16550_PCR_OFFSET);
868
869 pcr = readb(addr + NI16550_PCR_OFFSET);
870 pcr &= ~NI16550_PCR_WIRE_MODE_MASK;
871
872 /* set wire mode to default RS-422 */
873 pcr |= NI16550_PCR_RS422;
874 acr = NI16550_ACR_DTR_MANUAL_DTR;
875
876 /* write port configuration to register */
877 writeb(pcr, addr + NI16550_PCR_OFFSET);
878
879 /* access and write to UART acr register */
880 writeb(UART_ACR, addr + UART_SCR);
881 writeb(acr, addr + UART_ICR);
882
883 uart->port.rs485_config = &pci_ni8431_config_rs485;
884
885 iounmap(addr);
886
887 return setup_port(priv, uart, bar, offset, board->reg_shift);
888 }
889
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)890 static int pci_netmos_9900_setup(struct serial_private *priv,
891 const struct pciserial_board *board,
892 struct uart_8250_port *port, int idx)
893 {
894 unsigned int bar;
895
896 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
897 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
898 /* netmos apparently orders BARs by datasheet layout, so serial
899 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
900 */
901 bar = 3 * idx;
902
903 return setup_port(priv, port, bar, 0, board->reg_shift);
904 } else {
905 return pci_default_setup(priv, board, port, idx);
906 }
907 }
908
909 /* the 99xx series comes with a range of device IDs and a variety
910 * of capabilities:
911 *
912 * 9900 has varying capabilities and can cascade to sub-controllers
913 * (cascading should be purely internal)
914 * 9904 is hardwired with 4 serial ports
915 * 9912 and 9922 are hardwired with 2 serial ports
916 */
pci_netmos_9900_numports(struct pci_dev * dev)917 static int pci_netmos_9900_numports(struct pci_dev *dev)
918 {
919 unsigned int c = dev->class;
920 unsigned int pi;
921 unsigned short sub_serports;
922
923 pi = c & 0xff;
924
925 if (pi == 2)
926 return 1;
927
928 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
929 /* two possibilities: 0x30ps encodes number of parallel and
930 * serial ports, or 0x1000 indicates *something*. This is not
931 * immediately obvious, since the 2s1p+4s configuration seems
932 * to offer all functionality on functions 0..2, while still
933 * advertising the same function 3 as the 4s+2s1p config.
934 */
935 sub_serports = dev->subsystem_device & 0xf;
936 if (sub_serports > 0)
937 return sub_serports;
938
939 dev_err(&dev->dev,
940 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
941 return 0;
942 }
943
944 moan_device("unknown NetMos/Mostech program interface", dev);
945 return 0;
946 }
947
pci_netmos_init(struct pci_dev * dev)948 static int pci_netmos_init(struct pci_dev *dev)
949 {
950 /* subdevice 0x00PS means <P> parallel, <S> serial */
951 unsigned int num_serial = dev->subsystem_device & 0xf;
952
953 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
954 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
955 return 0;
956
957 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
958 dev->subsystem_device == 0x0299)
959 return 0;
960
961 switch (dev->device) { /* FALLTHROUGH on all */
962 case PCI_DEVICE_ID_NETMOS_9904:
963 case PCI_DEVICE_ID_NETMOS_9912:
964 case PCI_DEVICE_ID_NETMOS_9922:
965 case PCI_DEVICE_ID_NETMOS_9900:
966 num_serial = pci_netmos_9900_numports(dev);
967 break;
968
969 default:
970 break;
971 }
972
973 if (num_serial == 0) {
974 moan_device("unknown NetMos/Mostech device", dev);
975 return -ENODEV;
976 }
977
978 return num_serial;
979 }
980
981 /*
982 * These chips are available with optionally one parallel port and up to
983 * two serial ports. Unfortunately they all have the same product id.
984 *
985 * Basic configuration is done over a region of 32 I/O ports. The base
986 * ioport is called INTA or INTC, depending on docs/other drivers.
987 *
988 * The region of the 32 I/O ports is configured in POSIO0R...
989 */
990
991 /* registers */
992 #define ITE_887x_MISCR 0x9c
993 #define ITE_887x_INTCBAR 0x78
994 #define ITE_887x_UARTBAR 0x7c
995 #define ITE_887x_PS0BAR 0x10
996 #define ITE_887x_POSIO0 0x60
997
998 /* I/O space size */
999 #define ITE_887x_IOSIZE 32
1000 /* I/O space size (bits 26-24; 8 bytes = 011b) */
1001 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
1002 /* I/O space size (bits 26-24; 32 bytes = 101b) */
1003 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
1004 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
1005 #define ITE_887x_POSIO_SPEED (3 << 29)
1006 /* enable IO_Space bit */
1007 #define ITE_887x_POSIO_ENABLE (1 << 31)
1008
pci_ite887x_init(struct pci_dev * dev)1009 static int pci_ite887x_init(struct pci_dev *dev)
1010 {
1011 /* inta_addr are the configuration addresses of the ITE */
1012 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
1013 0x200, 0x280, 0 };
1014 int ret, i, type;
1015 struct resource *iobase = NULL;
1016 u32 miscr, uartbar, ioport;
1017
1018 /* search for the base-ioport */
1019 i = 0;
1020 while (inta_addr[i] && iobase == NULL) {
1021 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
1022 "ite887x");
1023 if (iobase != NULL) {
1024 /* write POSIO0R - speed | size | ioport */
1025 pci_write_config_dword(dev, ITE_887x_POSIO0,
1026 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1027 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
1028 /* write INTCBAR - ioport */
1029 pci_write_config_dword(dev, ITE_887x_INTCBAR,
1030 inta_addr[i]);
1031 ret = inb(inta_addr[i]);
1032 if (ret != 0xff) {
1033 /* ioport connected */
1034 break;
1035 }
1036 release_region(iobase->start, ITE_887x_IOSIZE);
1037 iobase = NULL;
1038 }
1039 i++;
1040 }
1041
1042 if (!inta_addr[i]) {
1043 dev_err(&dev->dev, "ite887x: could not find iobase\n");
1044 return -ENODEV;
1045 }
1046
1047 /* start of undocumented type checking (see parport_pc.c) */
1048 type = inb(iobase->start + 0x18) & 0x0f;
1049
1050 switch (type) {
1051 case 0x2: /* ITE8871 (1P) */
1052 case 0xa: /* ITE8875 (1P) */
1053 ret = 0;
1054 break;
1055 case 0xe: /* ITE8872 (2S1P) */
1056 ret = 2;
1057 break;
1058 case 0x6: /* ITE8873 (1S) */
1059 ret = 1;
1060 break;
1061 case 0x8: /* ITE8874 (2S) */
1062 ret = 2;
1063 break;
1064 default:
1065 moan_device("Unknown ITE887x", dev);
1066 ret = -ENODEV;
1067 }
1068
1069 /* configure all serial ports */
1070 for (i = 0; i < ret; i++) {
1071 /* read the I/O port from the device */
1072 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
1073 &ioport);
1074 ioport &= 0x0000FF00; /* the actual base address */
1075 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
1076 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
1077 ITE_887x_POSIO_IOSIZE_8 | ioport);
1078
1079 /* write the ioport to the UARTBAR */
1080 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
1081 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
1082 uartbar |= (ioport << (16 * i)); /* set the ioport */
1083 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
1084
1085 /* get current config */
1086 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
1087 /* disable interrupts (UARTx_Routing[3:0]) */
1088 miscr &= ~(0xf << (12 - 4 * i));
1089 /* activate the UART (UARTx_En) */
1090 miscr |= 1 << (23 - i);
1091 /* write new config with activated UART */
1092 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
1093 }
1094
1095 if (ret <= 0) {
1096 /* the device has no UARTs if we get here */
1097 release_region(iobase->start, ITE_887x_IOSIZE);
1098 }
1099
1100 return ret;
1101 }
1102
pci_ite887x_exit(struct pci_dev * dev)1103 static void pci_ite887x_exit(struct pci_dev *dev)
1104 {
1105 u32 ioport;
1106 /* the ioport is bit 0-15 in POSIO0R */
1107 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
1108 ioport &= 0xffff;
1109 release_region(ioport, ITE_887x_IOSIZE);
1110 }
1111
1112 /*
1113 * EndRun Technologies.
1114 * Determine the number of ports available on the device.
1115 */
1116 #define PCI_VENDOR_ID_ENDRUN 0x7401
1117 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
1118
pci_endrun_init(struct pci_dev * dev)1119 static int pci_endrun_init(struct pci_dev *dev)
1120 {
1121 u8 __iomem *p;
1122 unsigned long deviceID;
1123 unsigned int number_uarts = 0;
1124
1125 /* EndRun device is all 0xexxx */
1126 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1127 (dev->device & 0xf000) != 0xe000)
1128 return 0;
1129
1130 p = pci_iomap(dev, 0, 5);
1131 if (p == NULL)
1132 return -ENOMEM;
1133
1134 deviceID = ioread32(p);
1135 /* EndRun device */
1136 if (deviceID == 0x07000200) {
1137 number_uarts = ioread8(p + 4);
1138 dev_dbg(&dev->dev,
1139 "%d ports detected on EndRun PCI Express device\n",
1140 number_uarts);
1141 }
1142 pci_iounmap(dev, p);
1143 return number_uarts;
1144 }
1145
1146 /*
1147 * Oxford Semiconductor Inc.
1148 * Check that device is part of the Tornado range of devices, then determine
1149 * the number of ports available on the device.
1150 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1151 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1152 {
1153 u8 __iomem *p;
1154 unsigned long deviceID;
1155 unsigned int number_uarts = 0;
1156
1157 /* OxSemi Tornado devices are all 0xCxxx */
1158 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1159 (dev->device & 0xF000) != 0xC000)
1160 return 0;
1161
1162 p = pci_iomap(dev, 0, 5);
1163 if (p == NULL)
1164 return -ENOMEM;
1165
1166 deviceID = ioread32(p);
1167 /* Tornado device */
1168 if (deviceID == 0x07000200) {
1169 number_uarts = ioread8(p + 4);
1170 dev_dbg(&dev->dev,
1171 "%d ports detected on Oxford PCI Express device\n",
1172 number_uarts);
1173 }
1174 pci_iounmap(dev, p);
1175 return number_uarts;
1176 }
1177
pci_asix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1178 static int pci_asix_setup(struct serial_private *priv,
1179 const struct pciserial_board *board,
1180 struct uart_8250_port *port, int idx)
1181 {
1182 port->bugs |= UART_BUG_PARITY;
1183 return pci_default_setup(priv, board, port, idx);
1184 }
1185
1186 /* Quatech devices have their own extra interface features */
1187
1188 struct quatech_feature {
1189 u16 devid;
1190 bool amcc;
1191 };
1192
1193 #define QPCR_TEST_FOR1 0x3F
1194 #define QPCR_TEST_GET1 0x00
1195 #define QPCR_TEST_FOR2 0x40
1196 #define QPCR_TEST_GET2 0x40
1197 #define QPCR_TEST_FOR3 0x80
1198 #define QPCR_TEST_GET3 0x40
1199 #define QPCR_TEST_FOR4 0xC0
1200 #define QPCR_TEST_GET4 0x80
1201
1202 #define QOPR_CLOCK_X1 0x0000
1203 #define QOPR_CLOCK_X2 0x0001
1204 #define QOPR_CLOCK_X4 0x0002
1205 #define QOPR_CLOCK_X8 0x0003
1206 #define QOPR_CLOCK_RATE_MASK 0x0003
1207
1208
1209 static struct quatech_feature quatech_cards[] = {
1210 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1211 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1212 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1213 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1214 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1215 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1216 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1217 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1218 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1219 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1220 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1221 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1222 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1223 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1224 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1225 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1226 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1227 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1228 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1229 { 0, }
1230 };
1231
pci_quatech_amcc(u16 devid)1232 static int pci_quatech_amcc(u16 devid)
1233 {
1234 struct quatech_feature *qf = &quatech_cards[0];
1235 while (qf->devid) {
1236 if (qf->devid == devid)
1237 return qf->amcc;
1238 qf++;
1239 }
1240 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1241 return 0;
1242 };
1243
pci_quatech_rqopr(struct uart_8250_port * port)1244 static int pci_quatech_rqopr(struct uart_8250_port *port)
1245 {
1246 unsigned long base = port->port.iobase;
1247 u8 LCR, val;
1248
1249 LCR = inb(base + UART_LCR);
1250 outb(0xBF, base + UART_LCR);
1251 val = inb(base + UART_SCR);
1252 outb(LCR, base + UART_LCR);
1253 return val;
1254 }
1255
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1256 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1257 {
1258 unsigned long base = port->port.iobase;
1259 u8 LCR;
1260
1261 LCR = inb(base + UART_LCR);
1262 outb(0xBF, base + UART_LCR);
1263 inb(base + UART_SCR);
1264 outb(qopr, base + UART_SCR);
1265 outb(LCR, base + UART_LCR);
1266 }
1267
pci_quatech_rqmcr(struct uart_8250_port * port)1268 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1269 {
1270 unsigned long base = port->port.iobase;
1271 u8 LCR, val, qmcr;
1272
1273 LCR = inb(base + UART_LCR);
1274 outb(0xBF, base + UART_LCR);
1275 val = inb(base + UART_SCR);
1276 outb(val | 0x10, base + UART_SCR);
1277 qmcr = inb(base + UART_MCR);
1278 outb(val, base + UART_SCR);
1279 outb(LCR, base + UART_LCR);
1280
1281 return qmcr;
1282 }
1283
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1284 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1285 {
1286 unsigned long base = port->port.iobase;
1287 u8 LCR, val;
1288
1289 LCR = inb(base + UART_LCR);
1290 outb(0xBF, base + UART_LCR);
1291 val = inb(base + UART_SCR);
1292 outb(val | 0x10, base + UART_SCR);
1293 outb(qmcr, base + UART_MCR);
1294 outb(val, base + UART_SCR);
1295 outb(LCR, base + UART_LCR);
1296 }
1297
pci_quatech_has_qmcr(struct uart_8250_port * port)1298 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1299 {
1300 unsigned long base = port->port.iobase;
1301 u8 LCR, val;
1302
1303 LCR = inb(base + UART_LCR);
1304 outb(0xBF, base + UART_LCR);
1305 val = inb(base + UART_SCR);
1306 if (val & 0x20) {
1307 outb(0x80, UART_LCR);
1308 if (!(inb(UART_SCR) & 0x20)) {
1309 outb(LCR, base + UART_LCR);
1310 return 1;
1311 }
1312 }
1313 return 0;
1314 }
1315
pci_quatech_test(struct uart_8250_port * port)1316 static int pci_quatech_test(struct uart_8250_port *port)
1317 {
1318 u8 reg, qopr;
1319
1320 qopr = pci_quatech_rqopr(port);
1321 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1322 reg = pci_quatech_rqopr(port) & 0xC0;
1323 if (reg != QPCR_TEST_GET1)
1324 return -EINVAL;
1325 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1326 reg = pci_quatech_rqopr(port) & 0xC0;
1327 if (reg != QPCR_TEST_GET2)
1328 return -EINVAL;
1329 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1330 reg = pci_quatech_rqopr(port) & 0xC0;
1331 if (reg != QPCR_TEST_GET3)
1332 return -EINVAL;
1333 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1334 reg = pci_quatech_rqopr(port) & 0xC0;
1335 if (reg != QPCR_TEST_GET4)
1336 return -EINVAL;
1337
1338 pci_quatech_wqopr(port, qopr);
1339 return 0;
1340 }
1341
pci_quatech_clock(struct uart_8250_port * port)1342 static int pci_quatech_clock(struct uart_8250_port *port)
1343 {
1344 u8 qopr, reg, set;
1345 unsigned long clock;
1346
1347 if (pci_quatech_test(port) < 0)
1348 return 1843200;
1349
1350 qopr = pci_quatech_rqopr(port);
1351
1352 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1353 reg = pci_quatech_rqopr(port);
1354 if (reg & QOPR_CLOCK_X8) {
1355 clock = 1843200;
1356 goto out;
1357 }
1358 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1359 reg = pci_quatech_rqopr(port);
1360 if (!(reg & QOPR_CLOCK_X8)) {
1361 clock = 1843200;
1362 goto out;
1363 }
1364 reg &= QOPR_CLOCK_X8;
1365 if (reg == QOPR_CLOCK_X2) {
1366 clock = 3685400;
1367 set = QOPR_CLOCK_X2;
1368 } else if (reg == QOPR_CLOCK_X4) {
1369 clock = 7372800;
1370 set = QOPR_CLOCK_X4;
1371 } else if (reg == QOPR_CLOCK_X8) {
1372 clock = 14745600;
1373 set = QOPR_CLOCK_X8;
1374 } else {
1375 clock = 1843200;
1376 set = QOPR_CLOCK_X1;
1377 }
1378 qopr &= ~QOPR_CLOCK_RATE_MASK;
1379 qopr |= set;
1380
1381 out:
1382 pci_quatech_wqopr(port, qopr);
1383 return clock;
1384 }
1385
pci_quatech_rs422(struct uart_8250_port * port)1386 static int pci_quatech_rs422(struct uart_8250_port *port)
1387 {
1388 u8 qmcr;
1389 int rs422 = 0;
1390
1391 if (!pci_quatech_has_qmcr(port))
1392 return 0;
1393 qmcr = pci_quatech_rqmcr(port);
1394 pci_quatech_wqmcr(port, 0xFF);
1395 if (pci_quatech_rqmcr(port))
1396 rs422 = 1;
1397 pci_quatech_wqmcr(port, qmcr);
1398 return rs422;
1399 }
1400
pci_quatech_init(struct pci_dev * dev)1401 static int pci_quatech_init(struct pci_dev *dev)
1402 {
1403 if (pci_quatech_amcc(dev->device)) {
1404 unsigned long base = pci_resource_start(dev, 0);
1405 if (base) {
1406 u32 tmp;
1407
1408 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1409 tmp = inl(base + 0x3c);
1410 outl(tmp | 0x01000000, base + 0x3c);
1411 outl(tmp &= ~0x01000000, base + 0x3c);
1412 }
1413 }
1414 return 0;
1415 }
1416
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1417 static int pci_quatech_setup(struct serial_private *priv,
1418 const struct pciserial_board *board,
1419 struct uart_8250_port *port, int idx)
1420 {
1421 /* Needed by pci_quatech calls below */
1422 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1423 /* Set up the clocking */
1424 port->port.uartclk = pci_quatech_clock(port);
1425 /* For now just warn about RS422 */
1426 if (pci_quatech_rs422(port))
1427 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1428 return pci_default_setup(priv, board, port, idx);
1429 }
1430
pci_quatech_exit(struct pci_dev * dev)1431 static void pci_quatech_exit(struct pci_dev *dev)
1432 {
1433 }
1434
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1435 static int pci_default_setup(struct serial_private *priv,
1436 const struct pciserial_board *board,
1437 struct uart_8250_port *port, int idx)
1438 {
1439 unsigned int bar, offset = board->first_offset, maxnr;
1440
1441 bar = FL_GET_BASE(board->flags);
1442 if (board->flags & FL_BASE_BARS)
1443 bar += idx;
1444 else
1445 offset += idx * board->uart_offset;
1446
1447 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1448 (board->reg_shift + 3);
1449
1450 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1451 return 1;
1452
1453 return setup_port(priv, port, bar, offset, board->reg_shift);
1454 }
1455 static void
pericom_do_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int quot_frac)1456 pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1457 unsigned int quot, unsigned int quot_frac)
1458 {
1459 int scr;
1460 int lcr;
1461 int actual_baud;
1462 int tolerance;
1463
1464 for (scr = 5 ; scr <= 15 ; scr++) {
1465 actual_baud = 921600 * 16 / scr;
1466 tolerance = actual_baud / 50;
1467
1468 if ((baud < actual_baud + tolerance) &&
1469 (baud > actual_baud - tolerance)) {
1470
1471 lcr = serial_port_in(port, UART_LCR);
1472 serial_port_out(port, UART_LCR, lcr | 0x80);
1473
1474 serial_port_out(port, UART_DLL, 1);
1475 serial_port_out(port, UART_DLM, 0);
1476 serial_port_out(port, 2, 16 - scr);
1477 serial_port_out(port, UART_LCR, lcr);
1478 return;
1479 } else if (baud > actual_baud) {
1480 break;
1481 }
1482 }
1483 serial8250_do_set_divisor(port, baud, quot, quot_frac);
1484 }
pci_pericom_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1485 static int pci_pericom_setup(struct serial_private *priv,
1486 const struct pciserial_board *board,
1487 struct uart_8250_port *port, int idx)
1488 {
1489 unsigned int bar, offset = board->first_offset, maxnr;
1490
1491 bar = FL_GET_BASE(board->flags);
1492 if (board->flags & FL_BASE_BARS)
1493 bar += idx;
1494 else
1495 offset += idx * board->uart_offset;
1496
1497
1498 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1499 (board->reg_shift + 3);
1500
1501 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1502 return 1;
1503
1504 port->port.set_divisor = pericom_do_set_divisor;
1505
1506 return setup_port(priv, port, bar, offset, board->reg_shift);
1507 }
1508
pci_pericom_setup_four_at_eight(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1509 static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1510 const struct pciserial_board *board,
1511 struct uart_8250_port *port, int idx)
1512 {
1513 unsigned int bar, offset = board->first_offset, maxnr;
1514
1515 bar = FL_GET_BASE(board->flags);
1516 if (board->flags & FL_BASE_BARS)
1517 bar += idx;
1518 else
1519 offset += idx * board->uart_offset;
1520
1521 if (idx==3)
1522 offset = 0x38;
1523
1524 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1525 (board->reg_shift + 3);
1526
1527 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1528 return 1;
1529
1530 port->port.set_divisor = pericom_do_set_divisor;
1531
1532 return setup_port(priv, port, bar, offset, board->reg_shift);
1533 }
1534
1535 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1536 ce4100_serial_setup(struct serial_private *priv,
1537 const struct pciserial_board *board,
1538 struct uart_8250_port *port, int idx)
1539 {
1540 int ret;
1541
1542 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1543 port->port.iotype = UPIO_MEM32;
1544 port->port.type = PORT_XSCALE;
1545 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1546 port->port.regshift = 2;
1547
1548 return ret;
1549 }
1550
1551 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1552 pci_omegapci_setup(struct serial_private *priv,
1553 const struct pciserial_board *board,
1554 struct uart_8250_port *port, int idx)
1555 {
1556 return setup_port(priv, port, 2, idx * 8, 0);
1557 }
1558
1559 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1560 pci_brcm_trumanage_setup(struct serial_private *priv,
1561 const struct pciserial_board *board,
1562 struct uart_8250_port *port, int idx)
1563 {
1564 int ret = pci_default_setup(priv, board, port, idx);
1565
1566 port->port.type = PORT_BRCM_TRUMANAGE;
1567 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1568 return ret;
1569 }
1570
1571 /* RTS will control by MCR if this bit is 0 */
1572 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1573 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1574 #define FINTEK_RTS_INVERT BIT(5)
1575
1576 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)1577 static int pci_fintek_rs485_config(struct uart_port *port,
1578 struct serial_rs485 *rs485)
1579 {
1580 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1581 u8 setting;
1582 u8 *index = (u8 *) port->private_data;
1583
1584 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1585
1586 if (!rs485)
1587 rs485 = &port->rs485;
1588 else if (rs485->flags & SER_RS485_ENABLED)
1589 memset(rs485->padding, 0, sizeof(rs485->padding));
1590 else
1591 memset(rs485, 0, sizeof(*rs485));
1592
1593 /* F81504/508/512 not support RTS delay before or after send */
1594 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1595
1596 if (rs485->flags & SER_RS485_ENABLED) {
1597 /* Enable RTS H/W control mode */
1598 setting |= FINTEK_RTS_CONTROL_BY_HW;
1599
1600 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1601 /* RTS driving high on TX */
1602 setting &= ~FINTEK_RTS_INVERT;
1603 } else {
1604 /* RTS driving low on TX */
1605 setting |= FINTEK_RTS_INVERT;
1606 }
1607
1608 rs485->delay_rts_after_send = 0;
1609 rs485->delay_rts_before_send = 0;
1610 } else {
1611 /* Disable RTS H/W control mode */
1612 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1613 }
1614
1615 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1616
1617 if (rs485 != &port->rs485)
1618 port->rs485 = *rs485;
1619
1620 return 0;
1621 }
1622
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1623 static int pci_fintek_setup(struct serial_private *priv,
1624 const struct pciserial_board *board,
1625 struct uart_8250_port *port, int idx)
1626 {
1627 struct pci_dev *pdev = priv->dev;
1628 u8 *data;
1629 u8 config_base;
1630 u16 iobase;
1631
1632 config_base = 0x40 + 0x08 * idx;
1633
1634 /* Get the io address from configuration space */
1635 pci_read_config_word(pdev, config_base + 4, &iobase);
1636
1637 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1638
1639 port->port.iotype = UPIO_PORT;
1640 port->port.iobase = iobase;
1641 port->port.rs485_config = pci_fintek_rs485_config;
1642
1643 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1644 if (!data)
1645 return -ENOMEM;
1646
1647 /* preserve index in PCI configuration space */
1648 *data = idx;
1649 port->port.private_data = data;
1650
1651 return 0;
1652 }
1653
pci_fintek_init(struct pci_dev * dev)1654 static int pci_fintek_init(struct pci_dev *dev)
1655 {
1656 unsigned long iobase;
1657 u32 max_port, i;
1658 resource_size_t bar_data[3];
1659 u8 config_base;
1660 struct serial_private *priv = pci_get_drvdata(dev);
1661 struct uart_8250_port *port;
1662
1663 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1664 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1665 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1666 return -ENODEV;
1667
1668 switch (dev->device) {
1669 case 0x1104: /* 4 ports */
1670 case 0x1108: /* 8 ports */
1671 max_port = dev->device & 0xff;
1672 break;
1673 case 0x1112: /* 12 ports */
1674 max_port = 12;
1675 break;
1676 default:
1677 return -EINVAL;
1678 }
1679
1680 /* Get the io address dispatch from the BIOS */
1681 bar_data[0] = pci_resource_start(dev, 5);
1682 bar_data[1] = pci_resource_start(dev, 4);
1683 bar_data[2] = pci_resource_start(dev, 3);
1684
1685 for (i = 0; i < max_port; ++i) {
1686 /* UART0 configuration offset start from 0x40 */
1687 config_base = 0x40 + 0x08 * i;
1688
1689 /* Calculate Real IO Port */
1690 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1691
1692 /* Enable UART I/O port */
1693 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1694
1695 /* Select 128-byte FIFO and 8x FIFO threshold */
1696 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1697
1698 /* LSB UART */
1699 pci_write_config_byte(dev, config_base + 0x04,
1700 (u8)(iobase & 0xff));
1701
1702 /* MSB UART */
1703 pci_write_config_byte(dev, config_base + 0x05,
1704 (u8)((iobase & 0xff00) >> 8));
1705
1706 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1707
1708 if (priv) {
1709 /* re-apply RS232/485 mode when
1710 * pciserial_resume_ports()
1711 */
1712 port = serial8250_get_port(priv->line[i]);
1713 pci_fintek_rs485_config(&port->port, NULL);
1714 } else {
1715 /* First init without port data
1716 * force init to RS232 Mode
1717 */
1718 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1719 }
1720 }
1721
1722 return max_port;
1723 }
1724
f815xxa_mem_serial_out(struct uart_port * p,int offset,int value)1725 static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1726 {
1727 struct f815xxa_data *data = p->private_data;
1728 unsigned long flags;
1729
1730 spin_lock_irqsave(&data->lock, flags);
1731 writeb(value, p->membase + offset);
1732 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1733 spin_unlock_irqrestore(&data->lock, flags);
1734 }
1735
pci_fintek_f815xxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1736 static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1737 const struct pciserial_board *board,
1738 struct uart_8250_port *port, int idx)
1739 {
1740 struct pci_dev *pdev = priv->dev;
1741 struct f815xxa_data *data;
1742
1743 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1744 if (!data)
1745 return -ENOMEM;
1746
1747 data->idx = idx;
1748 spin_lock_init(&data->lock);
1749
1750 port->port.private_data = data;
1751 port->port.iotype = UPIO_MEM;
1752 port->port.flags |= UPF_IOREMAP;
1753 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1754 port->port.serial_out = f815xxa_mem_serial_out;
1755
1756 return 0;
1757 }
1758
pci_fintek_f815xxa_init(struct pci_dev * dev)1759 static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1760 {
1761 u32 max_port, i;
1762 int config_base;
1763
1764 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1765 return -ENODEV;
1766
1767 switch (dev->device) {
1768 case 0x1204: /* 4 ports */
1769 case 0x1208: /* 8 ports */
1770 max_port = dev->device & 0xff;
1771 break;
1772 case 0x1212: /* 12 ports */
1773 max_port = 12;
1774 break;
1775 default:
1776 return -EINVAL;
1777 }
1778
1779 /* Set to mmio decode */
1780 pci_write_config_byte(dev, 0x209, 0x40);
1781
1782 for (i = 0; i < max_port; ++i) {
1783 /* UART0 configuration offset start from 0x2A0 */
1784 config_base = 0x2A0 + 0x08 * i;
1785
1786 /* Select 128-byte FIFO and 8x FIFO threshold */
1787 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1788
1789 /* Enable UART I/O port */
1790 pci_write_config_byte(dev, config_base + 0, 0x01);
1791 }
1792
1793 return max_port;
1794 }
1795
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1796 static int skip_tx_en_setup(struct serial_private *priv,
1797 const struct pciserial_board *board,
1798 struct uart_8250_port *port, int idx)
1799 {
1800 port->port.quirks |= UPQ_NO_TXEN_TEST;
1801 dev_dbg(&priv->dev->dev,
1802 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1803 priv->dev->vendor, priv->dev->device,
1804 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1805
1806 return pci_default_setup(priv, board, port, idx);
1807 }
1808
kt_handle_break(struct uart_port * p)1809 static void kt_handle_break(struct uart_port *p)
1810 {
1811 struct uart_8250_port *up = up_to_u8250p(p);
1812 /*
1813 * On receipt of a BI, serial device in Intel ME (Intel
1814 * management engine) needs to have its fifos cleared for sane
1815 * SOL (Serial Over Lan) output.
1816 */
1817 serial8250_clear_and_reinit_fifos(up);
1818 }
1819
kt_serial_in(struct uart_port * p,int offset)1820 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1821 {
1822 struct uart_8250_port *up = up_to_u8250p(p);
1823 unsigned int val;
1824
1825 /*
1826 * When the Intel ME (management engine) gets reset its serial
1827 * port registers could return 0 momentarily. Functions like
1828 * serial8250_console_write, read and save the IER, perform
1829 * some operation and then restore it. In order to avoid
1830 * setting IER register inadvertently to 0, if the value read
1831 * is 0, double check with ier value in uart_8250_port and use
1832 * that instead. up->ier should be the same value as what is
1833 * currently configured.
1834 */
1835 val = inb(p->iobase + offset);
1836 if (offset == UART_IER) {
1837 if (val == 0)
1838 val = up->ier;
1839 }
1840 return val;
1841 }
1842
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1843 static int kt_serial_setup(struct serial_private *priv,
1844 const struct pciserial_board *board,
1845 struct uart_8250_port *port, int idx)
1846 {
1847 port->port.flags |= UPF_BUG_THRE;
1848 port->port.serial_in = kt_serial_in;
1849 port->port.handle_break = kt_handle_break;
1850 return skip_tx_en_setup(priv, board, port, idx);
1851 }
1852
pci_eg20t_init(struct pci_dev * dev)1853 static int pci_eg20t_init(struct pci_dev *dev)
1854 {
1855 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1856 return -ENODEV;
1857 #else
1858 return 0;
1859 #endif
1860 }
1861
1862 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1863 pci_wch_ch353_setup(struct serial_private *priv,
1864 const struct pciserial_board *board,
1865 struct uart_8250_port *port, int idx)
1866 {
1867 port->port.flags |= UPF_FIXED_TYPE;
1868 port->port.type = PORT_16550A;
1869 return pci_default_setup(priv, board, port, idx);
1870 }
1871
1872 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1873 pci_wch_ch355_setup(struct serial_private *priv,
1874 const struct pciserial_board *board,
1875 struct uart_8250_port *port, int idx)
1876 {
1877 port->port.flags |= UPF_FIXED_TYPE;
1878 port->port.type = PORT_16550A;
1879 return pci_default_setup(priv, board, port, idx);
1880 }
1881
1882 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1883 pci_wch_ch38x_setup(struct serial_private *priv,
1884 const struct pciserial_board *board,
1885 struct uart_8250_port *port, int idx)
1886 {
1887 port->port.flags |= UPF_FIXED_TYPE;
1888 port->port.type = PORT_16850;
1889 return pci_default_setup(priv, board, port, idx);
1890 }
1891
1892 static int
pci_sunix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1893 pci_sunix_setup(struct serial_private *priv,
1894 const struct pciserial_board *board,
1895 struct uart_8250_port *port, int idx)
1896 {
1897 int bar;
1898 int offset;
1899
1900 port->port.flags |= UPF_FIXED_TYPE;
1901 port->port.type = PORT_SUNIX;
1902
1903 if (idx < 4) {
1904 bar = 0;
1905 offset = idx * board->uart_offset;
1906 } else {
1907 bar = 1;
1908 idx -= 4;
1909 idx = div_s64_rem(idx, 4, &offset);
1910 offset = idx * 64 + offset * board->uart_offset;
1911 }
1912
1913 return setup_port(priv, port, bar, offset, 0);
1914 }
1915
1916 static int
pci_moxa_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1917 pci_moxa_setup(struct serial_private *priv,
1918 const struct pciserial_board *board,
1919 struct uart_8250_port *port, int idx)
1920 {
1921 unsigned int bar = FL_GET_BASE(board->flags);
1922 int offset;
1923
1924 if (board->num_ports == 4 && idx == 3)
1925 offset = 7 * board->uart_offset;
1926 else
1927 offset = idx * board->uart_offset;
1928
1929 return setup_port(priv, port, bar, offset, 0);
1930 }
1931
1932 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1933 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1934 #define PCI_DEVICE_ID_OCTPRO 0x0001
1935 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1936 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1937 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1938 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1939 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1940 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1941 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1942 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1943 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1944 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1945 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1946 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1947 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1948 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1949 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1950 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1951 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1952 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1953 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1954 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1955 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1956 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1957 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1958 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1959 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1960 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1961 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1962 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1963 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1964 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1965 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1966 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1967 #define PCI_VENDOR_ID_WCH 0x4348
1968 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1969 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1970 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1971 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1972 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1973 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1974 #define PCI_VENDOR_ID_AGESTAR 0x5372
1975 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1976 #define PCI_VENDOR_ID_ASIX 0x9710
1977 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1978 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1979
1980 #define PCIE_VENDOR_ID_WCH 0x1c00
1981 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1982 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1983 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1984
1985 #define PCI_VENDOR_ID_PERICOM 0x12D8
1986 #define PCI_DEVICE_ID_PERICOM_PI7C9X7951 0x7951
1987 #define PCI_DEVICE_ID_PERICOM_PI7C9X7952 0x7952
1988 #define PCI_DEVICE_ID_PERICOM_PI7C9X7954 0x7954
1989 #define PCI_DEVICE_ID_PERICOM_PI7C9X7958 0x7958
1990
1991 #define PCI_VENDOR_ID_ACCESIO 0x494f
1992 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1993 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1994 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1995 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1996 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1997 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1998 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1999 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
2000 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
2001 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
2002 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
2003 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
2004 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
2005 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
2006 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
2007 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
2008 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
2009 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
2010 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
2011 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
2012 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
2013 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
2014 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
2015 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
2016 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
2017 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
2018 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
2019 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
2020 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
2021 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
2022 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
2023 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
2024 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
2025
2026 #define PCIE_DEVICE_ID_NI_PXIE8430_2328 0x74C2
2027 #define PCIE_DEVICE_ID_NI_PXIE8430_23216 0x74C1
2028 #define PCI_DEVICE_ID_NI_PXI8431_4852 0x7081
2029 #define PCI_DEVICE_ID_NI_PXI8431_4854 0x70DE
2030 #define PCI_DEVICE_ID_NI_PXI8431_4858 0x70E3
2031 #define PCI_DEVICE_ID_NI_PXI8433_4852 0x70E9
2032 #define PCI_DEVICE_ID_NI_PXI8433_4854 0x70ED
2033 #define PCIE_DEVICE_ID_NI_PXIE8431_4858 0x74C4
2034 #define PCIE_DEVICE_ID_NI_PXIE8431_48516 0x74C3
2035
2036 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024
2037 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025
2038 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045
2039 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144
2040 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160
2041 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161
2042 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182
2043 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183
2044 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322
2045 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342
2046 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381
2047 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683
2048
2049 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
2050 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
2051 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
2052
2053 /*
2054 * Master list of serial port init/setup/exit quirks.
2055 * This does not describe the general nature of the port.
2056 * (ie, baud base, number and location of ports, etc)
2057 *
2058 * This list is ordered alphabetically by vendor then device.
2059 * Specific entries must come before more generic entries.
2060 */
2061 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
2062 /*
2063 * ADDI-DATA GmbH communication cards <info@addi-data.com>
2064 */
2065 {
2066 .vendor = PCI_VENDOR_ID_AMCC,
2067 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
2068 .subvendor = PCI_ANY_ID,
2069 .subdevice = PCI_ANY_ID,
2070 .setup = addidata_apci7800_setup,
2071 },
2072 /*
2073 * AFAVLAB cards - these may be called via parport_serial
2074 * It is not clear whether this applies to all products.
2075 */
2076 {
2077 .vendor = PCI_VENDOR_ID_AFAVLAB,
2078 .device = PCI_ANY_ID,
2079 .subvendor = PCI_ANY_ID,
2080 .subdevice = PCI_ANY_ID,
2081 .setup = afavlab_setup,
2082 },
2083 /*
2084 * HP Diva
2085 */
2086 {
2087 .vendor = PCI_VENDOR_ID_HP,
2088 .device = PCI_DEVICE_ID_HP_DIVA,
2089 .subvendor = PCI_ANY_ID,
2090 .subdevice = PCI_ANY_ID,
2091 .init = pci_hp_diva_init,
2092 .setup = pci_hp_diva_setup,
2093 },
2094 /*
2095 * Intel
2096 */
2097 {
2098 .vendor = PCI_VENDOR_ID_INTEL,
2099 .device = PCI_DEVICE_ID_INTEL_80960_RP,
2100 .subvendor = 0xe4bf,
2101 .subdevice = PCI_ANY_ID,
2102 .init = pci_inteli960ni_init,
2103 .setup = pci_default_setup,
2104 },
2105 {
2106 .vendor = PCI_VENDOR_ID_INTEL,
2107 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
2108 .subvendor = PCI_ANY_ID,
2109 .subdevice = PCI_ANY_ID,
2110 .setup = skip_tx_en_setup,
2111 },
2112 {
2113 .vendor = PCI_VENDOR_ID_INTEL,
2114 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
2115 .subvendor = PCI_ANY_ID,
2116 .subdevice = PCI_ANY_ID,
2117 .setup = skip_tx_en_setup,
2118 },
2119 {
2120 .vendor = PCI_VENDOR_ID_INTEL,
2121 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
2122 .subvendor = PCI_ANY_ID,
2123 .subdevice = PCI_ANY_ID,
2124 .setup = skip_tx_en_setup,
2125 },
2126 {
2127 .vendor = PCI_VENDOR_ID_INTEL,
2128 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
2129 .subvendor = PCI_ANY_ID,
2130 .subdevice = PCI_ANY_ID,
2131 .setup = ce4100_serial_setup,
2132 },
2133 {
2134 .vendor = PCI_VENDOR_ID_INTEL,
2135 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2136 .subvendor = PCI_ANY_ID,
2137 .subdevice = PCI_ANY_ID,
2138 .setup = kt_serial_setup,
2139 },
2140 /*
2141 * ITE
2142 */
2143 {
2144 .vendor = PCI_VENDOR_ID_ITE,
2145 .device = PCI_DEVICE_ID_ITE_8872,
2146 .subvendor = PCI_ANY_ID,
2147 .subdevice = PCI_ANY_ID,
2148 .init = pci_ite887x_init,
2149 .setup = pci_default_setup,
2150 .exit = pci_ite887x_exit,
2151 },
2152 /*
2153 * National Instruments
2154 */
2155 {
2156 .vendor = PCI_VENDOR_ID_NI,
2157 .device = PCI_DEVICE_ID_NI_PCI23216,
2158 .subvendor = PCI_ANY_ID,
2159 .subdevice = PCI_ANY_ID,
2160 .init = pci_ni8420_init,
2161 .setup = pci_default_setup,
2162 .exit = pci_ni8420_exit,
2163 },
2164 {
2165 .vendor = PCI_VENDOR_ID_NI,
2166 .device = PCI_DEVICE_ID_NI_PCI2328,
2167 .subvendor = PCI_ANY_ID,
2168 .subdevice = PCI_ANY_ID,
2169 .init = pci_ni8420_init,
2170 .setup = pci_default_setup,
2171 .exit = pci_ni8420_exit,
2172 },
2173 {
2174 .vendor = PCI_VENDOR_ID_NI,
2175 .device = PCI_DEVICE_ID_NI_PCI2324,
2176 .subvendor = PCI_ANY_ID,
2177 .subdevice = PCI_ANY_ID,
2178 .init = pci_ni8420_init,
2179 .setup = pci_default_setup,
2180 .exit = pci_ni8420_exit,
2181 },
2182 {
2183 .vendor = PCI_VENDOR_ID_NI,
2184 .device = PCI_DEVICE_ID_NI_PCI2322,
2185 .subvendor = PCI_ANY_ID,
2186 .subdevice = PCI_ANY_ID,
2187 .init = pci_ni8420_init,
2188 .setup = pci_default_setup,
2189 .exit = pci_ni8420_exit,
2190 },
2191 {
2192 .vendor = PCI_VENDOR_ID_NI,
2193 .device = PCI_DEVICE_ID_NI_PCI2324I,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .init = pci_ni8420_init,
2197 .setup = pci_default_setup,
2198 .exit = pci_ni8420_exit,
2199 },
2200 {
2201 .vendor = PCI_VENDOR_ID_NI,
2202 .device = PCI_DEVICE_ID_NI_PCI2322I,
2203 .subvendor = PCI_ANY_ID,
2204 .subdevice = PCI_ANY_ID,
2205 .init = pci_ni8420_init,
2206 .setup = pci_default_setup,
2207 .exit = pci_ni8420_exit,
2208 },
2209 {
2210 .vendor = PCI_VENDOR_ID_NI,
2211 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
2212 .subvendor = PCI_ANY_ID,
2213 .subdevice = PCI_ANY_ID,
2214 .init = pci_ni8420_init,
2215 .setup = pci_default_setup,
2216 .exit = pci_ni8420_exit,
2217 },
2218 {
2219 .vendor = PCI_VENDOR_ID_NI,
2220 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
2221 .subvendor = PCI_ANY_ID,
2222 .subdevice = PCI_ANY_ID,
2223 .init = pci_ni8420_init,
2224 .setup = pci_default_setup,
2225 .exit = pci_ni8420_exit,
2226 },
2227 {
2228 .vendor = PCI_VENDOR_ID_NI,
2229 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
2230 .subvendor = PCI_ANY_ID,
2231 .subdevice = PCI_ANY_ID,
2232 .init = pci_ni8420_init,
2233 .setup = pci_default_setup,
2234 .exit = pci_ni8420_exit,
2235 },
2236 {
2237 .vendor = PCI_VENDOR_ID_NI,
2238 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
2239 .subvendor = PCI_ANY_ID,
2240 .subdevice = PCI_ANY_ID,
2241 .init = pci_ni8420_init,
2242 .setup = pci_default_setup,
2243 .exit = pci_ni8420_exit,
2244 },
2245 {
2246 .vendor = PCI_VENDOR_ID_NI,
2247 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
2248 .subvendor = PCI_ANY_ID,
2249 .subdevice = PCI_ANY_ID,
2250 .init = pci_ni8420_init,
2251 .setup = pci_default_setup,
2252 .exit = pci_ni8420_exit,
2253 },
2254 {
2255 .vendor = PCI_VENDOR_ID_NI,
2256 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
2257 .subvendor = PCI_ANY_ID,
2258 .subdevice = PCI_ANY_ID,
2259 .init = pci_ni8420_init,
2260 .setup = pci_default_setup,
2261 .exit = pci_ni8420_exit,
2262 },
2263 {
2264 .vendor = PCI_VENDOR_ID_NI,
2265 .device = PCI_ANY_ID,
2266 .subvendor = PCI_ANY_ID,
2267 .subdevice = PCI_ANY_ID,
2268 .init = pci_ni8430_init,
2269 .setup = pci_ni8430_setup,
2270 .exit = pci_ni8430_exit,
2271 },
2272 {
2273 .vendor = PCI_VENDOR_ID_NI,
2274 .device = PCIE_DEVICE_ID_NI_PXIE8430_2328,
2275 .subvendor = PCI_ANY_ID,
2276 .subdevice = PCI_ANY_ID,
2277 .init = pci_ni8430_init,
2278 .setup = pci_ni8430_setup,
2279 .exit = pci_ni8430_exit,
2280 },
2281 {
2282 .vendor = PCI_VENDOR_ID_NI,
2283 .device = PCIE_DEVICE_ID_NI_PXIE8430_23216,
2284 .subvendor = PCI_ANY_ID,
2285 .subdevice = PCI_ANY_ID,
2286 .init = pci_ni8430_init,
2287 .setup = pci_ni8430_setup,
2288 .exit = pci_ni8430_exit,
2289 },
2290 {
2291 .vendor = PCI_VENDOR_ID_NI,
2292 .device = PCI_DEVICE_ID_NI_PXI8431_4852,
2293 .subvendor = PCI_ANY_ID,
2294 .subdevice = PCI_ANY_ID,
2295 .init = pci_ni8430_init,
2296 .setup = pci_ni8431_setup,
2297 .exit = pci_ni8430_exit,
2298 },
2299 {
2300 .vendor = PCI_VENDOR_ID_NI,
2301 .device = PCI_DEVICE_ID_NI_PXI8431_4854,
2302 .subvendor = PCI_ANY_ID,
2303 .subdevice = PCI_ANY_ID,
2304 .init = pci_ni8430_init,
2305 .setup = pci_ni8431_setup,
2306 .exit = pci_ni8430_exit,
2307 },
2308 {
2309 .vendor = PCI_VENDOR_ID_NI,
2310 .device = PCI_DEVICE_ID_NI_PXI8431_4858,
2311 .subvendor = PCI_ANY_ID,
2312 .subdevice = PCI_ANY_ID,
2313 .init = pci_ni8430_init,
2314 .setup = pci_ni8431_setup,
2315 .exit = pci_ni8430_exit,
2316 },
2317 {
2318 .vendor = PCI_VENDOR_ID_NI,
2319 .device = PCI_DEVICE_ID_NI_PXI8433_4852,
2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
2322 .init = pci_ni8430_init,
2323 .setup = pci_ni8431_setup,
2324 .exit = pci_ni8430_exit,
2325 },
2326 {
2327 .vendor = PCI_VENDOR_ID_NI,
2328 .device = PCI_DEVICE_ID_NI_PXI8433_4854,
2329 .subvendor = PCI_ANY_ID,
2330 .subdevice = PCI_ANY_ID,
2331 .init = pci_ni8430_init,
2332 .setup = pci_ni8431_setup,
2333 .exit = pci_ni8430_exit,
2334 },
2335 {
2336 .vendor = PCI_VENDOR_ID_NI,
2337 .device = PCIE_DEVICE_ID_NI_PXIE8431_4858,
2338 .subvendor = PCI_ANY_ID,
2339 .subdevice = PCI_ANY_ID,
2340 .init = pci_ni8430_init,
2341 .setup = pci_ni8431_setup,
2342 .exit = pci_ni8430_exit,
2343 },
2344 {
2345 .vendor = PCI_VENDOR_ID_NI,
2346 .device = PCIE_DEVICE_ID_NI_PXIE8431_48516,
2347 .subvendor = PCI_ANY_ID,
2348 .subdevice = PCI_ANY_ID,
2349 .init = pci_ni8430_init,
2350 .setup = pci_ni8431_setup,
2351 .exit = pci_ni8430_exit,
2352 },
2353 /* Quatech */
2354 {
2355 .vendor = PCI_VENDOR_ID_QUATECH,
2356 .device = PCI_ANY_ID,
2357 .subvendor = PCI_ANY_ID,
2358 .subdevice = PCI_ANY_ID,
2359 .init = pci_quatech_init,
2360 .setup = pci_quatech_setup,
2361 .exit = pci_quatech_exit,
2362 },
2363 /*
2364 * Panacom
2365 */
2366 {
2367 .vendor = PCI_VENDOR_ID_PANACOM,
2368 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2369 .subvendor = PCI_ANY_ID,
2370 .subdevice = PCI_ANY_ID,
2371 .init = pci_plx9050_init,
2372 .setup = pci_default_setup,
2373 .exit = pci_plx9050_exit,
2374 },
2375 {
2376 .vendor = PCI_VENDOR_ID_PANACOM,
2377 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2378 .subvendor = PCI_ANY_ID,
2379 .subdevice = PCI_ANY_ID,
2380 .init = pci_plx9050_init,
2381 .setup = pci_default_setup,
2382 .exit = pci_plx9050_exit,
2383 },
2384 /*
2385 * Pericom (Only 7954 - It have a offset jump for port 4)
2386 */
2387 {
2388 .vendor = PCI_VENDOR_ID_PERICOM,
2389 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2390 .subvendor = PCI_ANY_ID,
2391 .subdevice = PCI_ANY_ID,
2392 .setup = pci_pericom_setup_four_at_eight,
2393 },
2394 /*
2395 * PLX
2396 */
2397 {
2398 .vendor = PCI_VENDOR_ID_PLX,
2399 .device = PCI_DEVICE_ID_PLX_9050,
2400 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2401 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2402 .init = pci_plx9050_init,
2403 .setup = pci_default_setup,
2404 .exit = pci_plx9050_exit,
2405 },
2406 {
2407 .vendor = PCI_VENDOR_ID_PLX,
2408 .device = PCI_DEVICE_ID_PLX_9050,
2409 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2410 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2411 .init = pci_plx9050_init,
2412 .setup = pci_default_setup,
2413 .exit = pci_plx9050_exit,
2414 },
2415 {
2416 .vendor = PCI_VENDOR_ID_PLX,
2417 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2418 .subvendor = PCI_VENDOR_ID_PLX,
2419 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2420 .init = pci_plx9050_init,
2421 .setup = pci_default_setup,
2422 .exit = pci_plx9050_exit,
2423 },
2424 {
2425 .vendor = PCI_VENDOR_ID_ACCESIO,
2426 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2427 .subvendor = PCI_ANY_ID,
2428 .subdevice = PCI_ANY_ID,
2429 .setup = pci_pericom_setup_four_at_eight,
2430 },
2431 {
2432 .vendor = PCI_VENDOR_ID_ACCESIO,
2433 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2434 .subvendor = PCI_ANY_ID,
2435 .subdevice = PCI_ANY_ID,
2436 .setup = pci_pericom_setup_four_at_eight,
2437 },
2438 {
2439 .vendor = PCI_VENDOR_ID_ACCESIO,
2440 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2441 .subvendor = PCI_ANY_ID,
2442 .subdevice = PCI_ANY_ID,
2443 .setup = pci_pericom_setup_four_at_eight,
2444 },
2445 {
2446 .vendor = PCI_VENDOR_ID_ACCESIO,
2447 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2448 .subvendor = PCI_ANY_ID,
2449 .subdevice = PCI_ANY_ID,
2450 .setup = pci_pericom_setup_four_at_eight,
2451 },
2452 {
2453 .vendor = PCI_VENDOR_ID_ACCESIO,
2454 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2455 .subvendor = PCI_ANY_ID,
2456 .subdevice = PCI_ANY_ID,
2457 .setup = pci_pericom_setup_four_at_eight,
2458 },
2459 {
2460 .vendor = PCI_VENDOR_ID_ACCESIO,
2461 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2462 .subvendor = PCI_ANY_ID,
2463 .subdevice = PCI_ANY_ID,
2464 .setup = pci_pericom_setup_four_at_eight,
2465 },
2466 {
2467 .vendor = PCI_VENDOR_ID_ACCESIO,
2468 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2469 .subvendor = PCI_ANY_ID,
2470 .subdevice = PCI_ANY_ID,
2471 .setup = pci_pericom_setup_four_at_eight,
2472 },
2473 {
2474 .vendor = PCI_VENDOR_ID_ACCESIO,
2475 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2476 .subvendor = PCI_ANY_ID,
2477 .subdevice = PCI_ANY_ID,
2478 .setup = pci_pericom_setup_four_at_eight,
2479 },
2480 {
2481 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2482 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2483 .subvendor = PCI_ANY_ID,
2484 .subdevice = PCI_ANY_ID,
2485 .setup = pci_pericom_setup_four_at_eight,
2486 },
2487 {
2488 .vendor = PCI_VENDOR_ID_ACCESIO,
2489 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2490 .subvendor = PCI_ANY_ID,
2491 .subdevice = PCI_ANY_ID,
2492 .setup = pci_pericom_setup_four_at_eight,
2493 },
2494 {
2495 .vendor = PCI_VENDOR_ID_ACCESIO,
2496 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2497 .subvendor = PCI_ANY_ID,
2498 .subdevice = PCI_ANY_ID,
2499 .setup = pci_pericom_setup_four_at_eight,
2500 },
2501 {
2502 .vendor = PCI_VENDOR_ID_ACCESIO,
2503 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2504 .subvendor = PCI_ANY_ID,
2505 .subdevice = PCI_ANY_ID,
2506 .setup = pci_pericom_setup_four_at_eight,
2507 },
2508 {
2509 .vendor = PCI_VENDOR_ID_ACCESIO,
2510 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2511 .subvendor = PCI_ANY_ID,
2512 .subdevice = PCI_ANY_ID,
2513 .setup = pci_pericom_setup_four_at_eight,
2514 },
2515 {
2516 .vendor = PCI_VENDOR_ID_ACCESIO,
2517 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2518 .subvendor = PCI_ANY_ID,
2519 .subdevice = PCI_ANY_ID,
2520 .setup = pci_pericom_setup_four_at_eight,
2521 },
2522 {
2523 .vendor = PCI_VENDOR_ID_ACCESIO,
2524 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2525 .subvendor = PCI_ANY_ID,
2526 .subdevice = PCI_ANY_ID,
2527 .setup = pci_pericom_setup_four_at_eight,
2528 },
2529 {
2530 .vendor = PCI_VENDOR_ID_ACCESIO,
2531 .device = PCI_ANY_ID,
2532 .subvendor = PCI_ANY_ID,
2533 .subdevice = PCI_ANY_ID,
2534 .setup = pci_pericom_setup,
2535 }, /*
2536 * SBS Technologies, Inc., PMC-OCTALPRO 232
2537 */
2538 {
2539 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2540 .device = PCI_DEVICE_ID_OCTPRO,
2541 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2542 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2543 .init = sbs_init,
2544 .setup = sbs_setup,
2545 .exit = sbs_exit,
2546 },
2547 /*
2548 * SBS Technologies, Inc., PMC-OCTALPRO 422
2549 */
2550 {
2551 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2552 .device = PCI_DEVICE_ID_OCTPRO,
2553 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2554 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2555 .init = sbs_init,
2556 .setup = sbs_setup,
2557 .exit = sbs_exit,
2558 },
2559 /*
2560 * SBS Technologies, Inc., P-Octal 232
2561 */
2562 {
2563 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2564 .device = PCI_DEVICE_ID_OCTPRO,
2565 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2566 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2567 .init = sbs_init,
2568 .setup = sbs_setup,
2569 .exit = sbs_exit,
2570 },
2571 /*
2572 * SBS Technologies, Inc., P-Octal 422
2573 */
2574 {
2575 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2576 .device = PCI_DEVICE_ID_OCTPRO,
2577 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2578 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2579 .init = sbs_init,
2580 .setup = sbs_setup,
2581 .exit = sbs_exit,
2582 },
2583 /*
2584 * SIIG cards - these may be called via parport_serial
2585 */
2586 {
2587 .vendor = PCI_VENDOR_ID_SIIG,
2588 .device = PCI_ANY_ID,
2589 .subvendor = PCI_ANY_ID,
2590 .subdevice = PCI_ANY_ID,
2591 .init = pci_siig_init,
2592 .setup = pci_siig_setup,
2593 },
2594 /*
2595 * Titan cards
2596 */
2597 {
2598 .vendor = PCI_VENDOR_ID_TITAN,
2599 .device = PCI_DEVICE_ID_TITAN_400L,
2600 .subvendor = PCI_ANY_ID,
2601 .subdevice = PCI_ANY_ID,
2602 .setup = titan_400l_800l_setup,
2603 },
2604 {
2605 .vendor = PCI_VENDOR_ID_TITAN,
2606 .device = PCI_DEVICE_ID_TITAN_800L,
2607 .subvendor = PCI_ANY_ID,
2608 .subdevice = PCI_ANY_ID,
2609 .setup = titan_400l_800l_setup,
2610 },
2611 /*
2612 * Timedia cards
2613 */
2614 {
2615 .vendor = PCI_VENDOR_ID_TIMEDIA,
2616 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2617 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2618 .subdevice = PCI_ANY_ID,
2619 .probe = pci_timedia_probe,
2620 .init = pci_timedia_init,
2621 .setup = pci_timedia_setup,
2622 },
2623 {
2624 .vendor = PCI_VENDOR_ID_TIMEDIA,
2625 .device = PCI_ANY_ID,
2626 .subvendor = PCI_ANY_ID,
2627 .subdevice = PCI_ANY_ID,
2628 .setup = pci_timedia_setup,
2629 },
2630 /*
2631 * Sunix PCI serial boards
2632 */
2633 {
2634 .vendor = PCI_VENDOR_ID_SUNIX,
2635 .device = PCI_DEVICE_ID_SUNIX_1999,
2636 .subvendor = PCI_VENDOR_ID_SUNIX,
2637 .subdevice = PCI_ANY_ID,
2638 .setup = pci_sunix_setup,
2639 },
2640 /*
2641 * Xircom cards
2642 */
2643 {
2644 .vendor = PCI_VENDOR_ID_XIRCOM,
2645 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2646 .subvendor = PCI_ANY_ID,
2647 .subdevice = PCI_ANY_ID,
2648 .init = pci_xircom_init,
2649 .setup = pci_default_setup,
2650 },
2651 /*
2652 * Netmos cards - these may be called via parport_serial
2653 */
2654 {
2655 .vendor = PCI_VENDOR_ID_NETMOS,
2656 .device = PCI_ANY_ID,
2657 .subvendor = PCI_ANY_ID,
2658 .subdevice = PCI_ANY_ID,
2659 .init = pci_netmos_init,
2660 .setup = pci_netmos_9900_setup,
2661 },
2662 /*
2663 * EndRun Technologies
2664 */
2665 {
2666 .vendor = PCI_VENDOR_ID_ENDRUN,
2667 .device = PCI_ANY_ID,
2668 .subvendor = PCI_ANY_ID,
2669 .subdevice = PCI_ANY_ID,
2670 .init = pci_endrun_init,
2671 .setup = pci_default_setup,
2672 },
2673 /*
2674 * For Oxford Semiconductor Tornado based devices
2675 */
2676 {
2677 .vendor = PCI_VENDOR_ID_OXSEMI,
2678 .device = PCI_ANY_ID,
2679 .subvendor = PCI_ANY_ID,
2680 .subdevice = PCI_ANY_ID,
2681 .init = pci_oxsemi_tornado_init,
2682 .setup = pci_default_setup,
2683 },
2684 {
2685 .vendor = PCI_VENDOR_ID_MAINPINE,
2686 .device = PCI_ANY_ID,
2687 .subvendor = PCI_ANY_ID,
2688 .subdevice = PCI_ANY_ID,
2689 .init = pci_oxsemi_tornado_init,
2690 .setup = pci_default_setup,
2691 },
2692 {
2693 .vendor = PCI_VENDOR_ID_DIGI,
2694 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2695 .subvendor = PCI_SUBVENDOR_ID_IBM,
2696 .subdevice = PCI_ANY_ID,
2697 .init = pci_oxsemi_tornado_init,
2698 .setup = pci_default_setup,
2699 },
2700 {
2701 .vendor = PCI_VENDOR_ID_INTEL,
2702 .device = 0x8811,
2703 .subvendor = PCI_ANY_ID,
2704 .subdevice = PCI_ANY_ID,
2705 .init = pci_eg20t_init,
2706 .setup = pci_default_setup,
2707 },
2708 {
2709 .vendor = PCI_VENDOR_ID_INTEL,
2710 .device = 0x8812,
2711 .subvendor = PCI_ANY_ID,
2712 .subdevice = PCI_ANY_ID,
2713 .init = pci_eg20t_init,
2714 .setup = pci_default_setup,
2715 },
2716 {
2717 .vendor = PCI_VENDOR_ID_INTEL,
2718 .device = 0x8813,
2719 .subvendor = PCI_ANY_ID,
2720 .subdevice = PCI_ANY_ID,
2721 .init = pci_eg20t_init,
2722 .setup = pci_default_setup,
2723 },
2724 {
2725 .vendor = PCI_VENDOR_ID_INTEL,
2726 .device = 0x8814,
2727 .subvendor = PCI_ANY_ID,
2728 .subdevice = PCI_ANY_ID,
2729 .init = pci_eg20t_init,
2730 .setup = pci_default_setup,
2731 },
2732 {
2733 .vendor = 0x10DB,
2734 .device = 0x8027,
2735 .subvendor = PCI_ANY_ID,
2736 .subdevice = PCI_ANY_ID,
2737 .init = pci_eg20t_init,
2738 .setup = pci_default_setup,
2739 },
2740 {
2741 .vendor = 0x10DB,
2742 .device = 0x8028,
2743 .subvendor = PCI_ANY_ID,
2744 .subdevice = PCI_ANY_ID,
2745 .init = pci_eg20t_init,
2746 .setup = pci_default_setup,
2747 },
2748 {
2749 .vendor = 0x10DB,
2750 .device = 0x8029,
2751 .subvendor = PCI_ANY_ID,
2752 .subdevice = PCI_ANY_ID,
2753 .init = pci_eg20t_init,
2754 .setup = pci_default_setup,
2755 },
2756 {
2757 .vendor = 0x10DB,
2758 .device = 0x800C,
2759 .subvendor = PCI_ANY_ID,
2760 .subdevice = PCI_ANY_ID,
2761 .init = pci_eg20t_init,
2762 .setup = pci_default_setup,
2763 },
2764 {
2765 .vendor = 0x10DB,
2766 .device = 0x800D,
2767 .subvendor = PCI_ANY_ID,
2768 .subdevice = PCI_ANY_ID,
2769 .init = pci_eg20t_init,
2770 .setup = pci_default_setup,
2771 },
2772 /*
2773 * Cronyx Omega PCI (PLX-chip based)
2774 */
2775 {
2776 .vendor = PCI_VENDOR_ID_PLX,
2777 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2778 .subvendor = PCI_ANY_ID,
2779 .subdevice = PCI_ANY_ID,
2780 .setup = pci_omegapci_setup,
2781 },
2782 /* WCH CH353 1S1P card (16550 clone) */
2783 {
2784 .vendor = PCI_VENDOR_ID_WCH,
2785 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2786 .subvendor = PCI_ANY_ID,
2787 .subdevice = PCI_ANY_ID,
2788 .setup = pci_wch_ch353_setup,
2789 },
2790 /* WCH CH353 2S1P card (16550 clone) */
2791 {
2792 .vendor = PCI_VENDOR_ID_WCH,
2793 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2794 .subvendor = PCI_ANY_ID,
2795 .subdevice = PCI_ANY_ID,
2796 .setup = pci_wch_ch353_setup,
2797 },
2798 /* WCH CH353 4S card (16550 clone) */
2799 {
2800 .vendor = PCI_VENDOR_ID_WCH,
2801 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2802 .subvendor = PCI_ANY_ID,
2803 .subdevice = PCI_ANY_ID,
2804 .setup = pci_wch_ch353_setup,
2805 },
2806 /* WCH CH353 2S1PF card (16550 clone) */
2807 {
2808 .vendor = PCI_VENDOR_ID_WCH,
2809 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2810 .subvendor = PCI_ANY_ID,
2811 .subdevice = PCI_ANY_ID,
2812 .setup = pci_wch_ch353_setup,
2813 },
2814 /* WCH CH352 2S card (16550 clone) */
2815 {
2816 .vendor = PCI_VENDOR_ID_WCH,
2817 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2818 .subvendor = PCI_ANY_ID,
2819 .subdevice = PCI_ANY_ID,
2820 .setup = pci_wch_ch353_setup,
2821 },
2822 /* WCH CH355 4S card (16550 clone) */
2823 {
2824 .vendor = PCI_VENDOR_ID_WCH,
2825 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2826 .subvendor = PCI_ANY_ID,
2827 .subdevice = PCI_ANY_ID,
2828 .setup = pci_wch_ch355_setup,
2829 },
2830 /* WCH CH382 2S card (16850 clone) */
2831 {
2832 .vendor = PCIE_VENDOR_ID_WCH,
2833 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2834 .subvendor = PCI_ANY_ID,
2835 .subdevice = PCI_ANY_ID,
2836 .setup = pci_wch_ch38x_setup,
2837 },
2838 /* WCH CH382 2S1P card (16850 clone) */
2839 {
2840 .vendor = PCIE_VENDOR_ID_WCH,
2841 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2842 .subvendor = PCI_ANY_ID,
2843 .subdevice = PCI_ANY_ID,
2844 .setup = pci_wch_ch38x_setup,
2845 },
2846 /* WCH CH384 4S card (16850 clone) */
2847 {
2848 .vendor = PCIE_VENDOR_ID_WCH,
2849 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2850 .subvendor = PCI_ANY_ID,
2851 .subdevice = PCI_ANY_ID,
2852 .setup = pci_wch_ch38x_setup,
2853 },
2854 /*
2855 * ASIX devices with FIFO bug
2856 */
2857 {
2858 .vendor = PCI_VENDOR_ID_ASIX,
2859 .device = PCI_ANY_ID,
2860 .subvendor = PCI_ANY_ID,
2861 .subdevice = PCI_ANY_ID,
2862 .setup = pci_asix_setup,
2863 },
2864 /*
2865 * Broadcom TruManage (NetXtreme)
2866 */
2867 {
2868 .vendor = PCI_VENDOR_ID_BROADCOM,
2869 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2870 .subvendor = PCI_ANY_ID,
2871 .subdevice = PCI_ANY_ID,
2872 .setup = pci_brcm_trumanage_setup,
2873 },
2874 {
2875 .vendor = 0x1c29,
2876 .device = 0x1104,
2877 .subvendor = PCI_ANY_ID,
2878 .subdevice = PCI_ANY_ID,
2879 .setup = pci_fintek_setup,
2880 .init = pci_fintek_init,
2881 },
2882 {
2883 .vendor = 0x1c29,
2884 .device = 0x1108,
2885 .subvendor = PCI_ANY_ID,
2886 .subdevice = PCI_ANY_ID,
2887 .setup = pci_fintek_setup,
2888 .init = pci_fintek_init,
2889 },
2890 {
2891 .vendor = 0x1c29,
2892 .device = 0x1112,
2893 .subvendor = PCI_ANY_ID,
2894 .subdevice = PCI_ANY_ID,
2895 .setup = pci_fintek_setup,
2896 .init = pci_fintek_init,
2897 },
2898 /*
2899 * MOXA
2900 */
2901 {
2902 .vendor = PCI_VENDOR_ID_MOXA,
2903 .device = PCI_ANY_ID,
2904 .subvendor = PCI_ANY_ID,
2905 .subdevice = PCI_ANY_ID,
2906 .setup = pci_moxa_setup,
2907 },
2908 {
2909 .vendor = 0x1c29,
2910 .device = 0x1204,
2911 .subvendor = PCI_ANY_ID,
2912 .subdevice = PCI_ANY_ID,
2913 .setup = pci_fintek_f815xxa_setup,
2914 .init = pci_fintek_f815xxa_init,
2915 },
2916 {
2917 .vendor = 0x1c29,
2918 .device = 0x1208,
2919 .subvendor = PCI_ANY_ID,
2920 .subdevice = PCI_ANY_ID,
2921 .setup = pci_fintek_f815xxa_setup,
2922 .init = pci_fintek_f815xxa_init,
2923 },
2924 {
2925 .vendor = 0x1c29,
2926 .device = 0x1212,
2927 .subvendor = PCI_ANY_ID,
2928 .subdevice = PCI_ANY_ID,
2929 .setup = pci_fintek_f815xxa_setup,
2930 .init = pci_fintek_f815xxa_init,
2931 },
2932
2933 /*
2934 * Default "match everything" terminator entry
2935 */
2936 {
2937 .vendor = PCI_ANY_ID,
2938 .device = PCI_ANY_ID,
2939 .subvendor = PCI_ANY_ID,
2940 .subdevice = PCI_ANY_ID,
2941 .setup = pci_default_setup,
2942 }
2943 };
2944
quirk_id_matches(u32 quirk_id,u32 dev_id)2945 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2946 {
2947 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2948 }
2949
find_quirk(struct pci_dev * dev)2950 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2951 {
2952 struct pci_serial_quirk *quirk;
2953
2954 for (quirk = pci_serial_quirks; ; quirk++)
2955 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2956 quirk_id_matches(quirk->device, dev->device) &&
2957 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2958 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2959 break;
2960 return quirk;
2961 }
2962
get_pci_irq(struct pci_dev * dev,const struct pciserial_board * board)2963 static inline int get_pci_irq(struct pci_dev *dev,
2964 const struct pciserial_board *board)
2965 {
2966 if (board->flags & FL_NOIRQ)
2967 return 0;
2968 else
2969 return dev->irq;
2970 }
2971
2972 /*
2973 * This is the configuration table for all of the PCI serial boards
2974 * which we support. It is directly indexed by the pci_board_num_t enum
2975 * value, which is encoded in the pci_device_id PCI probe table's
2976 * driver_data member.
2977 *
2978 * The makeup of these names are:
2979 * pbn_bn{_bt}_n_baud{_offsetinhex}
2980 *
2981 * bn = PCI BAR number
2982 * bt = Index using PCI BARs
2983 * n = number of serial ports
2984 * baud = baud rate
2985 * offsetinhex = offset for each sequential port (in hex)
2986 *
2987 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2988 *
2989 * Please note: in theory if n = 1, _bt infix should make no difference.
2990 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2991 */
2992 enum pci_board_num_t {
2993 pbn_default = 0,
2994
2995 pbn_b0_1_115200,
2996 pbn_b0_2_115200,
2997 pbn_b0_4_115200,
2998 pbn_b0_5_115200,
2999 pbn_b0_8_115200,
3000
3001 pbn_b0_1_921600,
3002 pbn_b0_2_921600,
3003 pbn_b0_4_921600,
3004
3005 pbn_b0_2_1130000,
3006
3007 pbn_b0_4_1152000,
3008
3009 pbn_b0_4_1250000,
3010
3011 pbn_b0_2_1843200,
3012 pbn_b0_4_1843200,
3013
3014 pbn_b0_1_4000000,
3015
3016 pbn_b0_bt_1_115200,
3017 pbn_b0_bt_2_115200,
3018 pbn_b0_bt_4_115200,
3019 pbn_b0_bt_8_115200,
3020
3021 pbn_b0_bt_1_460800,
3022 pbn_b0_bt_2_460800,
3023 pbn_b0_bt_4_460800,
3024
3025 pbn_b0_bt_1_921600,
3026 pbn_b0_bt_2_921600,
3027 pbn_b0_bt_4_921600,
3028 pbn_b0_bt_8_921600,
3029
3030 pbn_b1_1_115200,
3031 pbn_b1_2_115200,
3032 pbn_b1_4_115200,
3033 pbn_b1_8_115200,
3034 pbn_b1_16_115200,
3035
3036 pbn_b1_1_921600,
3037 pbn_b1_2_921600,
3038 pbn_b1_4_921600,
3039 pbn_b1_8_921600,
3040
3041 pbn_b1_2_1250000,
3042
3043 pbn_b1_bt_1_115200,
3044 pbn_b1_bt_2_115200,
3045 pbn_b1_bt_4_115200,
3046
3047 pbn_b1_bt_2_921600,
3048
3049 pbn_b1_1_1382400,
3050 pbn_b1_2_1382400,
3051 pbn_b1_4_1382400,
3052 pbn_b1_8_1382400,
3053
3054 pbn_b2_1_115200,
3055 pbn_b2_2_115200,
3056 pbn_b2_4_115200,
3057 pbn_b2_8_115200,
3058
3059 pbn_b2_1_460800,
3060 pbn_b2_4_460800,
3061 pbn_b2_8_460800,
3062 pbn_b2_16_460800,
3063
3064 pbn_b2_1_921600,
3065 pbn_b2_4_921600,
3066 pbn_b2_8_921600,
3067
3068 pbn_b2_8_1152000,
3069
3070 pbn_b2_bt_1_115200,
3071 pbn_b2_bt_2_115200,
3072 pbn_b2_bt_4_115200,
3073
3074 pbn_b2_bt_2_921600,
3075 pbn_b2_bt_4_921600,
3076
3077 pbn_b3_2_115200,
3078 pbn_b3_4_115200,
3079 pbn_b3_8_115200,
3080
3081 pbn_b4_bt_2_921600,
3082 pbn_b4_bt_4_921600,
3083 pbn_b4_bt_8_921600,
3084
3085 /*
3086 * Board-specific versions.
3087 */
3088 pbn_panacom,
3089 pbn_panacom2,
3090 pbn_panacom4,
3091 pbn_plx_romulus,
3092 pbn_endrun_2_4000000,
3093 pbn_oxsemi,
3094 pbn_oxsemi_1_4000000,
3095 pbn_oxsemi_2_4000000,
3096 pbn_oxsemi_4_4000000,
3097 pbn_oxsemi_8_4000000,
3098 pbn_intel_i960,
3099 pbn_sgi_ioc3,
3100 pbn_computone_4,
3101 pbn_computone_6,
3102 pbn_computone_8,
3103 pbn_sbsxrsio,
3104 pbn_pasemi_1682M,
3105 pbn_ni8430_2,
3106 pbn_ni8430_4,
3107 pbn_ni8430_8,
3108 pbn_ni8430_16,
3109 pbn_ni8430_pxie_8,
3110 pbn_ni8430_pxie_16,
3111 pbn_ni8431_2,
3112 pbn_ni8431_4,
3113 pbn_ni8431_8,
3114 pbn_ni8431_pxie_8,
3115 pbn_ni8431_pxie_16,
3116 pbn_ADDIDATA_PCIe_1_3906250,
3117 pbn_ADDIDATA_PCIe_2_3906250,
3118 pbn_ADDIDATA_PCIe_4_3906250,
3119 pbn_ADDIDATA_PCIe_8_3906250,
3120 pbn_ce4100_1_115200,
3121 pbn_omegapci,
3122 pbn_NETMOS9900_2s_115200,
3123 pbn_brcm_trumanage,
3124 pbn_fintek_4,
3125 pbn_fintek_8,
3126 pbn_fintek_12,
3127 pbn_fintek_F81504A,
3128 pbn_fintek_F81508A,
3129 pbn_fintek_F81512A,
3130 pbn_wch382_2,
3131 pbn_wch384_4,
3132 pbn_pericom_PI7C9X7951,
3133 pbn_pericom_PI7C9X7952,
3134 pbn_pericom_PI7C9X7954,
3135 pbn_pericom_PI7C9X7958,
3136 pbn_sunix_pci_1s,
3137 pbn_sunix_pci_2s,
3138 pbn_sunix_pci_4s,
3139 pbn_sunix_pci_8s,
3140 pbn_sunix_pci_16s,
3141 pbn_moxa8250_2p,
3142 pbn_moxa8250_4p,
3143 pbn_moxa8250_8p,
3144 };
3145
3146 /*
3147 * uart_offset - the space between channels
3148 * reg_shift - describes how the UART registers are mapped
3149 * to PCI memory by the card.
3150 * For example IER register on SBS, Inc. PMC-OctPro is located at
3151 * offset 0x10 from the UART base, while UART_IER is defined as 1
3152 * in include/linux/serial_reg.h,
3153 * see first lines of serial_in() and serial_out() in 8250.c
3154 */
3155
3156 static struct pciserial_board pci_boards[] = {
3157 [pbn_default] = {
3158 .flags = FL_BASE0,
3159 .num_ports = 1,
3160 .base_baud = 115200,
3161 .uart_offset = 8,
3162 },
3163 [pbn_b0_1_115200] = {
3164 .flags = FL_BASE0,
3165 .num_ports = 1,
3166 .base_baud = 115200,
3167 .uart_offset = 8,
3168 },
3169 [pbn_b0_2_115200] = {
3170 .flags = FL_BASE0,
3171 .num_ports = 2,
3172 .base_baud = 115200,
3173 .uart_offset = 8,
3174 },
3175 [pbn_b0_4_115200] = {
3176 .flags = FL_BASE0,
3177 .num_ports = 4,
3178 .base_baud = 115200,
3179 .uart_offset = 8,
3180 },
3181 [pbn_b0_5_115200] = {
3182 .flags = FL_BASE0,
3183 .num_ports = 5,
3184 .base_baud = 115200,
3185 .uart_offset = 8,
3186 },
3187 [pbn_b0_8_115200] = {
3188 .flags = FL_BASE0,
3189 .num_ports = 8,
3190 .base_baud = 115200,
3191 .uart_offset = 8,
3192 },
3193 [pbn_b0_1_921600] = {
3194 .flags = FL_BASE0,
3195 .num_ports = 1,
3196 .base_baud = 921600,
3197 .uart_offset = 8,
3198 },
3199 [pbn_b0_2_921600] = {
3200 .flags = FL_BASE0,
3201 .num_ports = 2,
3202 .base_baud = 921600,
3203 .uart_offset = 8,
3204 },
3205 [pbn_b0_4_921600] = {
3206 .flags = FL_BASE0,
3207 .num_ports = 4,
3208 .base_baud = 921600,
3209 .uart_offset = 8,
3210 },
3211
3212 [pbn_b0_2_1130000] = {
3213 .flags = FL_BASE0,
3214 .num_ports = 2,
3215 .base_baud = 1130000,
3216 .uart_offset = 8,
3217 },
3218
3219 [pbn_b0_4_1152000] = {
3220 .flags = FL_BASE0,
3221 .num_ports = 4,
3222 .base_baud = 1152000,
3223 .uart_offset = 8,
3224 },
3225
3226 [pbn_b0_4_1250000] = {
3227 .flags = FL_BASE0,
3228 .num_ports = 4,
3229 .base_baud = 1250000,
3230 .uart_offset = 8,
3231 },
3232
3233 [pbn_b0_2_1843200] = {
3234 .flags = FL_BASE0,
3235 .num_ports = 2,
3236 .base_baud = 1843200,
3237 .uart_offset = 8,
3238 },
3239 [pbn_b0_4_1843200] = {
3240 .flags = FL_BASE0,
3241 .num_ports = 4,
3242 .base_baud = 1843200,
3243 .uart_offset = 8,
3244 },
3245
3246 [pbn_b0_1_4000000] = {
3247 .flags = FL_BASE0,
3248 .num_ports = 1,
3249 .base_baud = 4000000,
3250 .uart_offset = 8,
3251 },
3252
3253 [pbn_b0_bt_1_115200] = {
3254 .flags = FL_BASE0|FL_BASE_BARS,
3255 .num_ports = 1,
3256 .base_baud = 115200,
3257 .uart_offset = 8,
3258 },
3259 [pbn_b0_bt_2_115200] = {
3260 .flags = FL_BASE0|FL_BASE_BARS,
3261 .num_ports = 2,
3262 .base_baud = 115200,
3263 .uart_offset = 8,
3264 },
3265 [pbn_b0_bt_4_115200] = {
3266 .flags = FL_BASE0|FL_BASE_BARS,
3267 .num_ports = 4,
3268 .base_baud = 115200,
3269 .uart_offset = 8,
3270 },
3271 [pbn_b0_bt_8_115200] = {
3272 .flags = FL_BASE0|FL_BASE_BARS,
3273 .num_ports = 8,
3274 .base_baud = 115200,
3275 .uart_offset = 8,
3276 },
3277
3278 [pbn_b0_bt_1_460800] = {
3279 .flags = FL_BASE0|FL_BASE_BARS,
3280 .num_ports = 1,
3281 .base_baud = 460800,
3282 .uart_offset = 8,
3283 },
3284 [pbn_b0_bt_2_460800] = {
3285 .flags = FL_BASE0|FL_BASE_BARS,
3286 .num_ports = 2,
3287 .base_baud = 460800,
3288 .uart_offset = 8,
3289 },
3290 [pbn_b0_bt_4_460800] = {
3291 .flags = FL_BASE0|FL_BASE_BARS,
3292 .num_ports = 4,
3293 .base_baud = 460800,
3294 .uart_offset = 8,
3295 },
3296
3297 [pbn_b0_bt_1_921600] = {
3298 .flags = FL_BASE0|FL_BASE_BARS,
3299 .num_ports = 1,
3300 .base_baud = 921600,
3301 .uart_offset = 8,
3302 },
3303 [pbn_b0_bt_2_921600] = {
3304 .flags = FL_BASE0|FL_BASE_BARS,
3305 .num_ports = 2,
3306 .base_baud = 921600,
3307 .uart_offset = 8,
3308 },
3309 [pbn_b0_bt_4_921600] = {
3310 .flags = FL_BASE0|FL_BASE_BARS,
3311 .num_ports = 4,
3312 .base_baud = 921600,
3313 .uart_offset = 8,
3314 },
3315 [pbn_b0_bt_8_921600] = {
3316 .flags = FL_BASE0|FL_BASE_BARS,
3317 .num_ports = 8,
3318 .base_baud = 921600,
3319 .uart_offset = 8,
3320 },
3321
3322 [pbn_b1_1_115200] = {
3323 .flags = FL_BASE1,
3324 .num_ports = 1,
3325 .base_baud = 115200,
3326 .uart_offset = 8,
3327 },
3328 [pbn_b1_2_115200] = {
3329 .flags = FL_BASE1,
3330 .num_ports = 2,
3331 .base_baud = 115200,
3332 .uart_offset = 8,
3333 },
3334 [pbn_b1_4_115200] = {
3335 .flags = FL_BASE1,
3336 .num_ports = 4,
3337 .base_baud = 115200,
3338 .uart_offset = 8,
3339 },
3340 [pbn_b1_8_115200] = {
3341 .flags = FL_BASE1,
3342 .num_ports = 8,
3343 .base_baud = 115200,
3344 .uart_offset = 8,
3345 },
3346 [pbn_b1_16_115200] = {
3347 .flags = FL_BASE1,
3348 .num_ports = 16,
3349 .base_baud = 115200,
3350 .uart_offset = 8,
3351 },
3352
3353 [pbn_b1_1_921600] = {
3354 .flags = FL_BASE1,
3355 .num_ports = 1,
3356 .base_baud = 921600,
3357 .uart_offset = 8,
3358 },
3359 [pbn_b1_2_921600] = {
3360 .flags = FL_BASE1,
3361 .num_ports = 2,
3362 .base_baud = 921600,
3363 .uart_offset = 8,
3364 },
3365 [pbn_b1_4_921600] = {
3366 .flags = FL_BASE1,
3367 .num_ports = 4,
3368 .base_baud = 921600,
3369 .uart_offset = 8,
3370 },
3371 [pbn_b1_8_921600] = {
3372 .flags = FL_BASE1,
3373 .num_ports = 8,
3374 .base_baud = 921600,
3375 .uart_offset = 8,
3376 },
3377 [pbn_b1_2_1250000] = {
3378 .flags = FL_BASE1,
3379 .num_ports = 2,
3380 .base_baud = 1250000,
3381 .uart_offset = 8,
3382 },
3383
3384 [pbn_b1_bt_1_115200] = {
3385 .flags = FL_BASE1|FL_BASE_BARS,
3386 .num_ports = 1,
3387 .base_baud = 115200,
3388 .uart_offset = 8,
3389 },
3390 [pbn_b1_bt_2_115200] = {
3391 .flags = FL_BASE1|FL_BASE_BARS,
3392 .num_ports = 2,
3393 .base_baud = 115200,
3394 .uart_offset = 8,
3395 },
3396 [pbn_b1_bt_4_115200] = {
3397 .flags = FL_BASE1|FL_BASE_BARS,
3398 .num_ports = 4,
3399 .base_baud = 115200,
3400 .uart_offset = 8,
3401 },
3402
3403 [pbn_b1_bt_2_921600] = {
3404 .flags = FL_BASE1|FL_BASE_BARS,
3405 .num_ports = 2,
3406 .base_baud = 921600,
3407 .uart_offset = 8,
3408 },
3409
3410 [pbn_b1_1_1382400] = {
3411 .flags = FL_BASE1,
3412 .num_ports = 1,
3413 .base_baud = 1382400,
3414 .uart_offset = 8,
3415 },
3416 [pbn_b1_2_1382400] = {
3417 .flags = FL_BASE1,
3418 .num_ports = 2,
3419 .base_baud = 1382400,
3420 .uart_offset = 8,
3421 },
3422 [pbn_b1_4_1382400] = {
3423 .flags = FL_BASE1,
3424 .num_ports = 4,
3425 .base_baud = 1382400,
3426 .uart_offset = 8,
3427 },
3428 [pbn_b1_8_1382400] = {
3429 .flags = FL_BASE1,
3430 .num_ports = 8,
3431 .base_baud = 1382400,
3432 .uart_offset = 8,
3433 },
3434
3435 [pbn_b2_1_115200] = {
3436 .flags = FL_BASE2,
3437 .num_ports = 1,
3438 .base_baud = 115200,
3439 .uart_offset = 8,
3440 },
3441 [pbn_b2_2_115200] = {
3442 .flags = FL_BASE2,
3443 .num_ports = 2,
3444 .base_baud = 115200,
3445 .uart_offset = 8,
3446 },
3447 [pbn_b2_4_115200] = {
3448 .flags = FL_BASE2,
3449 .num_ports = 4,
3450 .base_baud = 115200,
3451 .uart_offset = 8,
3452 },
3453 [pbn_b2_8_115200] = {
3454 .flags = FL_BASE2,
3455 .num_ports = 8,
3456 .base_baud = 115200,
3457 .uart_offset = 8,
3458 },
3459
3460 [pbn_b2_1_460800] = {
3461 .flags = FL_BASE2,
3462 .num_ports = 1,
3463 .base_baud = 460800,
3464 .uart_offset = 8,
3465 },
3466 [pbn_b2_4_460800] = {
3467 .flags = FL_BASE2,
3468 .num_ports = 4,
3469 .base_baud = 460800,
3470 .uart_offset = 8,
3471 },
3472 [pbn_b2_8_460800] = {
3473 .flags = FL_BASE2,
3474 .num_ports = 8,
3475 .base_baud = 460800,
3476 .uart_offset = 8,
3477 },
3478 [pbn_b2_16_460800] = {
3479 .flags = FL_BASE2,
3480 .num_ports = 16,
3481 .base_baud = 460800,
3482 .uart_offset = 8,
3483 },
3484
3485 [pbn_b2_1_921600] = {
3486 .flags = FL_BASE2,
3487 .num_ports = 1,
3488 .base_baud = 921600,
3489 .uart_offset = 8,
3490 },
3491 [pbn_b2_4_921600] = {
3492 .flags = FL_BASE2,
3493 .num_ports = 4,
3494 .base_baud = 921600,
3495 .uart_offset = 8,
3496 },
3497 [pbn_b2_8_921600] = {
3498 .flags = FL_BASE2,
3499 .num_ports = 8,
3500 .base_baud = 921600,
3501 .uart_offset = 8,
3502 },
3503
3504 [pbn_b2_8_1152000] = {
3505 .flags = FL_BASE2,
3506 .num_ports = 8,
3507 .base_baud = 1152000,
3508 .uart_offset = 8,
3509 },
3510
3511 [pbn_b2_bt_1_115200] = {
3512 .flags = FL_BASE2|FL_BASE_BARS,
3513 .num_ports = 1,
3514 .base_baud = 115200,
3515 .uart_offset = 8,
3516 },
3517 [pbn_b2_bt_2_115200] = {
3518 .flags = FL_BASE2|FL_BASE_BARS,
3519 .num_ports = 2,
3520 .base_baud = 115200,
3521 .uart_offset = 8,
3522 },
3523 [pbn_b2_bt_4_115200] = {
3524 .flags = FL_BASE2|FL_BASE_BARS,
3525 .num_ports = 4,
3526 .base_baud = 115200,
3527 .uart_offset = 8,
3528 },
3529
3530 [pbn_b2_bt_2_921600] = {
3531 .flags = FL_BASE2|FL_BASE_BARS,
3532 .num_ports = 2,
3533 .base_baud = 921600,
3534 .uart_offset = 8,
3535 },
3536 [pbn_b2_bt_4_921600] = {
3537 .flags = FL_BASE2|FL_BASE_BARS,
3538 .num_ports = 4,
3539 .base_baud = 921600,
3540 .uart_offset = 8,
3541 },
3542
3543 [pbn_b3_2_115200] = {
3544 .flags = FL_BASE3,
3545 .num_ports = 2,
3546 .base_baud = 115200,
3547 .uart_offset = 8,
3548 },
3549 [pbn_b3_4_115200] = {
3550 .flags = FL_BASE3,
3551 .num_ports = 4,
3552 .base_baud = 115200,
3553 .uart_offset = 8,
3554 },
3555 [pbn_b3_8_115200] = {
3556 .flags = FL_BASE3,
3557 .num_ports = 8,
3558 .base_baud = 115200,
3559 .uart_offset = 8,
3560 },
3561
3562 [pbn_b4_bt_2_921600] = {
3563 .flags = FL_BASE4,
3564 .num_ports = 2,
3565 .base_baud = 921600,
3566 .uart_offset = 8,
3567 },
3568 [pbn_b4_bt_4_921600] = {
3569 .flags = FL_BASE4,
3570 .num_ports = 4,
3571 .base_baud = 921600,
3572 .uart_offset = 8,
3573 },
3574 [pbn_b4_bt_8_921600] = {
3575 .flags = FL_BASE4,
3576 .num_ports = 8,
3577 .base_baud = 921600,
3578 .uart_offset = 8,
3579 },
3580
3581 /*
3582 * Entries following this are board-specific.
3583 */
3584
3585 /*
3586 * Panacom - IOMEM
3587 */
3588 [pbn_panacom] = {
3589 .flags = FL_BASE2,
3590 .num_ports = 2,
3591 .base_baud = 921600,
3592 .uart_offset = 0x400,
3593 .reg_shift = 7,
3594 },
3595 [pbn_panacom2] = {
3596 .flags = FL_BASE2|FL_BASE_BARS,
3597 .num_ports = 2,
3598 .base_baud = 921600,
3599 .uart_offset = 0x400,
3600 .reg_shift = 7,
3601 },
3602 [pbn_panacom4] = {
3603 .flags = FL_BASE2|FL_BASE_BARS,
3604 .num_ports = 4,
3605 .base_baud = 921600,
3606 .uart_offset = 0x400,
3607 .reg_shift = 7,
3608 },
3609
3610 /* I think this entry is broken - the first_offset looks wrong --rmk */
3611 [pbn_plx_romulus] = {
3612 .flags = FL_BASE2,
3613 .num_ports = 4,
3614 .base_baud = 921600,
3615 .uart_offset = 8 << 2,
3616 .reg_shift = 2,
3617 .first_offset = 0x03,
3618 },
3619
3620 /*
3621 * EndRun Technologies
3622 * Uses the size of PCI Base region 0 to
3623 * signal now many ports are available
3624 * 2 port 952 Uart support
3625 */
3626 [pbn_endrun_2_4000000] = {
3627 .flags = FL_BASE0,
3628 .num_ports = 2,
3629 .base_baud = 4000000,
3630 .uart_offset = 0x200,
3631 .first_offset = 0x1000,
3632 },
3633
3634 /*
3635 * This board uses the size of PCI Base region 0 to
3636 * signal now many ports are available
3637 */
3638 [pbn_oxsemi] = {
3639 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3640 .num_ports = 32,
3641 .base_baud = 115200,
3642 .uart_offset = 8,
3643 },
3644 [pbn_oxsemi_1_4000000] = {
3645 .flags = FL_BASE0,
3646 .num_ports = 1,
3647 .base_baud = 4000000,
3648 .uart_offset = 0x200,
3649 .first_offset = 0x1000,
3650 },
3651 [pbn_oxsemi_2_4000000] = {
3652 .flags = FL_BASE0,
3653 .num_ports = 2,
3654 .base_baud = 4000000,
3655 .uart_offset = 0x200,
3656 .first_offset = 0x1000,
3657 },
3658 [pbn_oxsemi_4_4000000] = {
3659 .flags = FL_BASE0,
3660 .num_ports = 4,
3661 .base_baud = 4000000,
3662 .uart_offset = 0x200,
3663 .first_offset = 0x1000,
3664 },
3665 [pbn_oxsemi_8_4000000] = {
3666 .flags = FL_BASE0,
3667 .num_ports = 8,
3668 .base_baud = 4000000,
3669 .uart_offset = 0x200,
3670 .first_offset = 0x1000,
3671 },
3672
3673
3674 /*
3675 * EKF addition for i960 Boards form EKF with serial port.
3676 * Max 256 ports.
3677 */
3678 [pbn_intel_i960] = {
3679 .flags = FL_BASE0,
3680 .num_ports = 32,
3681 .base_baud = 921600,
3682 .uart_offset = 8 << 2,
3683 .reg_shift = 2,
3684 .first_offset = 0x10000,
3685 },
3686 [pbn_sgi_ioc3] = {
3687 .flags = FL_BASE0|FL_NOIRQ,
3688 .num_ports = 1,
3689 .base_baud = 458333,
3690 .uart_offset = 8,
3691 .reg_shift = 0,
3692 .first_offset = 0x20178,
3693 },
3694
3695 /*
3696 * Computone - uses IOMEM.
3697 */
3698 [pbn_computone_4] = {
3699 .flags = FL_BASE0,
3700 .num_ports = 4,
3701 .base_baud = 921600,
3702 .uart_offset = 0x40,
3703 .reg_shift = 2,
3704 .first_offset = 0x200,
3705 },
3706 [pbn_computone_6] = {
3707 .flags = FL_BASE0,
3708 .num_ports = 6,
3709 .base_baud = 921600,
3710 .uart_offset = 0x40,
3711 .reg_shift = 2,
3712 .first_offset = 0x200,
3713 },
3714 [pbn_computone_8] = {
3715 .flags = FL_BASE0,
3716 .num_ports = 8,
3717 .base_baud = 921600,
3718 .uart_offset = 0x40,
3719 .reg_shift = 2,
3720 .first_offset = 0x200,
3721 },
3722 [pbn_sbsxrsio] = {
3723 .flags = FL_BASE0,
3724 .num_ports = 8,
3725 .base_baud = 460800,
3726 .uart_offset = 256,
3727 .reg_shift = 4,
3728 },
3729 /*
3730 * PA Semi PWRficient PA6T-1682M on-chip UART
3731 */
3732 [pbn_pasemi_1682M] = {
3733 .flags = FL_BASE0,
3734 .num_ports = 1,
3735 .base_baud = 8333333,
3736 },
3737 /*
3738 * National Instruments 843x
3739 */
3740 [pbn_ni8430_16] = {
3741 .flags = FL_BASE0,
3742 .num_ports = 16,
3743 .base_baud = 3686400,
3744 .uart_offset = 0x10,
3745 .first_offset = 0x800,
3746 },
3747 [pbn_ni8430_8] = {
3748 .flags = FL_BASE0,
3749 .num_ports = 8,
3750 .base_baud = 3686400,
3751 .uart_offset = 0x10,
3752 .first_offset = 0x800,
3753 },
3754 [pbn_ni8430_4] = {
3755 .flags = FL_BASE0,
3756 .num_ports = 4,
3757 .base_baud = 3686400,
3758 .uart_offset = 0x10,
3759 .first_offset = 0x800,
3760 },
3761 [pbn_ni8430_2] = {
3762 .flags = FL_BASE0,
3763 .num_ports = 2,
3764 .base_baud = 3686400,
3765 .uart_offset = 0x10,
3766 .first_offset = 0x800,
3767 },
3768 [pbn_ni8430_pxie_16] = {
3769 .flags = FL_BASE0,
3770 .num_ports = 16,
3771 .base_baud = 3125000,
3772 .uart_offset = 0x10,
3773 .first_offset = 0x800,
3774 },
3775 [pbn_ni8430_pxie_8] = {
3776 .flags = FL_BASE0,
3777 .num_ports = 8,
3778 .base_baud = 3125000,
3779 .uart_offset = 0x10,
3780 .first_offset = 0x800,
3781 },
3782 [pbn_ni8431_8] = {
3783 .flags = FL_BASE0,
3784 .num_ports = 8,
3785 .base_baud = 3686400,
3786 .uart_offset = 0x10,
3787 .first_offset = 0x800,
3788 },
3789 [pbn_ni8431_4] = {
3790 .flags = FL_BASE0,
3791 .num_ports = 4,
3792 .base_baud = 3686400,
3793 .uart_offset = 0x10,
3794 .first_offset = 0x800,
3795 },
3796 [pbn_ni8431_2] = {
3797 .flags = FL_BASE0,
3798 .num_ports = 2,
3799 .base_baud = 3686400,
3800 .uart_offset = 0x10,
3801 .first_offset = 0x800,
3802 },
3803 [pbn_ni8431_pxie_16] = {
3804 .flags = FL_BASE0,
3805 .num_ports = 16,
3806 .base_baud = 3125000,
3807 .uart_offset = 0x10,
3808 .first_offset = 0x800,
3809 },
3810 [pbn_ni8431_pxie_8] = {
3811 .flags = FL_BASE0,
3812 .num_ports = 8,
3813 .base_baud = 3125000,
3814 .uart_offset = 0x10,
3815 .first_offset = 0x800,
3816 },
3817 /*
3818 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3819 */
3820 [pbn_ADDIDATA_PCIe_1_3906250] = {
3821 .flags = FL_BASE0,
3822 .num_ports = 1,
3823 .base_baud = 3906250,
3824 .uart_offset = 0x200,
3825 .first_offset = 0x1000,
3826 },
3827 [pbn_ADDIDATA_PCIe_2_3906250] = {
3828 .flags = FL_BASE0,
3829 .num_ports = 2,
3830 .base_baud = 3906250,
3831 .uart_offset = 0x200,
3832 .first_offset = 0x1000,
3833 },
3834 [pbn_ADDIDATA_PCIe_4_3906250] = {
3835 .flags = FL_BASE0,
3836 .num_ports = 4,
3837 .base_baud = 3906250,
3838 .uart_offset = 0x200,
3839 .first_offset = 0x1000,
3840 },
3841 [pbn_ADDIDATA_PCIe_8_3906250] = {
3842 .flags = FL_BASE0,
3843 .num_ports = 8,
3844 .base_baud = 3906250,
3845 .uart_offset = 0x200,
3846 .first_offset = 0x1000,
3847 },
3848 [pbn_ce4100_1_115200] = {
3849 .flags = FL_BASE_BARS,
3850 .num_ports = 2,
3851 .base_baud = 921600,
3852 .reg_shift = 2,
3853 },
3854 [pbn_omegapci] = {
3855 .flags = FL_BASE0,
3856 .num_ports = 8,
3857 .base_baud = 115200,
3858 .uart_offset = 0x200,
3859 },
3860 [pbn_NETMOS9900_2s_115200] = {
3861 .flags = FL_BASE0,
3862 .num_ports = 2,
3863 .base_baud = 115200,
3864 },
3865 [pbn_brcm_trumanage] = {
3866 .flags = FL_BASE0,
3867 .num_ports = 1,
3868 .reg_shift = 2,
3869 .base_baud = 115200,
3870 },
3871 [pbn_fintek_4] = {
3872 .num_ports = 4,
3873 .uart_offset = 8,
3874 .base_baud = 115200,
3875 .first_offset = 0x40,
3876 },
3877 [pbn_fintek_8] = {
3878 .num_ports = 8,
3879 .uart_offset = 8,
3880 .base_baud = 115200,
3881 .first_offset = 0x40,
3882 },
3883 [pbn_fintek_12] = {
3884 .num_ports = 12,
3885 .uart_offset = 8,
3886 .base_baud = 115200,
3887 .first_offset = 0x40,
3888 },
3889 [pbn_fintek_F81504A] = {
3890 .num_ports = 4,
3891 .uart_offset = 8,
3892 .base_baud = 115200,
3893 },
3894 [pbn_fintek_F81508A] = {
3895 .num_ports = 8,
3896 .uart_offset = 8,
3897 .base_baud = 115200,
3898 },
3899 [pbn_fintek_F81512A] = {
3900 .num_ports = 12,
3901 .uart_offset = 8,
3902 .base_baud = 115200,
3903 },
3904 [pbn_wch382_2] = {
3905 .flags = FL_BASE0,
3906 .num_ports = 2,
3907 .base_baud = 115200,
3908 .uart_offset = 8,
3909 .first_offset = 0xC0,
3910 },
3911 [pbn_wch384_4] = {
3912 .flags = FL_BASE0,
3913 .num_ports = 4,
3914 .base_baud = 115200,
3915 .uart_offset = 8,
3916 .first_offset = 0xC0,
3917 },
3918 /*
3919 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3920 */
3921 [pbn_pericom_PI7C9X7951] = {
3922 .flags = FL_BASE0,
3923 .num_ports = 1,
3924 .base_baud = 921600,
3925 .uart_offset = 0x8,
3926 },
3927 [pbn_pericom_PI7C9X7952] = {
3928 .flags = FL_BASE0,
3929 .num_ports = 2,
3930 .base_baud = 921600,
3931 .uart_offset = 0x8,
3932 },
3933 [pbn_pericom_PI7C9X7954] = {
3934 .flags = FL_BASE0,
3935 .num_ports = 4,
3936 .base_baud = 921600,
3937 .uart_offset = 0x8,
3938 },
3939 [pbn_pericom_PI7C9X7958] = {
3940 .flags = FL_BASE0,
3941 .num_ports = 8,
3942 .base_baud = 921600,
3943 .uart_offset = 0x8,
3944 },
3945 [pbn_sunix_pci_1s] = {
3946 .num_ports = 1,
3947 .base_baud = 921600,
3948 .uart_offset = 0x8,
3949 },
3950 [pbn_sunix_pci_2s] = {
3951 .num_ports = 2,
3952 .base_baud = 921600,
3953 .uart_offset = 0x8,
3954 },
3955 [pbn_sunix_pci_4s] = {
3956 .num_ports = 4,
3957 .base_baud = 921600,
3958 .uart_offset = 0x8,
3959 },
3960 [pbn_sunix_pci_8s] = {
3961 .num_ports = 8,
3962 .base_baud = 921600,
3963 .uart_offset = 0x8,
3964 },
3965 [pbn_sunix_pci_16s] = {
3966 .num_ports = 16,
3967 .base_baud = 921600,
3968 .uart_offset = 0x8,
3969 },
3970 [pbn_moxa8250_2p] = {
3971 .flags = FL_BASE1,
3972 .num_ports = 2,
3973 .base_baud = 921600,
3974 .uart_offset = 0x200,
3975 },
3976 [pbn_moxa8250_4p] = {
3977 .flags = FL_BASE1,
3978 .num_ports = 4,
3979 .base_baud = 921600,
3980 .uart_offset = 0x200,
3981 },
3982 [pbn_moxa8250_8p] = {
3983 .flags = FL_BASE1,
3984 .num_ports = 8,
3985 .base_baud = 921600,
3986 .uart_offset = 0x200,
3987 },
3988 };
3989
3990 static const struct pci_device_id blacklist[] = {
3991 /* softmodems */
3992 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3993 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3994 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3995
3996 /* multi-io cards handled by parport_serial */
3997 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3998 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3999 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
4000
4001 /* Intel platforms with MID UART */
4002 { PCI_VDEVICE(INTEL, 0x081b), },
4003 { PCI_VDEVICE(INTEL, 0x081c), },
4004 { PCI_VDEVICE(INTEL, 0x081d), },
4005 { PCI_VDEVICE(INTEL, 0x1191), },
4006 { PCI_VDEVICE(INTEL, 0x18d8), },
4007 { PCI_VDEVICE(INTEL, 0x19d8), },
4008
4009 /* Intel platforms with DesignWare UART */
4010 { PCI_VDEVICE(INTEL, 0x0936), },
4011 { PCI_VDEVICE(INTEL, 0x0f0a), },
4012 { PCI_VDEVICE(INTEL, 0x0f0c), },
4013 { PCI_VDEVICE(INTEL, 0x228a), },
4014 { PCI_VDEVICE(INTEL, 0x228c), },
4015 { PCI_VDEVICE(INTEL, 0x9ce3), },
4016 { PCI_VDEVICE(INTEL, 0x9ce4), },
4017
4018 /* Exar devices */
4019 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
4020 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
4021
4022 /* End of the black list */
4023 { }
4024 };
4025
serial_pci_is_class_communication(struct pci_dev * dev)4026 static int serial_pci_is_class_communication(struct pci_dev *dev)
4027 {
4028 /*
4029 * If it is not a communications device or the programming
4030 * interface is greater than 6, give up.
4031 */
4032 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
4033 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
4034 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
4035 (dev->class & 0xff) > 6)
4036 return -ENODEV;
4037
4038 return 0;
4039 }
4040
4041 /*
4042 * Given a complete unknown PCI device, try to use some heuristics to
4043 * guess what the configuration might be, based on the pitiful PCI
4044 * serial specs. Returns 0 on success, -ENODEV on failure.
4045 */
4046 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)4047 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
4048 {
4049 int num_iomem, num_port, first_port = -1, i;
4050 int rc;
4051
4052 rc = serial_pci_is_class_communication(dev);
4053 if (rc)
4054 return rc;
4055
4056 /*
4057 * Should we try to make guesses for multiport serial devices later?
4058 */
4059 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
4060 return -ENODEV;
4061
4062 num_iomem = num_port = 0;
4063 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4064 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
4065 num_port++;
4066 if (first_port == -1)
4067 first_port = i;
4068 }
4069 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
4070 num_iomem++;
4071 }
4072
4073 /*
4074 * If there is 1 or 0 iomem regions, and exactly one port,
4075 * use it. We guess the number of ports based on the IO
4076 * region size.
4077 */
4078 if (num_iomem <= 1 && num_port == 1) {
4079 board->flags = first_port;
4080 board->num_ports = pci_resource_len(dev, first_port) / 8;
4081 return 0;
4082 }
4083
4084 /*
4085 * Now guess if we've got a board which indexes by BARs.
4086 * Each IO BAR should be 8 bytes, and they should follow
4087 * consecutively.
4088 */
4089 first_port = -1;
4090 num_port = 0;
4091 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
4092 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
4093 pci_resource_len(dev, i) == 8 &&
4094 (first_port == -1 || (first_port + num_port) == i)) {
4095 num_port++;
4096 if (first_port == -1)
4097 first_port = i;
4098 }
4099 }
4100
4101 if (num_port > 1) {
4102 board->flags = first_port | FL_BASE_BARS;
4103 board->num_ports = num_port;
4104 return 0;
4105 }
4106
4107 return -ENODEV;
4108 }
4109
4110 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)4111 serial_pci_matches(const struct pciserial_board *board,
4112 const struct pciserial_board *guessed)
4113 {
4114 return
4115 board->num_ports == guessed->num_ports &&
4116 board->base_baud == guessed->base_baud &&
4117 board->uart_offset == guessed->uart_offset &&
4118 board->reg_shift == guessed->reg_shift &&
4119 board->first_offset == guessed->first_offset;
4120 }
4121
4122 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)4123 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
4124 {
4125 struct uart_8250_port uart;
4126 struct serial_private *priv;
4127 struct pci_serial_quirk *quirk;
4128 int rc, nr_ports, i;
4129
4130 nr_ports = board->num_ports;
4131
4132 /*
4133 * Find an init and setup quirks.
4134 */
4135 quirk = find_quirk(dev);
4136
4137 /*
4138 * Run the new-style initialization function.
4139 * The initialization function returns:
4140 * <0 - error
4141 * 0 - use board->num_ports
4142 * >0 - number of ports
4143 */
4144 if (quirk->init) {
4145 rc = quirk->init(dev);
4146 if (rc < 0) {
4147 priv = ERR_PTR(rc);
4148 goto err_out;
4149 }
4150 if (rc)
4151 nr_ports = rc;
4152 }
4153
4154 priv = kzalloc(sizeof(struct serial_private) +
4155 sizeof(unsigned int) * nr_ports,
4156 GFP_KERNEL);
4157 if (!priv) {
4158 priv = ERR_PTR(-ENOMEM);
4159 goto err_deinit;
4160 }
4161
4162 priv->dev = dev;
4163 priv->quirk = quirk;
4164
4165 memset(&uart, 0, sizeof(uart));
4166 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
4167 uart.port.uartclk = board->base_baud * 16;
4168
4169 if (pci_match_id(pci_use_msi, dev)) {
4170 dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n");
4171 pci_set_master(dev);
4172 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4173 } else {
4174 dev_dbg(&dev->dev, "Using legacy interrupts\n");
4175 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
4176 }
4177 if (rc < 0) {
4178 kfree(priv);
4179 priv = ERR_PTR(rc);
4180 goto err_deinit;
4181 }
4182
4183 uart.port.irq = pci_irq_vector(dev, 0);
4184 uart.port.dev = &dev->dev;
4185
4186 for (i = 0; i < nr_ports; i++) {
4187 if (quirk->setup(priv, board, &uart, i))
4188 break;
4189
4190 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4191 uart.port.iobase, uart.port.irq, uart.port.iotype);
4192
4193 priv->line[i] = serial8250_register_8250_port(&uart);
4194 if (priv->line[i] < 0) {
4195 dev_err(&dev->dev,
4196 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4197 uart.port.iobase, uart.port.irq,
4198 uart.port.iotype, priv->line[i]);
4199 break;
4200 }
4201 }
4202 priv->nr = i;
4203 priv->board = board;
4204 return priv;
4205
4206 err_deinit:
4207 if (quirk->exit)
4208 quirk->exit(dev);
4209 err_out:
4210 return priv;
4211 }
4212 EXPORT_SYMBOL_GPL(pciserial_init_ports);
4213
pciserial_detach_ports(struct serial_private * priv)4214 static void pciserial_detach_ports(struct serial_private *priv)
4215 {
4216 struct pci_serial_quirk *quirk;
4217 int i;
4218
4219 for (i = 0; i < priv->nr; i++)
4220 serial8250_unregister_port(priv->line[i]);
4221
4222 /*
4223 * Find the exit quirks.
4224 */
4225 quirk = find_quirk(priv->dev);
4226 if (quirk->exit)
4227 quirk->exit(priv->dev);
4228 }
4229
pciserial_remove_ports(struct serial_private * priv)4230 void pciserial_remove_ports(struct serial_private *priv)
4231 {
4232 pciserial_detach_ports(priv);
4233 kfree(priv);
4234 }
4235 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4236
pciserial_suspend_ports(struct serial_private * priv)4237 void pciserial_suspend_ports(struct serial_private *priv)
4238 {
4239 int i;
4240
4241 for (i = 0; i < priv->nr; i++)
4242 if (priv->line[i] >= 0)
4243 serial8250_suspend_port(priv->line[i]);
4244
4245 /*
4246 * Ensure that every init quirk is properly torn down
4247 */
4248 if (priv->quirk->exit)
4249 priv->quirk->exit(priv->dev);
4250 }
4251 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4252
pciserial_resume_ports(struct serial_private * priv)4253 void pciserial_resume_ports(struct serial_private *priv)
4254 {
4255 int i;
4256
4257 /*
4258 * Ensure that the board is correctly configured.
4259 */
4260 if (priv->quirk->init)
4261 priv->quirk->init(priv->dev);
4262
4263 for (i = 0; i < priv->nr; i++)
4264 if (priv->line[i] >= 0)
4265 serial8250_resume_port(priv->line[i]);
4266 }
4267 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4268
4269 /*
4270 * Probe one serial board. Unfortunately, there is no rhyme nor reason
4271 * to the arrangement of serial ports on a PCI card.
4272 */
4273 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)4274 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4275 {
4276 struct pci_serial_quirk *quirk;
4277 struct serial_private *priv;
4278 const struct pciserial_board *board;
4279 const struct pci_device_id *exclude;
4280 struct pciserial_board tmp;
4281 int rc;
4282
4283 quirk = find_quirk(dev);
4284 if (quirk->probe) {
4285 rc = quirk->probe(dev);
4286 if (rc)
4287 return rc;
4288 }
4289
4290 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4291 dev_err(&dev->dev, "invalid driver_data: %ld\n",
4292 ent->driver_data);
4293 return -EINVAL;
4294 }
4295
4296 board = &pci_boards[ent->driver_data];
4297
4298 exclude = pci_match_id(blacklist, dev);
4299 if (exclude)
4300 return -ENODEV;
4301
4302 rc = pcim_enable_device(dev);
4303 pci_save_state(dev);
4304 if (rc)
4305 return rc;
4306
4307 if (ent->driver_data == pbn_default) {
4308 /*
4309 * Use a copy of the pci_board entry for this;
4310 * avoid changing entries in the table.
4311 */
4312 memcpy(&tmp, board, sizeof(struct pciserial_board));
4313 board = &tmp;
4314
4315 /*
4316 * We matched one of our class entries. Try to
4317 * determine the parameters of this board.
4318 */
4319 rc = serial_pci_guess_board(dev, &tmp);
4320 if (rc)
4321 return rc;
4322 } else {
4323 /*
4324 * We matched an explicit entry. If we are able to
4325 * detect this boards settings with our heuristic,
4326 * then we no longer need this entry.
4327 */
4328 memcpy(&tmp, &pci_boards[pbn_default],
4329 sizeof(struct pciserial_board));
4330 rc = serial_pci_guess_board(dev, &tmp);
4331 if (rc == 0 && serial_pci_matches(board, &tmp))
4332 moan_device("Redundant entry in serial pci_table.",
4333 dev);
4334 }
4335
4336 priv = pciserial_init_ports(dev, board);
4337 if (IS_ERR(priv))
4338 return PTR_ERR(priv);
4339
4340 pci_set_drvdata(dev, priv);
4341 return 0;
4342 }
4343
pciserial_remove_one(struct pci_dev * dev)4344 static void pciserial_remove_one(struct pci_dev *dev)
4345 {
4346 struct serial_private *priv = pci_get_drvdata(dev);
4347
4348 pciserial_remove_ports(priv);
4349 }
4350
4351 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)4352 static int pciserial_suspend_one(struct device *dev)
4353 {
4354 struct serial_private *priv = dev_get_drvdata(dev);
4355
4356 if (priv)
4357 pciserial_suspend_ports(priv);
4358
4359 return 0;
4360 }
4361
pciserial_resume_one(struct device * dev)4362 static int pciserial_resume_one(struct device *dev)
4363 {
4364 struct pci_dev *pdev = to_pci_dev(dev);
4365 struct serial_private *priv = pci_get_drvdata(pdev);
4366 int err;
4367
4368 if (priv) {
4369 /*
4370 * The device may have been disabled. Re-enable it.
4371 */
4372 err = pci_enable_device(pdev);
4373 /* FIXME: We cannot simply error out here */
4374 if (err)
4375 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4376 pciserial_resume_ports(priv);
4377 }
4378 return 0;
4379 }
4380 #endif
4381
4382 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4383 pciserial_resume_one);
4384
4385 static const struct pci_device_id serial_pci_tbl[] = {
4386 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4387 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4388 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4389 pbn_b2_8_921600 },
4390 /* Advantech also use 0x3618 and 0xf618 */
4391 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4392 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4393 pbn_b0_4_921600 },
4394 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4395 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4396 pbn_b0_4_921600 },
4397 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4398 PCI_SUBVENDOR_ID_CONNECT_TECH,
4399 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4400 pbn_b1_8_1382400 },
4401 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4402 PCI_SUBVENDOR_ID_CONNECT_TECH,
4403 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4404 pbn_b1_4_1382400 },
4405 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4406 PCI_SUBVENDOR_ID_CONNECT_TECH,
4407 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4408 pbn_b1_2_1382400 },
4409 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4410 PCI_SUBVENDOR_ID_CONNECT_TECH,
4411 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4412 pbn_b1_8_1382400 },
4413 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4414 PCI_SUBVENDOR_ID_CONNECT_TECH,
4415 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4416 pbn_b1_4_1382400 },
4417 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4418 PCI_SUBVENDOR_ID_CONNECT_TECH,
4419 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4420 pbn_b1_2_1382400 },
4421 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4422 PCI_SUBVENDOR_ID_CONNECT_TECH,
4423 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4424 pbn_b1_8_921600 },
4425 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4426 PCI_SUBVENDOR_ID_CONNECT_TECH,
4427 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4428 pbn_b1_8_921600 },
4429 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4430 PCI_SUBVENDOR_ID_CONNECT_TECH,
4431 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4432 pbn_b1_4_921600 },
4433 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4434 PCI_SUBVENDOR_ID_CONNECT_TECH,
4435 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4436 pbn_b1_4_921600 },
4437 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4438 PCI_SUBVENDOR_ID_CONNECT_TECH,
4439 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4440 pbn_b1_2_921600 },
4441 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4442 PCI_SUBVENDOR_ID_CONNECT_TECH,
4443 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4444 pbn_b1_8_921600 },
4445 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4446 PCI_SUBVENDOR_ID_CONNECT_TECH,
4447 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4448 pbn_b1_8_921600 },
4449 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4450 PCI_SUBVENDOR_ID_CONNECT_TECH,
4451 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4452 pbn_b1_4_921600 },
4453 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4454 PCI_SUBVENDOR_ID_CONNECT_TECH,
4455 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4456 pbn_b1_2_1250000 },
4457 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4458 PCI_SUBVENDOR_ID_CONNECT_TECH,
4459 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4460 pbn_b0_2_1843200 },
4461 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4462 PCI_SUBVENDOR_ID_CONNECT_TECH,
4463 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4464 pbn_b0_4_1843200 },
4465 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4466 PCI_VENDOR_ID_AFAVLAB,
4467 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4468 pbn_b0_4_1152000 },
4469 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4470 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4471 pbn_b2_bt_1_115200 },
4472 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4473 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4474 pbn_b2_bt_2_115200 },
4475 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_b2_bt_4_115200 },
4478 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4479 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4480 pbn_b2_bt_2_115200 },
4481 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4482 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4483 pbn_b2_bt_4_115200 },
4484 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4485 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4486 pbn_b2_8_115200 },
4487 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4488 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4489 pbn_b2_8_460800 },
4490 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4491 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4492 pbn_b2_8_115200 },
4493
4494 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4495 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4496 pbn_b2_bt_2_115200 },
4497 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4498 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4499 pbn_b2_bt_2_921600 },
4500 /*
4501 * VScom SPCOM800, from sl@s.pl
4502 */
4503 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4504 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4505 pbn_b2_8_921600 },
4506 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4507 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4508 pbn_b2_4_921600 },
4509 /* Unknown card - subdevice 0x1584 */
4510 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4511 PCI_VENDOR_ID_PLX,
4512 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4513 pbn_b2_4_115200 },
4514 /* Unknown card - subdevice 0x1588 */
4515 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4516 PCI_VENDOR_ID_PLX,
4517 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4518 pbn_b2_8_115200 },
4519 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4520 PCI_SUBVENDOR_ID_KEYSPAN,
4521 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4522 pbn_panacom },
4523 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 pbn_panacom4 },
4526 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528 pbn_panacom2 },
4529 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4530 PCI_VENDOR_ID_ESDGMBH,
4531 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4532 pbn_b2_4_115200 },
4533 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4534 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4535 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4536 pbn_b2_4_460800 },
4537 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4538 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4539 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4540 pbn_b2_8_460800 },
4541 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4542 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4543 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4544 pbn_b2_16_460800 },
4545 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4546 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4547 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4548 pbn_b2_16_460800 },
4549 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4550 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4551 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4552 pbn_b2_4_460800 },
4553 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4554 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4555 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4556 pbn_b2_8_460800 },
4557 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4558 PCI_SUBVENDOR_ID_EXSYS,
4559 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4560 pbn_b2_4_115200 },
4561 /*
4562 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4563 * (Exoray@isys.ca)
4564 */
4565 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4566 0x10b5, 0x106a, 0, 0,
4567 pbn_plx_romulus },
4568 /*
4569 * EndRun Technologies. PCI express device range.
4570 * EndRun PTP/1588 has 2 Native UARTs.
4571 */
4572 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4573 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4574 pbn_endrun_2_4000000 },
4575 /*
4576 * Quatech cards. These actually have configurable clocks but for
4577 * now we just use the default.
4578 *
4579 * 100 series are RS232, 200 series RS422,
4580 */
4581 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4582 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4583 pbn_b1_4_115200 },
4584 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4585 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586 pbn_b1_2_115200 },
4587 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4588 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4589 pbn_b2_2_115200 },
4590 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4591 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4592 pbn_b1_2_115200 },
4593 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4594 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4595 pbn_b2_2_115200 },
4596 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4597 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4598 pbn_b1_4_115200 },
4599 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4600 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4601 pbn_b1_8_115200 },
4602 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4603 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4604 pbn_b1_8_115200 },
4605 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4606 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4607 pbn_b1_4_115200 },
4608 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4609 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4610 pbn_b1_2_115200 },
4611 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4612 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4613 pbn_b1_4_115200 },
4614 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4615 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4616 pbn_b1_2_115200 },
4617 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4618 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4619 pbn_b2_4_115200 },
4620 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4621 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4622 pbn_b2_2_115200 },
4623 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4624 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4625 pbn_b2_1_115200 },
4626 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4627 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4628 pbn_b2_4_115200 },
4629 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4630 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4631 pbn_b2_2_115200 },
4632 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4633 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4634 pbn_b2_1_115200 },
4635 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4636 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4637 pbn_b0_8_115200 },
4638
4639 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4640 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4641 0, 0,
4642 pbn_b0_4_921600 },
4643 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4644 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4645 0, 0,
4646 pbn_b0_4_1152000 },
4647 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_b0_bt_2_921600 },
4650
4651 /*
4652 * The below card is a little controversial since it is the
4653 * subject of a PCI vendor/device ID clash. (See
4654 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4655 * For now just used the hex ID 0x950a.
4656 */
4657 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4658 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4659 0, 0, pbn_b0_2_115200 },
4660 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4661 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4662 0, 0, pbn_b0_2_115200 },
4663 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4664 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4665 pbn_b0_2_1130000 },
4666 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4667 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4668 pbn_b0_1_921600 },
4669 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4670 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4671 pbn_b0_4_115200 },
4672 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4673 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4674 pbn_b0_bt_2_921600 },
4675 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 pbn_b2_8_1152000 },
4678
4679 /*
4680 * Oxford Semiconductor Inc. Tornado PCI express device range.
4681 */
4682 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4683 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4684 pbn_b0_1_4000000 },
4685 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4686 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4687 pbn_b0_1_4000000 },
4688 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4689 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4690 pbn_oxsemi_1_4000000 },
4691 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4692 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4693 pbn_oxsemi_1_4000000 },
4694 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4695 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4696 pbn_b0_1_4000000 },
4697 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4698 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4699 pbn_b0_1_4000000 },
4700 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4701 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4702 pbn_oxsemi_1_4000000 },
4703 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4704 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4705 pbn_oxsemi_1_4000000 },
4706 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4707 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4708 pbn_b0_1_4000000 },
4709 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4710 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4711 pbn_b0_1_4000000 },
4712 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4713 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4714 pbn_b0_1_4000000 },
4715 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4716 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4717 pbn_b0_1_4000000 },
4718 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4719 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4720 pbn_oxsemi_2_4000000 },
4721 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4722 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4723 pbn_oxsemi_2_4000000 },
4724 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4725 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4726 pbn_oxsemi_4_4000000 },
4727 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4728 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4729 pbn_oxsemi_4_4000000 },
4730 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4731 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4732 pbn_oxsemi_8_4000000 },
4733 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4734 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4735 pbn_oxsemi_8_4000000 },
4736 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4737 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4738 pbn_oxsemi_1_4000000 },
4739 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4740 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4741 pbn_oxsemi_1_4000000 },
4742 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4743 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4744 pbn_oxsemi_1_4000000 },
4745 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4746 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4747 pbn_oxsemi_1_4000000 },
4748 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4749 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4750 pbn_oxsemi_1_4000000 },
4751 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4752 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4753 pbn_oxsemi_1_4000000 },
4754 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4755 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4756 pbn_oxsemi_1_4000000 },
4757 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4758 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4759 pbn_oxsemi_1_4000000 },
4760 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4761 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4762 pbn_oxsemi_1_4000000 },
4763 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4764 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4765 pbn_oxsemi_1_4000000 },
4766 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4767 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4768 pbn_oxsemi_1_4000000 },
4769 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4770 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4771 pbn_oxsemi_1_4000000 },
4772 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4773 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4774 pbn_oxsemi_1_4000000 },
4775 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4776 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4777 pbn_oxsemi_1_4000000 },
4778 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4779 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4780 pbn_oxsemi_1_4000000 },
4781 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4782 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4783 pbn_oxsemi_1_4000000 },
4784 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4785 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4786 pbn_oxsemi_1_4000000 },
4787 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4788 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4789 pbn_oxsemi_1_4000000 },
4790 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4791 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4792 pbn_oxsemi_1_4000000 },
4793 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4794 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4795 pbn_oxsemi_1_4000000 },
4796 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4797 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4798 pbn_oxsemi_1_4000000 },
4799 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4800 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4801 pbn_oxsemi_1_4000000 },
4802 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4803 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4804 pbn_oxsemi_1_4000000 },
4805 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4806 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4807 pbn_oxsemi_1_4000000 },
4808 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4809 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4810 pbn_oxsemi_1_4000000 },
4811 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4812 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4813 pbn_oxsemi_1_4000000 },
4814 /*
4815 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4816 */
4817 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4818 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4819 pbn_oxsemi_1_4000000 },
4820 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4821 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4822 pbn_oxsemi_2_4000000 },
4823 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4824 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4825 pbn_oxsemi_4_4000000 },
4826 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4827 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4828 pbn_oxsemi_8_4000000 },
4829
4830 /*
4831 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4832 */
4833 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4834 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4835 pbn_oxsemi_2_4000000 },
4836
4837 /*
4838 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4839 * from skokodyn@yahoo.com
4840 */
4841 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4842 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4843 pbn_sbsxrsio },
4844 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4845 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4846 pbn_sbsxrsio },
4847 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4848 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4849 pbn_sbsxrsio },
4850 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4851 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4852 pbn_sbsxrsio },
4853
4854 /*
4855 * Digitan DS560-558, from jimd@esoft.com
4856 */
4857 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4858 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4859 pbn_b1_1_115200 },
4860
4861 /*
4862 * Titan Electronic cards
4863 * The 400L and 800L have a custom setup quirk.
4864 */
4865 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4866 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4867 pbn_b0_1_921600 },
4868 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4869 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4870 pbn_b0_2_921600 },
4871 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4872 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4873 pbn_b0_4_921600 },
4874 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4875 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4876 pbn_b0_4_921600 },
4877 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4878 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4879 pbn_b1_1_921600 },
4880 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4881 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4882 pbn_b1_bt_2_921600 },
4883 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4884 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4885 pbn_b0_bt_4_921600 },
4886 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4887 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4888 pbn_b0_bt_8_921600 },
4889 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4890 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4891 pbn_b4_bt_2_921600 },
4892 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4893 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4894 pbn_b4_bt_4_921600 },
4895 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4896 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4897 pbn_b4_bt_8_921600 },
4898 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4899 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4900 pbn_b0_4_921600 },
4901 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4902 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4903 pbn_b0_4_921600 },
4904 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4905 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4906 pbn_b0_4_921600 },
4907 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4908 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4909 pbn_oxsemi_1_4000000 },
4910 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4911 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4912 pbn_oxsemi_2_4000000 },
4913 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4914 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4915 pbn_oxsemi_4_4000000 },
4916 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4917 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4918 pbn_oxsemi_8_4000000 },
4919 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4920 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4921 pbn_oxsemi_2_4000000 },
4922 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4923 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4924 pbn_oxsemi_2_4000000 },
4925 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4926 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4927 pbn_b0_bt_2_921600 },
4928 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4929 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4930 pbn_b0_4_921600 },
4931 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4932 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4933 pbn_b0_4_921600 },
4934 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4935 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4936 pbn_b0_4_921600 },
4937 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4938 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4939 pbn_b0_4_921600 },
4940
4941 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4943 pbn_b2_1_460800 },
4944 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4946 pbn_b2_1_460800 },
4947 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4949 pbn_b2_1_460800 },
4950 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4951 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4952 pbn_b2_bt_2_921600 },
4953 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4954 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4955 pbn_b2_bt_2_921600 },
4956 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4957 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4958 pbn_b2_bt_2_921600 },
4959 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4960 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4961 pbn_b2_bt_4_921600 },
4962 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4963 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4964 pbn_b2_bt_4_921600 },
4965 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4966 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4967 pbn_b2_bt_4_921600 },
4968 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4969 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4970 pbn_b0_1_921600 },
4971 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4972 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4973 pbn_b0_1_921600 },
4974 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4975 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4976 pbn_b0_1_921600 },
4977 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4978 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4979 pbn_b0_bt_2_921600 },
4980 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4982 pbn_b0_bt_2_921600 },
4983 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4985 pbn_b0_bt_2_921600 },
4986 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4987 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4988 pbn_b0_bt_4_921600 },
4989 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4990 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4991 pbn_b0_bt_4_921600 },
4992 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4993 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4994 pbn_b0_bt_4_921600 },
4995 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4996 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4997 pbn_b0_bt_8_921600 },
4998 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4999 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5000 pbn_b0_bt_8_921600 },
5001 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
5002 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5003 pbn_b0_bt_8_921600 },
5004
5005 /*
5006 * Computone devices submitted by Doug McNash dmcnash@computone.com
5007 */
5008 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5009 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
5010 0, 0, pbn_computone_4 },
5011 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5012 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
5013 0, 0, pbn_computone_8 },
5014 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
5015 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
5016 0, 0, pbn_computone_6 },
5017
5018 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
5019 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5020 pbn_oxsemi },
5021 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
5022 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
5023 pbn_b0_bt_1_921600 },
5024
5025 /*
5026 * Sunix PCI serial boards
5027 */
5028 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5029 PCI_VENDOR_ID_SUNIX, 0x0001, 0, 0,
5030 pbn_sunix_pci_1s },
5031 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5032 PCI_VENDOR_ID_SUNIX, 0x0002, 0, 0,
5033 pbn_sunix_pci_2s },
5034 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5035 PCI_VENDOR_ID_SUNIX, 0x0004, 0, 0,
5036 pbn_sunix_pci_4s },
5037 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5038 PCI_VENDOR_ID_SUNIX, 0x0084, 0, 0,
5039 pbn_sunix_pci_4s },
5040 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5041 PCI_VENDOR_ID_SUNIX, 0x0008, 0, 0,
5042 pbn_sunix_pci_8s },
5043 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5044 PCI_VENDOR_ID_SUNIX, 0x0088, 0, 0,
5045 pbn_sunix_pci_8s },
5046 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
5047 PCI_VENDOR_ID_SUNIX, 0x0010, 0, 0,
5048 pbn_sunix_pci_16s },
5049
5050 /*
5051 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
5052 */
5053 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
5054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5055 pbn_b0_bt_8_115200 },
5056 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
5057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5058 pbn_b0_bt_8_115200 },
5059
5060 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
5061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5062 pbn_b0_bt_2_115200 },
5063 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
5064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5065 pbn_b0_bt_2_115200 },
5066 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
5067 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5068 pbn_b0_bt_2_115200 },
5069 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
5070 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5071 pbn_b0_bt_2_115200 },
5072 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
5073 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5074 pbn_b0_bt_2_115200 },
5075 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
5076 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5077 pbn_b0_bt_4_460800 },
5078 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
5079 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5080 pbn_b0_bt_4_460800 },
5081 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
5082 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5083 pbn_b0_bt_2_460800 },
5084 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
5085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5086 pbn_b0_bt_2_460800 },
5087 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
5088 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5089 pbn_b0_bt_2_460800 },
5090 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
5091 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5092 pbn_b0_bt_1_115200 },
5093 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
5094 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5095 pbn_b0_bt_1_460800 },
5096
5097 /*
5098 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
5099 * Cards are identified by their subsystem vendor IDs, which
5100 * (in hex) match the model number.
5101 *
5102 * Note that JC140x are RS422/485 cards which require ox950
5103 * ACR = 0x10, and as such are not currently fully supported.
5104 */
5105 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5106 0x1204, 0x0004, 0, 0,
5107 pbn_b0_4_921600 },
5108 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5109 0x1208, 0x0004, 0, 0,
5110 pbn_b0_4_921600 },
5111 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5112 0x1402, 0x0002, 0, 0,
5113 pbn_b0_2_921600 }, */
5114 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
5115 0x1404, 0x0004, 0, 0,
5116 pbn_b0_4_921600 }, */
5117 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
5118 0x1208, 0x0004, 0, 0,
5119 pbn_b0_4_921600 },
5120
5121 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5122 0x1204, 0x0004, 0, 0,
5123 pbn_b0_4_921600 },
5124 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
5125 0x1208, 0x0004, 0, 0,
5126 pbn_b0_4_921600 },
5127 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
5128 0x1208, 0x0004, 0, 0,
5129 pbn_b0_4_921600 },
5130 /*
5131 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
5132 */
5133 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
5134 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5135 pbn_b1_1_1382400 },
5136
5137 /*
5138 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
5139 */
5140 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
5141 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5142 pbn_b1_1_1382400 },
5143
5144 /*
5145 * RAStel 2 port modem, gerg@moreton.com.au
5146 */
5147 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
5148 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5149 pbn_b2_bt_2_115200 },
5150
5151 /*
5152 * EKF addition for i960 Boards form EKF with serial port
5153 */
5154 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
5155 0xE4BF, PCI_ANY_ID, 0, 0,
5156 pbn_intel_i960 },
5157
5158 /*
5159 * Xircom Cardbus/Ethernet combos
5160 */
5161 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
5162 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5163 pbn_b0_1_115200 },
5164 /*
5165 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
5166 */
5167 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
5168 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5169 pbn_b0_1_115200 },
5170
5171 /*
5172 * Untested PCI modems, sent in from various folks...
5173 */
5174
5175 /*
5176 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
5177 */
5178 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
5179 0x1048, 0x1500, 0, 0,
5180 pbn_b1_1_115200 },
5181
5182 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
5183 0xFF00, 0, 0, 0,
5184 pbn_sgi_ioc3 },
5185
5186 /*
5187 * HP Diva card
5188 */
5189 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5190 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
5191 pbn_b1_1_115200 },
5192 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
5193 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5194 pbn_b0_5_115200 },
5195 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
5196 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5197 pbn_b2_1_115200 },
5198
5199 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
5200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5201 pbn_b3_2_115200 },
5202 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
5203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5204 pbn_b3_4_115200 },
5205 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
5206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5207 pbn_b3_8_115200 },
5208 /*
5209 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
5210 */
5211 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
5212 PCI_ANY_ID, PCI_ANY_ID,
5213 0,
5214 0, pbn_pericom_PI7C9X7951 },
5215 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
5216 PCI_ANY_ID, PCI_ANY_ID,
5217 0,
5218 0, pbn_pericom_PI7C9X7952 },
5219 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
5220 PCI_ANY_ID, PCI_ANY_ID,
5221 0,
5222 0, pbn_pericom_PI7C9X7954 },
5223 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
5224 PCI_ANY_ID, PCI_ANY_ID,
5225 0,
5226 0, pbn_pericom_PI7C9X7958 },
5227 /*
5228 * ACCES I/O Products quad
5229 */
5230 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
5231 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5232 pbn_pericom_PI7C9X7952 },
5233 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
5234 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5235 pbn_pericom_PI7C9X7952 },
5236 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
5237 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5238 pbn_pericom_PI7C9X7954 },
5239 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
5240 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5241 pbn_pericom_PI7C9X7954 },
5242 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
5243 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5244 pbn_pericom_PI7C9X7952 },
5245 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
5246 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5247 pbn_pericom_PI7C9X7952 },
5248 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
5249 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5250 pbn_pericom_PI7C9X7954 },
5251 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
5252 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5253 pbn_pericom_PI7C9X7954 },
5254 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
5255 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5256 pbn_pericom_PI7C9X7952 },
5257 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
5258 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5259 pbn_pericom_PI7C9X7952 },
5260 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
5261 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5262 pbn_pericom_PI7C9X7954 },
5263 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
5264 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5265 pbn_pericom_PI7C9X7954 },
5266 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
5267 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5268 pbn_pericom_PI7C9X7951 },
5269 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
5270 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5271 pbn_pericom_PI7C9X7952 },
5272 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
5273 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5274 pbn_pericom_PI7C9X7952 },
5275 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
5276 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5277 pbn_pericom_PI7C9X7954 },
5278 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
5279 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5280 pbn_pericom_PI7C9X7954 },
5281 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
5282 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5283 pbn_pericom_PI7C9X7952 },
5284 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
5285 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5286 pbn_pericom_PI7C9X7954 },
5287 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
5288 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5289 pbn_pericom_PI7C9X7952 },
5290 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
5291 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5292 pbn_pericom_PI7C9X7952 },
5293 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
5294 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5295 pbn_pericom_PI7C9X7954 },
5296 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
5297 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5298 pbn_pericom_PI7C9X7954 },
5299 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
5300 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5301 pbn_pericom_PI7C9X7952 },
5302 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
5303 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5304 pbn_pericom_PI7C9X7954 },
5305 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
5306 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5307 pbn_pericom_PI7C9X7954 },
5308 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
5309 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5310 pbn_pericom_PI7C9X7958 },
5311 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
5312 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5313 pbn_pericom_PI7C9X7958 },
5314 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
5315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5316 pbn_pericom_PI7C9X7954 },
5317 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
5318 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5319 pbn_pericom_PI7C9X7958 },
5320 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
5321 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5322 pbn_pericom_PI7C9X7954 },
5323 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
5324 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5325 pbn_pericom_PI7C9X7958 },
5326 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
5327 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5328 pbn_pericom_PI7C9X7954 },
5329 /*
5330 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
5331 */
5332 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
5333 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5334 pbn_b0_1_115200 },
5335 /*
5336 * ITE
5337 */
5338 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
5339 PCI_ANY_ID, PCI_ANY_ID,
5340 0, 0,
5341 pbn_b1_bt_1_115200 },
5342
5343 /*
5344 * IntaShield IS-200
5345 */
5346 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
5347 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
5348 pbn_b2_2_115200 },
5349 /*
5350 * IntaShield IS-400
5351 */
5352 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
5353 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
5354 pbn_b2_4_115200 },
5355 /*
5356 * BrainBoxes UC-260
5357 */
5358 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
5359 PCI_ANY_ID, PCI_ANY_ID,
5360 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5361 pbn_b2_4_115200 },
5362 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
5363 PCI_ANY_ID, PCI_ANY_ID,
5364 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
5365 pbn_b2_4_115200 },
5366 /*
5367 * Perle PCI-RAS cards
5368 */
5369 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5370 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
5371 0, 0, pbn_b2_4_921600 },
5372 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
5373 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
5374 0, 0, pbn_b2_8_921600 },
5375
5376 /*
5377 * Mainpine series cards: Fairly standard layout but fools
5378 * parts of the autodetect in some cases and uses otherwise
5379 * unmatched communications subclasses in the PCI Express case
5380 */
5381
5382 { /* RockForceDUO */
5383 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5384 PCI_VENDOR_ID_MAINPINE, 0x0200,
5385 0, 0, pbn_b0_2_115200 },
5386 { /* RockForceQUATRO */
5387 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5388 PCI_VENDOR_ID_MAINPINE, 0x0300,
5389 0, 0, pbn_b0_4_115200 },
5390 { /* RockForceDUO+ */
5391 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5392 PCI_VENDOR_ID_MAINPINE, 0x0400,
5393 0, 0, pbn_b0_2_115200 },
5394 { /* RockForceQUATRO+ */
5395 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5396 PCI_VENDOR_ID_MAINPINE, 0x0500,
5397 0, 0, pbn_b0_4_115200 },
5398 { /* RockForce+ */
5399 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5400 PCI_VENDOR_ID_MAINPINE, 0x0600,
5401 0, 0, pbn_b0_2_115200 },
5402 { /* RockForce+ */
5403 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5404 PCI_VENDOR_ID_MAINPINE, 0x0700,
5405 0, 0, pbn_b0_4_115200 },
5406 { /* RockForceOCTO+ */
5407 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5408 PCI_VENDOR_ID_MAINPINE, 0x0800,
5409 0, 0, pbn_b0_8_115200 },
5410 { /* RockForceDUO+ */
5411 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5412 PCI_VENDOR_ID_MAINPINE, 0x0C00,
5413 0, 0, pbn_b0_2_115200 },
5414 { /* RockForceQUARTRO+ */
5415 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5416 PCI_VENDOR_ID_MAINPINE, 0x0D00,
5417 0, 0, pbn_b0_4_115200 },
5418 { /* RockForceOCTO+ */
5419 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5420 PCI_VENDOR_ID_MAINPINE, 0x1D00,
5421 0, 0, pbn_b0_8_115200 },
5422 { /* RockForceD1 */
5423 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5424 PCI_VENDOR_ID_MAINPINE, 0x2000,
5425 0, 0, pbn_b0_1_115200 },
5426 { /* RockForceF1 */
5427 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5428 PCI_VENDOR_ID_MAINPINE, 0x2100,
5429 0, 0, pbn_b0_1_115200 },
5430 { /* RockForceD2 */
5431 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5432 PCI_VENDOR_ID_MAINPINE, 0x2200,
5433 0, 0, pbn_b0_2_115200 },
5434 { /* RockForceF2 */
5435 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5436 PCI_VENDOR_ID_MAINPINE, 0x2300,
5437 0, 0, pbn_b0_2_115200 },
5438 { /* RockForceD4 */
5439 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5440 PCI_VENDOR_ID_MAINPINE, 0x2400,
5441 0, 0, pbn_b0_4_115200 },
5442 { /* RockForceF4 */
5443 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5444 PCI_VENDOR_ID_MAINPINE, 0x2500,
5445 0, 0, pbn_b0_4_115200 },
5446 { /* RockForceD8 */
5447 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5448 PCI_VENDOR_ID_MAINPINE, 0x2600,
5449 0, 0, pbn_b0_8_115200 },
5450 { /* RockForceF8 */
5451 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5452 PCI_VENDOR_ID_MAINPINE, 0x2700,
5453 0, 0, pbn_b0_8_115200 },
5454 { /* IQ Express D1 */
5455 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5456 PCI_VENDOR_ID_MAINPINE, 0x3000,
5457 0, 0, pbn_b0_1_115200 },
5458 { /* IQ Express F1 */
5459 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5460 PCI_VENDOR_ID_MAINPINE, 0x3100,
5461 0, 0, pbn_b0_1_115200 },
5462 { /* IQ Express D2 */
5463 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5464 PCI_VENDOR_ID_MAINPINE, 0x3200,
5465 0, 0, pbn_b0_2_115200 },
5466 { /* IQ Express F2 */
5467 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5468 PCI_VENDOR_ID_MAINPINE, 0x3300,
5469 0, 0, pbn_b0_2_115200 },
5470 { /* IQ Express D4 */
5471 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5472 PCI_VENDOR_ID_MAINPINE, 0x3400,
5473 0, 0, pbn_b0_4_115200 },
5474 { /* IQ Express F4 */
5475 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5476 PCI_VENDOR_ID_MAINPINE, 0x3500,
5477 0, 0, pbn_b0_4_115200 },
5478 { /* IQ Express D8 */
5479 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5480 PCI_VENDOR_ID_MAINPINE, 0x3C00,
5481 0, 0, pbn_b0_8_115200 },
5482 { /* IQ Express F8 */
5483 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
5484 PCI_VENDOR_ID_MAINPINE, 0x3D00,
5485 0, 0, pbn_b0_8_115200 },
5486
5487
5488 /*
5489 * PA Semi PA6T-1682M on-chip UART
5490 */
5491 { PCI_VENDOR_ID_PASEMI, 0xa004,
5492 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5493 pbn_pasemi_1682M },
5494
5495 /*
5496 * National Instruments
5497 */
5498 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
5499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5500 pbn_b1_16_115200 },
5501 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
5502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5503 pbn_b1_8_115200 },
5504 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
5505 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5506 pbn_b1_bt_4_115200 },
5507 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
5508 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5509 pbn_b1_bt_2_115200 },
5510 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
5511 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5512 pbn_b1_bt_4_115200 },
5513 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
5514 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5515 pbn_b1_bt_2_115200 },
5516 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
5517 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5518 pbn_b1_16_115200 },
5519 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
5520 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5521 pbn_b1_8_115200 },
5522 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
5523 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5524 pbn_b1_bt_4_115200 },
5525 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
5526 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5527 pbn_b1_bt_2_115200 },
5528 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
5529 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5530 pbn_b1_bt_4_115200 },
5531 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
5532 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5533 pbn_b1_bt_2_115200 },
5534 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
5535 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5536 pbn_ni8430_2 },
5537 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
5538 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5539 pbn_ni8430_2 },
5540 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
5541 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5542 pbn_ni8430_4 },
5543 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
5544 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5545 pbn_ni8430_4 },
5546 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
5547 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5548 pbn_ni8430_8 },
5549 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
5550 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5551 pbn_ni8430_8 },
5552 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
5553 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5554 pbn_ni8430_16 },
5555 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5556 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5557 pbn_ni8430_16 },
5558 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5559 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5560 pbn_ni8430_2 },
5561 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5562 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5563 pbn_ni8430_2 },
5564 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5565 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5566 pbn_ni8430_4 },
5567 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5568 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5569 pbn_ni8430_4 },
5570 { PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8430_2328,
5571 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5572 pbn_ni8430_pxie_8 },
5573 { PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8430_23216,
5574 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5575 pbn_ni8430_pxie_16 },
5576 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8431_4852,
5577 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5578 pbn_ni8431_2 },
5579 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8431_4854,
5580 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5581 pbn_ni8431_4 },
5582 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8431_4858,
5583 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5584 pbn_ni8431_8 },
5585 { PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8431_4858,
5586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5587 pbn_ni8431_pxie_8 },
5588 { PCI_VENDOR_ID_NI, PCIE_DEVICE_ID_NI_PXIE8431_48516,
5589 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5590 pbn_ni8431_pxie_16 },
5591 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8433_4852,
5592 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5593 pbn_ni8431_2 },
5594 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8433_4854,
5595 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5596 pbn_ni8431_4 },
5597
5598 /*
5599 * MOXA
5600 */
5601 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102E,
5602 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5603 pbn_moxa8250_2p },
5604 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP102EL,
5605 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5606 pbn_moxa8250_2p },
5607 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A,
5608 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5609 pbn_moxa8250_4p },
5610 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP114EL,
5611 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5612 pbn_moxa8250_4p },
5613 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A,
5614 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5615 pbn_moxa8250_8p },
5616 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B,
5617 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5618 pbn_moxa8250_8p },
5619 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A,
5620 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5621 pbn_moxa8250_8p },
5622 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I,
5623 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5624 pbn_moxa8250_8p },
5625 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP132EL,
5626 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5627 pbn_moxa8250_2p },
5628 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A,
5629 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5630 pbn_moxa8250_4p },
5631 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP138E_A,
5632 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5633 pbn_moxa8250_8p },
5634 { PCI_VENDOR_ID_MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A,
5635 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5636 pbn_moxa8250_8p },
5637
5638 /*
5639 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5640 */
5641 { PCI_VENDOR_ID_ADDIDATA,
5642 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5643 PCI_ANY_ID,
5644 PCI_ANY_ID,
5645 0,
5646 0,
5647 pbn_b0_4_115200 },
5648
5649 { PCI_VENDOR_ID_ADDIDATA,
5650 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5651 PCI_ANY_ID,
5652 PCI_ANY_ID,
5653 0,
5654 0,
5655 pbn_b0_2_115200 },
5656
5657 { PCI_VENDOR_ID_ADDIDATA,
5658 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5659 PCI_ANY_ID,
5660 PCI_ANY_ID,
5661 0,
5662 0,
5663 pbn_b0_1_115200 },
5664
5665 { PCI_VENDOR_ID_AMCC,
5666 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5667 PCI_ANY_ID,
5668 PCI_ANY_ID,
5669 0,
5670 0,
5671 pbn_b1_8_115200 },
5672
5673 { PCI_VENDOR_ID_ADDIDATA,
5674 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5675 PCI_ANY_ID,
5676 PCI_ANY_ID,
5677 0,
5678 0,
5679 pbn_b0_4_115200 },
5680
5681 { PCI_VENDOR_ID_ADDIDATA,
5682 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5683 PCI_ANY_ID,
5684 PCI_ANY_ID,
5685 0,
5686 0,
5687 pbn_b0_2_115200 },
5688
5689 { PCI_VENDOR_ID_ADDIDATA,
5690 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5691 PCI_ANY_ID,
5692 PCI_ANY_ID,
5693 0,
5694 0,
5695 pbn_b0_1_115200 },
5696
5697 { PCI_VENDOR_ID_ADDIDATA,
5698 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5699 PCI_ANY_ID,
5700 PCI_ANY_ID,
5701 0,
5702 0,
5703 pbn_b0_4_115200 },
5704
5705 { PCI_VENDOR_ID_ADDIDATA,
5706 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5707 PCI_ANY_ID,
5708 PCI_ANY_ID,
5709 0,
5710 0,
5711 pbn_b0_2_115200 },
5712
5713 { PCI_VENDOR_ID_ADDIDATA,
5714 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5715 PCI_ANY_ID,
5716 PCI_ANY_ID,
5717 0,
5718 0,
5719 pbn_b0_1_115200 },
5720
5721 { PCI_VENDOR_ID_ADDIDATA,
5722 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5723 PCI_ANY_ID,
5724 PCI_ANY_ID,
5725 0,
5726 0,
5727 pbn_b0_8_115200 },
5728
5729 { PCI_VENDOR_ID_ADDIDATA,
5730 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5731 PCI_ANY_ID,
5732 PCI_ANY_ID,
5733 0,
5734 0,
5735 pbn_ADDIDATA_PCIe_4_3906250 },
5736
5737 { PCI_VENDOR_ID_ADDIDATA,
5738 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5739 PCI_ANY_ID,
5740 PCI_ANY_ID,
5741 0,
5742 0,
5743 pbn_ADDIDATA_PCIe_2_3906250 },
5744
5745 { PCI_VENDOR_ID_ADDIDATA,
5746 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5747 PCI_ANY_ID,
5748 PCI_ANY_ID,
5749 0,
5750 0,
5751 pbn_ADDIDATA_PCIe_1_3906250 },
5752
5753 { PCI_VENDOR_ID_ADDIDATA,
5754 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5755 PCI_ANY_ID,
5756 PCI_ANY_ID,
5757 0,
5758 0,
5759 pbn_ADDIDATA_PCIe_8_3906250 },
5760
5761 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5762 PCI_VENDOR_ID_IBM, 0x0299,
5763 0, 0, pbn_b0_bt_2_115200 },
5764
5765 /*
5766 * other NetMos 9835 devices are most likely handled by the
5767 * parport_serial driver, check drivers/parport/parport_serial.c
5768 * before adding them here.
5769 */
5770
5771 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5772 0xA000, 0x1000,
5773 0, 0, pbn_b0_1_115200 },
5774
5775 /* the 9901 is a rebranded 9912 */
5776 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5777 0xA000, 0x1000,
5778 0, 0, pbn_b0_1_115200 },
5779
5780 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5781 0xA000, 0x1000,
5782 0, 0, pbn_b0_1_115200 },
5783
5784 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5785 0xA000, 0x1000,
5786 0, 0, pbn_b0_1_115200 },
5787
5788 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5789 0xA000, 0x1000,
5790 0, 0, pbn_b0_1_115200 },
5791
5792 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5793 0xA000, 0x3002,
5794 0, 0, pbn_NETMOS9900_2s_115200 },
5795
5796 /*
5797 * Best Connectivity and Rosewill PCI Multi I/O cards
5798 */
5799
5800 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5801 0xA000, 0x1000,
5802 0, 0, pbn_b0_1_115200 },
5803
5804 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5805 0xA000, 0x3002,
5806 0, 0, pbn_b0_bt_2_115200 },
5807
5808 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5809 0xA000, 0x3004,
5810 0, 0, pbn_b0_bt_4_115200 },
5811 /* Intel CE4100 */
5812 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5813 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5814 pbn_ce4100_1_115200 },
5815
5816 /*
5817 * Cronyx Omega PCI
5818 */
5819 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5821 pbn_omegapci },
5822
5823 /*
5824 * Broadcom TruManage
5825 */
5826 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5828 pbn_brcm_trumanage },
5829
5830 /*
5831 * AgeStar as-prs2-009
5832 */
5833 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5834 PCI_ANY_ID, PCI_ANY_ID,
5835 0, 0, pbn_b0_bt_2_115200 },
5836
5837 /*
5838 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5839 * so not listed here.
5840 */
5841 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5842 PCI_ANY_ID, PCI_ANY_ID,
5843 0, 0, pbn_b0_bt_4_115200 },
5844
5845 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5846 PCI_ANY_ID, PCI_ANY_ID,
5847 0, 0, pbn_b0_bt_2_115200 },
5848
5849 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5850 PCI_ANY_ID, PCI_ANY_ID,
5851 0, 0, pbn_b0_bt_4_115200 },
5852
5853 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5854 PCI_ANY_ID, PCI_ANY_ID,
5855 0, 0, pbn_wch382_2 },
5856
5857 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5858 PCI_ANY_ID, PCI_ANY_ID,
5859 0, 0, pbn_wch384_4 },
5860
5861 /* Fintek PCI serial cards */
5862 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5863 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5864 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5865 { PCI_DEVICE(0x1c29, 0x1204), .driver_data = pbn_fintek_F81504A },
5866 { PCI_DEVICE(0x1c29, 0x1208), .driver_data = pbn_fintek_F81508A },
5867 { PCI_DEVICE(0x1c29, 0x1212), .driver_data = pbn_fintek_F81512A },
5868
5869 /* MKS Tenta SCOM-080x serial cards */
5870 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5871 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5872
5873 /* Amazon PCI serial device */
5874 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5875
5876 /*
5877 * These entries match devices with class COMMUNICATION_SERIAL,
5878 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5879 */
5880 { PCI_ANY_ID, PCI_ANY_ID,
5881 PCI_ANY_ID, PCI_ANY_ID,
5882 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5883 0xffff00, pbn_default },
5884 { PCI_ANY_ID, PCI_ANY_ID,
5885 PCI_ANY_ID, PCI_ANY_ID,
5886 PCI_CLASS_COMMUNICATION_MODEM << 8,
5887 0xffff00, pbn_default },
5888 { PCI_ANY_ID, PCI_ANY_ID,
5889 PCI_ANY_ID, PCI_ANY_ID,
5890 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5891 0xffff00, pbn_default },
5892 { 0, }
5893 };
5894
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)5895 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5896 pci_channel_state_t state)
5897 {
5898 struct serial_private *priv = pci_get_drvdata(dev);
5899
5900 if (state == pci_channel_io_perm_failure)
5901 return PCI_ERS_RESULT_DISCONNECT;
5902
5903 if (priv)
5904 pciserial_detach_ports(priv);
5905
5906 pci_disable_device(dev);
5907
5908 return PCI_ERS_RESULT_NEED_RESET;
5909 }
5910
serial8250_io_slot_reset(struct pci_dev * dev)5911 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5912 {
5913 int rc;
5914
5915 rc = pci_enable_device(dev);
5916
5917 if (rc)
5918 return PCI_ERS_RESULT_DISCONNECT;
5919
5920 pci_restore_state(dev);
5921 pci_save_state(dev);
5922
5923 return PCI_ERS_RESULT_RECOVERED;
5924 }
5925
serial8250_io_resume(struct pci_dev * dev)5926 static void serial8250_io_resume(struct pci_dev *dev)
5927 {
5928 struct serial_private *priv = pci_get_drvdata(dev);
5929 struct serial_private *new;
5930
5931 if (!priv)
5932 return;
5933
5934 new = pciserial_init_ports(dev, priv->board);
5935 if (!IS_ERR(new)) {
5936 pci_set_drvdata(dev, new);
5937 kfree(priv);
5938 }
5939 }
5940
5941 static const struct pci_error_handlers serial8250_err_handler = {
5942 .error_detected = serial8250_io_error_detected,
5943 .slot_reset = serial8250_io_slot_reset,
5944 .resume = serial8250_io_resume,
5945 };
5946
5947 static struct pci_driver serial_pci_driver = {
5948 .name = "serial",
5949 .probe = pciserial_init_one,
5950 .remove = pciserial_remove_one,
5951 .driver = {
5952 .pm = &pciserial_pm_ops,
5953 },
5954 .id_table = serial_pci_tbl,
5955 .err_handler = &serial8250_err_handler,
5956 };
5957
5958 module_pci_driver(serial_pci_driver);
5959
5960 MODULE_LICENSE("GPL");
5961 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5962 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5963
