1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * drivers/soc/tegra/pmc.c
4 *
5 * Copyright (c) 2010 Google, Inc
6 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
7 *
8 * Author:
9 * Colin Cross <ccross@google.com>
10 */
11
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
13
14 #include <linux/arm-smccc.h>
15 #include <linux/clk.h>
16 #include <linux/clk/tegra.h>
17 #include <linux/debugfs.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/export.h>
21 #include <linux/init.h>
22 #include <linux/io.h>
23 #include <linux/iopoll.h>
24 #include <linux/irqdomain.h>
25 #include <linux/irq.h>
26 #include <linux/kernel.h>
27 #include <linux/of_address.h>
28 #include <linux/of_clk.h>
29 #include <linux/of.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/pinctrl/pinconf-generic.h>
33 #include <linux/pinctrl/pinconf.h>
34 #include <linux/pinctrl/pinctrl.h>
35 #include <linux/platform_device.h>
36 #include <linux/pm_domain.h>
37 #include <linux/reboot.h>
38 #include <linux/reset.h>
39 #include <linux/seq_file.h>
40 #include <linux/slab.h>
41 #include <linux/spinlock.h>
42
43 #include <soc/tegra/common.h>
44 #include <soc/tegra/fuse.h>
45 #include <soc/tegra/pmc.h>
46
47 #include <dt-bindings/interrupt-controller/arm-gic.h>
48 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
49 #include <dt-bindings/gpio/tegra186-gpio.h>
50 #include <dt-bindings/gpio/tegra194-gpio.h>
51
52 #define PMC_CNTRL 0x0
53 #define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
54 #define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
55 #define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
56 #define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
57 #define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
58 #define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
59 #define PMC_CNTRL_MAIN_RST BIT(4)
60
61 #define DPD_SAMPLE 0x020
62 #define DPD_SAMPLE_ENABLE BIT(0)
63 #define DPD_SAMPLE_DISABLE (0 << 0)
64
65 #define PWRGATE_TOGGLE 0x30
66 #define PWRGATE_TOGGLE_START BIT(8)
67
68 #define REMOVE_CLAMPING 0x34
69
70 #define PWRGATE_STATUS 0x38
71
72 #define PMC_IMPL_E_33V_PWR 0x40
73
74 #define PMC_PWR_DET 0x48
75
76 #define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
77 #define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
78 #define PMC_SCRATCH0_MODE_RCM BIT(1)
79 #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
80 PMC_SCRATCH0_MODE_BOOTLOADER | \
81 PMC_SCRATCH0_MODE_RCM)
82
83 #define PMC_CPUPWRGOOD_TIMER 0xc8
84 #define PMC_CPUPWROFF_TIMER 0xcc
85
86 #define PMC_PWR_DET_VALUE 0xe4
87
88 #define PMC_SCRATCH41 0x140
89
90 #define PMC_SENSOR_CTRL 0x1b0
91 #define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
92 #define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
93
94 #define PMC_RST_STATUS_POR 0
95 #define PMC_RST_STATUS_WATCHDOG 1
96 #define PMC_RST_STATUS_SENSOR 2
97 #define PMC_RST_STATUS_SW_MAIN 3
98 #define PMC_RST_STATUS_LP0 4
99 #define PMC_RST_STATUS_AOTAG 5
100
101 #define IO_DPD_REQ 0x1b8
102 #define IO_DPD_REQ_CODE_IDLE (0U << 30)
103 #define IO_DPD_REQ_CODE_OFF (1U << 30)
104 #define IO_DPD_REQ_CODE_ON (2U << 30)
105 #define IO_DPD_REQ_CODE_MASK (3U << 30)
106
107 #define IO_DPD_STATUS 0x1bc
108 #define IO_DPD2_REQ 0x1c0
109 #define IO_DPD2_STATUS 0x1c4
110 #define SEL_DPD_TIM 0x1c8
111
112 #define PMC_SCRATCH54 0x258
113 #define PMC_SCRATCH54_DATA_SHIFT 8
114 #define PMC_SCRATCH54_ADDR_SHIFT 0
115
116 #define PMC_SCRATCH55 0x25c
117 #define PMC_SCRATCH55_RESET_TEGRA BIT(31)
118 #define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
119 #define PMC_SCRATCH55_PINMUX_SHIFT 24
120 #define PMC_SCRATCH55_16BITOP BIT(15)
121 #define PMC_SCRATCH55_CHECKSUM_SHIFT 16
122 #define PMC_SCRATCH55_I2CSLV1_SHIFT 0
123
124 #define GPU_RG_CNTRL 0x2d4
125
126 /* Tegra186 and later */
127 #define WAKE_AOWAKE_CNTRL(x) (0x000 + ((x) << 2))
128 #define WAKE_AOWAKE_CNTRL_LEVEL (1 << 3)
129 #define WAKE_AOWAKE_MASK_W(x) (0x180 + ((x) << 2))
130 #define WAKE_AOWAKE_MASK_R(x) (0x300 + ((x) << 2))
131 #define WAKE_AOWAKE_STATUS_W(x) (0x30c + ((x) << 2))
132 #define WAKE_AOWAKE_STATUS_R(x) (0x48c + ((x) << 2))
133 #define WAKE_AOWAKE_TIER0_ROUTING(x) (0x4b4 + ((x) << 2))
134 #define WAKE_AOWAKE_TIER1_ROUTING(x) (0x4c0 + ((x) << 2))
135 #define WAKE_AOWAKE_TIER2_ROUTING(x) (0x4cc + ((x) << 2))
136
137 #define WAKE_AOWAKE_CTRL 0x4f4
138 #define WAKE_AOWAKE_CTRL_INTR_POLARITY BIT(0)
139
140 /* for secure PMC */
141 #define TEGRA_SMC_PMC 0xc2fffe00
142 #define TEGRA_SMC_PMC_READ 0xaa
143 #define TEGRA_SMC_PMC_WRITE 0xbb
144
145 struct tegra_powergate {
146 struct generic_pm_domain genpd;
147 struct tegra_pmc *pmc;
148 unsigned int id;
149 struct clk **clks;
150 unsigned int num_clks;
151 struct reset_control *reset;
152 };
153
154 struct tegra_io_pad_soc {
155 enum tegra_io_pad id;
156 unsigned int dpd;
157 unsigned int voltage;
158 const char *name;
159 };
160
161 struct tegra_pmc_regs {
162 unsigned int scratch0;
163 unsigned int dpd_req;
164 unsigned int dpd_status;
165 unsigned int dpd2_req;
166 unsigned int dpd2_status;
167 unsigned int rst_status;
168 unsigned int rst_source_shift;
169 unsigned int rst_source_mask;
170 unsigned int rst_level_shift;
171 unsigned int rst_level_mask;
172 };
173
174 struct tegra_wake_event {
175 const char *name;
176 unsigned int id;
177 unsigned int irq;
178 struct {
179 unsigned int instance;
180 unsigned int pin;
181 } gpio;
182 };
183
184 #define TEGRA_WAKE_IRQ(_name, _id, _irq) \
185 { \
186 .name = _name, \
187 .id = _id, \
188 .irq = _irq, \
189 .gpio = { \
190 .instance = UINT_MAX, \
191 .pin = UINT_MAX, \
192 }, \
193 }
194
195 #define TEGRA_WAKE_GPIO(_name, _id, _instance, _pin) \
196 { \
197 .name = _name, \
198 .id = _id, \
199 .irq = 0, \
200 .gpio = { \
201 .instance = _instance, \
202 .pin = _pin, \
203 }, \
204 }
205
206 struct tegra_pmc_soc {
207 unsigned int num_powergates;
208 const char *const *powergates;
209 unsigned int num_cpu_powergates;
210 const u8 *cpu_powergates;
211
212 bool has_tsense_reset;
213 bool has_gpu_clamps;
214 bool needs_mbist_war;
215 bool has_impl_33v_pwr;
216 bool maybe_tz_only;
217
218 const struct tegra_io_pad_soc *io_pads;
219 unsigned int num_io_pads;
220
221 const struct pinctrl_pin_desc *pin_descs;
222 unsigned int num_pin_descs;
223
224 const struct tegra_pmc_regs *regs;
225 void (*init)(struct tegra_pmc *pmc);
226 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
227 struct device_node *np,
228 bool invert);
229
230 const char * const *reset_sources;
231 unsigned int num_reset_sources;
232 const char * const *reset_levels;
233 unsigned int num_reset_levels;
234
235 /*
236 * These describe events that can wake the system from sleep (i.e.
237 * LP0 or SC7). Wakeup from other sleep states (such as LP1 or LP2)
238 * are dealt with in the LIC.
239 */
240 const struct tegra_wake_event *wake_events;
241 unsigned int num_wake_events;
242 };
243
244 static const char * const tegra186_reset_sources[] = {
245 "SYS_RESET",
246 "AOWDT",
247 "MCCPLEXWDT",
248 "BPMPWDT",
249 "SCEWDT",
250 "SPEWDT",
251 "APEWDT",
252 "BCCPLEXWDT",
253 "SENSOR",
254 "AOTAG",
255 "VFSENSOR",
256 "SWREST",
257 "SC7",
258 "HSM",
259 "CORESIGHT"
260 };
261
262 static const char * const tegra186_reset_levels[] = {
263 "L0", "L1", "L2", "WARM"
264 };
265
266 static const char * const tegra30_reset_sources[] = {
267 "POWER_ON_RESET",
268 "WATCHDOG",
269 "SENSOR",
270 "SW_MAIN",
271 "LP0"
272 };
273
274 static const char * const tegra210_reset_sources[] = {
275 "POWER_ON_RESET",
276 "WATCHDOG",
277 "SENSOR",
278 "SW_MAIN",
279 "LP0",
280 "AOTAG"
281 };
282
283 /**
284 * struct tegra_pmc - NVIDIA Tegra PMC
285 * @dev: pointer to PMC device structure
286 * @base: pointer to I/O remapped register region
287 * @wake: pointer to I/O remapped region for WAKE registers
288 * @aotag: pointer to I/O remapped region for AOTAG registers
289 * @scratch: pointer to I/O remapped region for scratch registers
290 * @clk: pointer to pclk clock
291 * @soc: pointer to SoC data structure
292 * @tz_only: flag specifying if the PMC can only be accessed via TrustZone
293 * @debugfs: pointer to debugfs entry
294 * @rate: currently configured rate of pclk
295 * @suspend_mode: lowest suspend mode available
296 * @cpu_good_time: CPU power good time (in microseconds)
297 * @cpu_off_time: CPU power off time (in microsecends)
298 * @core_osc_time: core power good OSC time (in microseconds)
299 * @core_pmu_time: core power good PMU time (in microseconds)
300 * @core_off_time: core power off time (in microseconds)
301 * @corereq_high: core power request is active-high
302 * @sysclkreq_high: system clock request is active-high
303 * @combined_req: combined power request for CPU & core
304 * @cpu_pwr_good_en: CPU power good signal is enabled
305 * @lp0_vec_phys: physical base address of the LP0 warm boot code
306 * @lp0_vec_size: size of the LP0 warm boot code
307 * @powergates_available: Bitmap of available power gates
308 * @powergates_lock: mutex for power gate register access
309 * @pctl_dev: pin controller exposed by the PMC
310 * @domain: IRQ domain provided by the PMC
311 * @irq: chip implementation for the IRQ domain
312 */
313 struct tegra_pmc {
314 struct device *dev;
315 void __iomem *base;
316 void __iomem *wake;
317 void __iomem *aotag;
318 void __iomem *scratch;
319 struct clk *clk;
320 struct dentry *debugfs;
321
322 const struct tegra_pmc_soc *soc;
323 bool tz_only;
324
325 unsigned long rate;
326
327 enum tegra_suspend_mode suspend_mode;
328 u32 cpu_good_time;
329 u32 cpu_off_time;
330 u32 core_osc_time;
331 u32 core_pmu_time;
332 u32 core_off_time;
333 bool corereq_high;
334 bool sysclkreq_high;
335 bool combined_req;
336 bool cpu_pwr_good_en;
337 u32 lp0_vec_phys;
338 u32 lp0_vec_size;
339 DECLARE_BITMAP(powergates_available, TEGRA_POWERGATE_MAX);
340
341 struct mutex powergates_lock;
342
343 struct pinctrl_dev *pctl_dev;
344
345 struct irq_domain *domain;
346 struct irq_chip irq;
347 };
348
349 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
350 .base = NULL,
351 .suspend_mode = TEGRA_SUSPEND_NONE,
352 };
353
354 static inline struct tegra_powergate *
to_powergate(struct generic_pm_domain * domain)355 to_powergate(struct generic_pm_domain *domain)
356 {
357 return container_of(domain, struct tegra_powergate, genpd);
358 }
359
tegra_pmc_readl(struct tegra_pmc * pmc,unsigned long offset)360 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
361 {
362 struct arm_smccc_res res;
363
364 if (pmc->tz_only) {
365 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
366 0, 0, 0, &res);
367 if (res.a0) {
368 if (pmc->dev)
369 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
370 __func__, res.a0);
371 else
372 pr_warn("%s(): SMC failed: %lu\n", __func__,
373 res.a0);
374 }
375
376 return res.a1;
377 }
378
379 return readl(pmc->base + offset);
380 }
381
tegra_pmc_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)382 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
383 unsigned long offset)
384 {
385 struct arm_smccc_res res;
386
387 if (pmc->tz_only) {
388 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
389 value, 0, 0, 0, 0, &res);
390 if (res.a0) {
391 if (pmc->dev)
392 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
393 __func__, res.a0);
394 else
395 pr_warn("%s(): SMC failed: %lu\n", __func__,
396 res.a0);
397 }
398 } else {
399 writel(value, pmc->base + offset);
400 }
401 }
402
tegra_pmc_scratch_readl(struct tegra_pmc * pmc,unsigned long offset)403 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
404 {
405 if (pmc->tz_only)
406 return tegra_pmc_readl(pmc, offset);
407
408 return readl(pmc->scratch + offset);
409 }
410
tegra_pmc_scratch_writel(struct tegra_pmc * pmc,u32 value,unsigned long offset)411 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
412 unsigned long offset)
413 {
414 if (pmc->tz_only)
415 tegra_pmc_writel(pmc, value, offset);
416 else
417 writel(value, pmc->scratch + offset);
418 }
419
420 /*
421 * TODO Figure out a way to call this with the struct tegra_pmc * passed in.
422 * This currently doesn't work because readx_poll_timeout() can only operate
423 * on functions that take a single argument.
424 */
tegra_powergate_state(int id)425 static inline bool tegra_powergate_state(int id)
426 {
427 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
428 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
429 else
430 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
431 }
432
tegra_powergate_is_valid(struct tegra_pmc * pmc,int id)433 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
434 {
435 return (pmc->soc && pmc->soc->powergates[id]);
436 }
437
tegra_powergate_is_available(struct tegra_pmc * pmc,int id)438 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
439 {
440 return test_bit(id, pmc->powergates_available);
441 }
442
tegra_powergate_lookup(struct tegra_pmc * pmc,const char * name)443 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
444 {
445 unsigned int i;
446
447 if (!pmc || !pmc->soc || !name)
448 return -EINVAL;
449
450 for (i = 0; i < pmc->soc->num_powergates; i++) {
451 if (!tegra_powergate_is_valid(pmc, i))
452 continue;
453
454 if (!strcmp(name, pmc->soc->powergates[i]))
455 return i;
456 }
457
458 return -ENODEV;
459 }
460
461 /**
462 * tegra_powergate_set() - set the state of a partition
463 * @pmc: power management controller
464 * @id: partition ID
465 * @new_state: new state of the partition
466 */
tegra_powergate_set(struct tegra_pmc * pmc,unsigned int id,bool new_state)467 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
468 bool new_state)
469 {
470 bool status;
471 int err;
472
473 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
474 return -EINVAL;
475
476 mutex_lock(&pmc->powergates_lock);
477
478 if (tegra_powergate_state(id) == new_state) {
479 mutex_unlock(&pmc->powergates_lock);
480 return 0;
481 }
482
483 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
484
485 err = readx_poll_timeout(tegra_powergate_state, id, status,
486 status == new_state, 10, 100000);
487
488 mutex_unlock(&pmc->powergates_lock);
489
490 return err;
491 }
492
__tegra_powergate_remove_clamping(struct tegra_pmc * pmc,unsigned int id)493 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
494 unsigned int id)
495 {
496 u32 mask;
497
498 mutex_lock(&pmc->powergates_lock);
499
500 /*
501 * On Tegra124 and later, the clamps for the GPU are controlled by a
502 * separate register (with different semantics).
503 */
504 if (id == TEGRA_POWERGATE_3D) {
505 if (pmc->soc->has_gpu_clamps) {
506 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
507 goto out;
508 }
509 }
510
511 /*
512 * Tegra 2 has a bug where PCIE and VDE clamping masks are
513 * swapped relatively to the partition ids
514 */
515 if (id == TEGRA_POWERGATE_VDEC)
516 mask = (1 << TEGRA_POWERGATE_PCIE);
517 else if (id == TEGRA_POWERGATE_PCIE)
518 mask = (1 << TEGRA_POWERGATE_VDEC);
519 else
520 mask = (1 << id);
521
522 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
523
524 out:
525 mutex_unlock(&pmc->powergates_lock);
526
527 return 0;
528 }
529
tegra_powergate_disable_clocks(struct tegra_powergate * pg)530 static void tegra_powergate_disable_clocks(struct tegra_powergate *pg)
531 {
532 unsigned int i;
533
534 for (i = 0; i < pg->num_clks; i++)
535 clk_disable_unprepare(pg->clks[i]);
536 }
537
tegra_powergate_enable_clocks(struct tegra_powergate * pg)538 static int tegra_powergate_enable_clocks(struct tegra_powergate *pg)
539 {
540 unsigned int i;
541 int err;
542
543 for (i = 0; i < pg->num_clks; i++) {
544 err = clk_prepare_enable(pg->clks[i]);
545 if (err)
546 goto out;
547 }
548
549 return 0;
550
551 out:
552 while (i--)
553 clk_disable_unprepare(pg->clks[i]);
554
555 return err;
556 }
557
tegra210_clk_handle_mbist_war(unsigned int id)558 int __weak tegra210_clk_handle_mbist_war(unsigned int id)
559 {
560 return 0;
561 }
562
tegra_powergate_power_up(struct tegra_powergate * pg,bool disable_clocks)563 static int tegra_powergate_power_up(struct tegra_powergate *pg,
564 bool disable_clocks)
565 {
566 int err;
567
568 err = reset_control_assert(pg->reset);
569 if (err)
570 return err;
571
572 usleep_range(10, 20);
573
574 err = tegra_powergate_set(pg->pmc, pg->id, true);
575 if (err < 0)
576 return err;
577
578 usleep_range(10, 20);
579
580 err = tegra_powergate_enable_clocks(pg);
581 if (err)
582 goto disable_clks;
583
584 usleep_range(10, 20);
585
586 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
587 if (err)
588 goto disable_clks;
589
590 usleep_range(10, 20);
591
592 err = reset_control_deassert(pg->reset);
593 if (err)
594 goto powergate_off;
595
596 usleep_range(10, 20);
597
598 if (pg->pmc->soc->needs_mbist_war)
599 err = tegra210_clk_handle_mbist_war(pg->id);
600 if (err)
601 goto disable_clks;
602
603 if (disable_clocks)
604 tegra_powergate_disable_clocks(pg);
605
606 return 0;
607
608 disable_clks:
609 tegra_powergate_disable_clocks(pg);
610 usleep_range(10, 20);
611
612 powergate_off:
613 tegra_powergate_set(pg->pmc, pg->id, false);
614
615 return err;
616 }
617
tegra_powergate_power_down(struct tegra_powergate * pg)618 static int tegra_powergate_power_down(struct tegra_powergate *pg)
619 {
620 int err;
621
622 err = tegra_powergate_enable_clocks(pg);
623 if (err)
624 return err;
625
626 usleep_range(10, 20);
627
628 err = reset_control_assert(pg->reset);
629 if (err)
630 goto disable_clks;
631
632 usleep_range(10, 20);
633
634 tegra_powergate_disable_clocks(pg);
635
636 usleep_range(10, 20);
637
638 err = tegra_powergate_set(pg->pmc, pg->id, false);
639 if (err)
640 goto assert_resets;
641
642 return 0;
643
644 assert_resets:
645 tegra_powergate_enable_clocks(pg);
646 usleep_range(10, 20);
647 reset_control_deassert(pg->reset);
648 usleep_range(10, 20);
649
650 disable_clks:
651 tegra_powergate_disable_clocks(pg);
652
653 return err;
654 }
655
tegra_genpd_power_on(struct generic_pm_domain * domain)656 static int tegra_genpd_power_on(struct generic_pm_domain *domain)
657 {
658 struct tegra_powergate *pg = to_powergate(domain);
659 struct device *dev = pg->pmc->dev;
660 int err;
661
662 err = tegra_powergate_power_up(pg, true);
663 if (err) {
664 dev_err(dev, "failed to turn on PM domain %s: %d\n",
665 pg->genpd.name, err);
666 goto out;
667 }
668
669 reset_control_release(pg->reset);
670
671 out:
672 return err;
673 }
674
tegra_genpd_power_off(struct generic_pm_domain * domain)675 static int tegra_genpd_power_off(struct generic_pm_domain *domain)
676 {
677 struct tegra_powergate *pg = to_powergate(domain);
678 struct device *dev = pg->pmc->dev;
679 int err;
680
681 err = reset_control_acquire(pg->reset);
682 if (err < 0) {
683 pr_err("failed to acquire resets: %d\n", err);
684 return err;
685 }
686
687 err = tegra_powergate_power_down(pg);
688 if (err) {
689 dev_err(dev, "failed to turn off PM domain %s: %d\n",
690 pg->genpd.name, err);
691 reset_control_release(pg->reset);
692 }
693
694 return err;
695 }
696
697 /**
698 * tegra_powergate_power_on() - power on partition
699 * @id: partition ID
700 */
tegra_powergate_power_on(unsigned int id)701 int tegra_powergate_power_on(unsigned int id)
702 {
703 if (!tegra_powergate_is_available(pmc, id))
704 return -EINVAL;
705
706 return tegra_powergate_set(pmc, id, true);
707 }
708 EXPORT_SYMBOL(tegra_powergate_power_on);
709
710 /**
711 * tegra_powergate_power_off() - power off partition
712 * @id: partition ID
713 */
tegra_powergate_power_off(unsigned int id)714 int tegra_powergate_power_off(unsigned int id)
715 {
716 if (!tegra_powergate_is_available(pmc, id))
717 return -EINVAL;
718
719 return tegra_powergate_set(pmc, id, false);
720 }
721 EXPORT_SYMBOL(tegra_powergate_power_off);
722
723 /**
724 * tegra_powergate_is_powered() - check if partition is powered
725 * @pmc: power management controller
726 * @id: partition ID
727 */
tegra_powergate_is_powered(struct tegra_pmc * pmc,unsigned int id)728 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
729 {
730 if (!tegra_powergate_is_valid(pmc, id))
731 return -EINVAL;
732
733 return tegra_powergate_state(id);
734 }
735
736 /**
737 * tegra_powergate_remove_clamping() - remove power clamps for partition
738 * @id: partition ID
739 */
tegra_powergate_remove_clamping(unsigned int id)740 int tegra_powergate_remove_clamping(unsigned int id)
741 {
742 if (!tegra_powergate_is_available(pmc, id))
743 return -EINVAL;
744
745 return __tegra_powergate_remove_clamping(pmc, id);
746 }
747 EXPORT_SYMBOL(tegra_powergate_remove_clamping);
748
749 /**
750 * tegra_powergate_sequence_power_up() - power up partition
751 * @id: partition ID
752 * @clk: clock for partition
753 * @rst: reset for partition
754 *
755 * Must be called with clk disabled, and returns with clk enabled.
756 */
tegra_powergate_sequence_power_up(unsigned int id,struct clk * clk,struct reset_control * rst)757 int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
758 struct reset_control *rst)
759 {
760 struct tegra_powergate *pg;
761 int err;
762
763 if (!tegra_powergate_is_available(pmc, id))
764 return -EINVAL;
765
766 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
767 if (!pg)
768 return -ENOMEM;
769
770 pg->id = id;
771 pg->clks = &clk;
772 pg->num_clks = 1;
773 pg->reset = rst;
774 pg->pmc = pmc;
775
776 err = tegra_powergate_power_up(pg, false);
777 if (err)
778 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
779 err);
780
781 kfree(pg);
782
783 return err;
784 }
785 EXPORT_SYMBOL(tegra_powergate_sequence_power_up);
786
787 /**
788 * tegra_get_cpu_powergate_id() - convert from CPU ID to partition ID
789 * @pmc: power management controller
790 * @cpuid: CPU partition ID
791 *
792 * Returns the partition ID corresponding to the CPU partition ID or a
793 * negative error code on failure.
794 */
tegra_get_cpu_powergate_id(struct tegra_pmc * pmc,unsigned int cpuid)795 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
796 unsigned int cpuid)
797 {
798 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
799 return pmc->soc->cpu_powergates[cpuid];
800
801 return -EINVAL;
802 }
803
804 /**
805 * tegra_pmc_cpu_is_powered() - check if CPU partition is powered
806 * @cpuid: CPU partition ID
807 */
tegra_pmc_cpu_is_powered(unsigned int cpuid)808 bool tegra_pmc_cpu_is_powered(unsigned int cpuid)
809 {
810 int id;
811
812 id = tegra_get_cpu_powergate_id(pmc, cpuid);
813 if (id < 0)
814 return false;
815
816 return tegra_powergate_is_powered(pmc, id);
817 }
818
819 /**
820 * tegra_pmc_cpu_power_on() - power on CPU partition
821 * @cpuid: CPU partition ID
822 */
tegra_pmc_cpu_power_on(unsigned int cpuid)823 int tegra_pmc_cpu_power_on(unsigned int cpuid)
824 {
825 int id;
826
827 id = tegra_get_cpu_powergate_id(pmc, cpuid);
828 if (id < 0)
829 return id;
830
831 return tegra_powergate_set(pmc, id, true);
832 }
833
834 /**
835 * tegra_pmc_cpu_remove_clamping() - remove power clamps for CPU partition
836 * @cpuid: CPU partition ID
837 */
tegra_pmc_cpu_remove_clamping(unsigned int cpuid)838 int tegra_pmc_cpu_remove_clamping(unsigned int cpuid)
839 {
840 int id;
841
842 id = tegra_get_cpu_powergate_id(pmc, cpuid);
843 if (id < 0)
844 return id;
845
846 return tegra_powergate_remove_clamping(id);
847 }
848
tegra_pmc_restart_notify(struct notifier_block * this,unsigned long action,void * data)849 static int tegra_pmc_restart_notify(struct notifier_block *this,
850 unsigned long action, void *data)
851 {
852 const char *cmd = data;
853 u32 value;
854
855 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
856 value &= ~PMC_SCRATCH0_MODE_MASK;
857
858 if (cmd) {
859 if (strcmp(cmd, "recovery") == 0)
860 value |= PMC_SCRATCH0_MODE_RECOVERY;
861
862 if (strcmp(cmd, "bootloader") == 0)
863 value |= PMC_SCRATCH0_MODE_BOOTLOADER;
864
865 if (strcmp(cmd, "forced-recovery") == 0)
866 value |= PMC_SCRATCH0_MODE_RCM;
867 }
868
869 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
870
871 /* reset everything but PMC_SCRATCH0 and PMC_RST_STATUS */
872 value = tegra_pmc_readl(pmc, PMC_CNTRL);
873 value |= PMC_CNTRL_MAIN_RST;
874 tegra_pmc_writel(pmc, value, PMC_CNTRL);
875
876 return NOTIFY_DONE;
877 }
878
879 static struct notifier_block tegra_pmc_restart_handler = {
880 .notifier_call = tegra_pmc_restart_notify,
881 .priority = 128,
882 };
883
powergate_show(struct seq_file * s,void * data)884 static int powergate_show(struct seq_file *s, void *data)
885 {
886 unsigned int i;
887 int status;
888
889 seq_printf(s, " powergate powered\n");
890 seq_printf(s, "------------------\n");
891
892 for (i = 0; i < pmc->soc->num_powergates; i++) {
893 status = tegra_powergate_is_powered(pmc, i);
894 if (status < 0)
895 continue;
896
897 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
898 status ? "yes" : "no");
899 }
900
901 return 0;
902 }
903
904 DEFINE_SHOW_ATTRIBUTE(powergate);
905
tegra_powergate_debugfs_init(void)906 static int tegra_powergate_debugfs_init(void)
907 {
908 pmc->debugfs = debugfs_create_file("powergate", S_IRUGO, NULL, NULL,
909 &powergate_fops);
910 if (!pmc->debugfs)
911 return -ENOMEM;
912
913 return 0;
914 }
915
tegra_powergate_of_get_clks(struct tegra_powergate * pg,struct device_node * np)916 static int tegra_powergate_of_get_clks(struct tegra_powergate *pg,
917 struct device_node *np)
918 {
919 struct clk *clk;
920 unsigned int i, count;
921 int err;
922
923 count = of_clk_get_parent_count(np);
924 if (count == 0)
925 return -ENODEV;
926
927 pg->clks = kcalloc(count, sizeof(clk), GFP_KERNEL);
928 if (!pg->clks)
929 return -ENOMEM;
930
931 for (i = 0; i < count; i++) {
932 pg->clks[i] = of_clk_get(np, i);
933 if (IS_ERR(pg->clks[i])) {
934 err = PTR_ERR(pg->clks[i]);
935 goto err;
936 }
937 }
938
939 pg->num_clks = count;
940
941 return 0;
942
943 err:
944 while (i--)
945 clk_put(pg->clks[i]);
946
947 kfree(pg->clks);
948
949 return err;
950 }
951
tegra_powergate_of_get_resets(struct tegra_powergate * pg,struct device_node * np,bool off)952 static int tegra_powergate_of_get_resets(struct tegra_powergate *pg,
953 struct device_node *np, bool off)
954 {
955 struct device *dev = pg->pmc->dev;
956 int err;
957
958 pg->reset = of_reset_control_array_get_exclusive_released(np);
959 if (IS_ERR(pg->reset)) {
960 err = PTR_ERR(pg->reset);
961 dev_err(dev, "failed to get device resets: %d\n", err);
962 return err;
963 }
964
965 err = reset_control_acquire(pg->reset);
966 if (err < 0) {
967 pr_err("failed to acquire resets: %d\n", err);
968 goto out;
969 }
970
971 if (off) {
972 err = reset_control_assert(pg->reset);
973 } else {
974 err = reset_control_deassert(pg->reset);
975 if (err < 0)
976 goto out;
977
978 reset_control_release(pg->reset);
979 }
980
981 out:
982 if (err) {
983 reset_control_release(pg->reset);
984 reset_control_put(pg->reset);
985 }
986
987 return err;
988 }
989
tegra_powergate_add(struct tegra_pmc * pmc,struct device_node * np)990 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
991 {
992 struct device *dev = pmc->dev;
993 struct tegra_powergate *pg;
994 int id, err = 0;
995 bool off;
996
997 pg = kzalloc(sizeof(*pg), GFP_KERNEL);
998 if (!pg)
999 return -ENOMEM;
1000
1001 id = tegra_powergate_lookup(pmc, np->name);
1002 if (id < 0) {
1003 dev_err(dev, "powergate lookup failed for %pOFn: %d\n", np, id);
1004 err = -ENODEV;
1005 goto free_mem;
1006 }
1007
1008 /*
1009 * Clear the bit for this powergate so it cannot be managed
1010 * directly via the legacy APIs for controlling powergates.
1011 */
1012 clear_bit(id, pmc->powergates_available);
1013
1014 pg->id = id;
1015 pg->genpd.name = np->name;
1016 pg->genpd.power_off = tegra_genpd_power_off;
1017 pg->genpd.power_on = tegra_genpd_power_on;
1018 pg->pmc = pmc;
1019
1020 off = !tegra_powergate_is_powered(pmc, pg->id);
1021
1022 err = tegra_powergate_of_get_clks(pg, np);
1023 if (err < 0) {
1024 dev_err(dev, "failed to get clocks for %pOFn: %d\n", np, err);
1025 goto set_available;
1026 }
1027
1028 err = tegra_powergate_of_get_resets(pg, np, off);
1029 if (err < 0) {
1030 dev_err(dev, "failed to get resets for %pOFn: %d\n", np, err);
1031 goto remove_clks;
1032 }
1033
1034 if (!IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
1035 if (off)
1036 WARN_ON(tegra_powergate_power_up(pg, true));
1037
1038 goto remove_resets;
1039 }
1040
1041 err = pm_genpd_init(&pg->genpd, NULL, off);
1042 if (err < 0) {
1043 dev_err(dev, "failed to initialise PM domain %pOFn: %d\n", np,
1044 err);
1045 goto remove_resets;
1046 }
1047
1048 err = of_genpd_add_provider_simple(np, &pg->genpd);
1049 if (err < 0) {
1050 dev_err(dev, "failed to add PM domain provider for %pOFn: %d\n",
1051 np, err);
1052 goto remove_genpd;
1053 }
1054
1055 dev_dbg(dev, "added PM domain %s\n", pg->genpd.name);
1056
1057 return 0;
1058
1059 remove_genpd:
1060 pm_genpd_remove(&pg->genpd);
1061
1062 remove_resets:
1063 reset_control_put(pg->reset);
1064
1065 remove_clks:
1066 while (pg->num_clks--)
1067 clk_put(pg->clks[pg->num_clks]);
1068
1069 kfree(pg->clks);
1070
1071 set_available:
1072 set_bit(id, pmc->powergates_available);
1073
1074 free_mem:
1075 kfree(pg);
1076
1077 return err;
1078 }
1079
tegra_powergate_init(struct tegra_pmc * pmc,struct device_node * parent)1080 static int tegra_powergate_init(struct tegra_pmc *pmc,
1081 struct device_node *parent)
1082 {
1083 struct device_node *np, *child;
1084 int err = 0;
1085
1086 np = of_get_child_by_name(parent, "powergates");
1087 if (!np)
1088 return 0;
1089
1090 for_each_child_of_node(np, child) {
1091 err = tegra_powergate_add(pmc, child);
1092 if (err < 0) {
1093 of_node_put(child);
1094 break;
1095 }
1096 }
1097
1098 of_node_put(np);
1099
1100 return err;
1101 }
1102
tegra_powergate_remove(struct generic_pm_domain * genpd)1103 static void tegra_powergate_remove(struct generic_pm_domain *genpd)
1104 {
1105 struct tegra_powergate *pg = to_powergate(genpd);
1106
1107 reset_control_put(pg->reset);
1108
1109 while (pg->num_clks--)
1110 clk_put(pg->clks[pg->num_clks]);
1111
1112 kfree(pg->clks);
1113
1114 set_bit(pg->id, pmc->powergates_available);
1115
1116 kfree(pg);
1117 }
1118
tegra_powergate_remove_all(struct device_node * parent)1119 static void tegra_powergate_remove_all(struct device_node *parent)
1120 {
1121 struct generic_pm_domain *genpd;
1122 struct device_node *np, *child;
1123
1124 np = of_get_child_by_name(parent, "powergates");
1125 if (!np)
1126 return;
1127
1128 for_each_child_of_node(np, child) {
1129 of_genpd_del_provider(child);
1130
1131 genpd = of_genpd_remove_last(child);
1132 if (IS_ERR(genpd))
1133 continue;
1134
1135 tegra_powergate_remove(genpd);
1136 }
1137
1138 of_node_put(np);
1139 }
1140
1141 static const struct tegra_io_pad_soc *
tegra_io_pad_find(struct tegra_pmc * pmc,enum tegra_io_pad id)1142 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1143 {
1144 unsigned int i;
1145
1146 for (i = 0; i < pmc->soc->num_io_pads; i++)
1147 if (pmc->soc->io_pads[i].id == id)
1148 return &pmc->soc->io_pads[i];
1149
1150 return NULL;
1151 }
1152
tegra_io_pad_get_dpd_register_bit(struct tegra_pmc * pmc,enum tegra_io_pad id,unsigned long * request,unsigned long * status,u32 * mask)1153 static int tegra_io_pad_get_dpd_register_bit(struct tegra_pmc *pmc,
1154 enum tegra_io_pad id,
1155 unsigned long *request,
1156 unsigned long *status,
1157 u32 *mask)
1158 {
1159 const struct tegra_io_pad_soc *pad;
1160
1161 pad = tegra_io_pad_find(pmc, id);
1162 if (!pad) {
1163 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1164 return -ENOENT;
1165 }
1166
1167 if (pad->dpd == UINT_MAX)
1168 return -ENOTSUPP;
1169
1170 *mask = BIT(pad->dpd % 32);
1171
1172 if (pad->dpd < 32) {
1173 *status = pmc->soc->regs->dpd_status;
1174 *request = pmc->soc->regs->dpd_req;
1175 } else {
1176 *status = pmc->soc->regs->dpd2_status;
1177 *request = pmc->soc->regs->dpd2_req;
1178 }
1179
1180 return 0;
1181 }
1182
tegra_io_pad_prepare(struct tegra_pmc * pmc,enum tegra_io_pad id,unsigned long * request,unsigned long * status,u32 * mask)1183 static int tegra_io_pad_prepare(struct tegra_pmc *pmc, enum tegra_io_pad id,
1184 unsigned long *request, unsigned long *status,
1185 u32 *mask)
1186 {
1187 unsigned long rate, value;
1188 int err;
1189
1190 err = tegra_io_pad_get_dpd_register_bit(pmc, id, request, status, mask);
1191 if (err)
1192 return err;
1193
1194 if (pmc->clk) {
1195 rate = clk_get_rate(pmc->clk);
1196 if (!rate) {
1197 dev_err(pmc->dev, "failed to get clock rate\n");
1198 return -ENODEV;
1199 }
1200
1201 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1202
1203 /* must be at least 200 ns, in APB (PCLK) clock cycles */
1204 value = DIV_ROUND_UP(1000000000, rate);
1205 value = DIV_ROUND_UP(200, value);
1206 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1207 }
1208
1209 return 0;
1210 }
1211
tegra_io_pad_poll(struct tegra_pmc * pmc,unsigned long offset,u32 mask,u32 val,unsigned long timeout)1212 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1213 u32 mask, u32 val, unsigned long timeout)
1214 {
1215 u32 value;
1216
1217 timeout = jiffies + msecs_to_jiffies(timeout);
1218
1219 while (time_after(timeout, jiffies)) {
1220 value = tegra_pmc_readl(pmc, offset);
1221 if ((value & mask) == val)
1222 return 0;
1223
1224 usleep_range(250, 1000);
1225 }
1226
1227 return -ETIMEDOUT;
1228 }
1229
tegra_io_pad_unprepare(struct tegra_pmc * pmc)1230 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1231 {
1232 if (pmc->clk)
1233 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1234 }
1235
1236 /**
1237 * tegra_io_pad_power_enable() - enable power to I/O pad
1238 * @id: Tegra I/O pad ID for which to enable power
1239 *
1240 * Returns: 0 on success or a negative error code on failure.
1241 */
tegra_io_pad_power_enable(enum tegra_io_pad id)1242 int tegra_io_pad_power_enable(enum tegra_io_pad id)
1243 {
1244 unsigned long request, status;
1245 u32 mask;
1246 int err;
1247
1248 mutex_lock(&pmc->powergates_lock);
1249
1250 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1251 if (err < 0) {
1252 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1253 goto unlock;
1254 }
1255
1256 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1257
1258 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1259 if (err < 0) {
1260 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1261 goto unlock;
1262 }
1263
1264 tegra_io_pad_unprepare(pmc);
1265
1266 unlock:
1267 mutex_unlock(&pmc->powergates_lock);
1268 return err;
1269 }
1270 EXPORT_SYMBOL(tegra_io_pad_power_enable);
1271
1272 /**
1273 * tegra_io_pad_power_disable() - disable power to I/O pad
1274 * @id: Tegra I/O pad ID for which to disable power
1275 *
1276 * Returns: 0 on success or a negative error code on failure.
1277 */
tegra_io_pad_power_disable(enum tegra_io_pad id)1278 int tegra_io_pad_power_disable(enum tegra_io_pad id)
1279 {
1280 unsigned long request, status;
1281 u32 mask;
1282 int err;
1283
1284 mutex_lock(&pmc->powergates_lock);
1285
1286 err = tegra_io_pad_prepare(pmc, id, &request, &status, &mask);
1287 if (err < 0) {
1288 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1289 goto unlock;
1290 }
1291
1292 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1293
1294 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1295 if (err < 0) {
1296 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1297 goto unlock;
1298 }
1299
1300 tegra_io_pad_unprepare(pmc);
1301
1302 unlock:
1303 mutex_unlock(&pmc->powergates_lock);
1304 return err;
1305 }
1306 EXPORT_SYMBOL(tegra_io_pad_power_disable);
1307
tegra_io_pad_is_powered(struct tegra_pmc * pmc,enum tegra_io_pad id)1308 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1309 {
1310 unsigned long request, status;
1311 u32 mask, value;
1312 int err;
1313
1314 err = tegra_io_pad_get_dpd_register_bit(pmc, id, &request, &status,
1315 &mask);
1316 if (err)
1317 return err;
1318
1319 value = tegra_pmc_readl(pmc, status);
1320
1321 return !(value & mask);
1322 }
1323
tegra_io_pad_set_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id,int voltage)1324 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1325 int voltage)
1326 {
1327 const struct tegra_io_pad_soc *pad;
1328 u32 value;
1329
1330 pad = tegra_io_pad_find(pmc, id);
1331 if (!pad)
1332 return -ENOENT;
1333
1334 if (pad->voltage == UINT_MAX)
1335 return -ENOTSUPP;
1336
1337 mutex_lock(&pmc->powergates_lock);
1338
1339 if (pmc->soc->has_impl_33v_pwr) {
1340 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1341
1342 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1343 value &= ~BIT(pad->voltage);
1344 else
1345 value |= BIT(pad->voltage);
1346
1347 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1348 } else {
1349 /* write-enable PMC_PWR_DET_VALUE[pad->voltage] */
1350 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1351 value |= BIT(pad->voltage);
1352 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1353
1354 /* update I/O voltage */
1355 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1356
1357 if (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)
1358 value &= ~BIT(pad->voltage);
1359 else
1360 value |= BIT(pad->voltage);
1361
1362 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1363 }
1364
1365 mutex_unlock(&pmc->powergates_lock);
1366
1367 usleep_range(100, 250);
1368
1369 return 0;
1370 }
1371
tegra_io_pad_get_voltage(struct tegra_pmc * pmc,enum tegra_io_pad id)1372 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1373 {
1374 const struct tegra_io_pad_soc *pad;
1375 u32 value;
1376
1377 pad = tegra_io_pad_find(pmc, id);
1378 if (!pad)
1379 return -ENOENT;
1380
1381 if (pad->voltage == UINT_MAX)
1382 return -ENOTSUPP;
1383
1384 if (pmc->soc->has_impl_33v_pwr)
1385 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1386 else
1387 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1388
1389 if ((value & BIT(pad->voltage)) == 0)
1390 return TEGRA_IO_PAD_VOLTAGE_1V8;
1391
1392 return TEGRA_IO_PAD_VOLTAGE_3V3;
1393 }
1394
1395 /**
1396 * tegra_io_rail_power_on() - enable power to I/O rail
1397 * @id: Tegra I/O pad ID for which to enable power
1398 *
1399 * See also: tegra_io_pad_power_enable()
1400 */
tegra_io_rail_power_on(unsigned int id)1401 int tegra_io_rail_power_on(unsigned int id)
1402 {
1403 return tegra_io_pad_power_enable(id);
1404 }
1405 EXPORT_SYMBOL(tegra_io_rail_power_on);
1406
1407 /**
1408 * tegra_io_rail_power_off() - disable power to I/O rail
1409 * @id: Tegra I/O pad ID for which to disable power
1410 *
1411 * See also: tegra_io_pad_power_disable()
1412 */
tegra_io_rail_power_off(unsigned int id)1413 int tegra_io_rail_power_off(unsigned int id)
1414 {
1415 return tegra_io_pad_power_disable(id);
1416 }
1417 EXPORT_SYMBOL(tegra_io_rail_power_off);
1418
1419 #ifdef CONFIG_PM_SLEEP
tegra_pmc_get_suspend_mode(void)1420 enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void)
1421 {
1422 return pmc->suspend_mode;
1423 }
1424
tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)1425 void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode)
1426 {
1427 if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE)
1428 return;
1429
1430 pmc->suspend_mode = mode;
1431 }
1432
tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)1433 void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode)
1434 {
1435 unsigned long long rate = 0;
1436 u32 value;
1437
1438 switch (mode) {
1439 case TEGRA_SUSPEND_LP1:
1440 rate = 32768;
1441 break;
1442
1443 case TEGRA_SUSPEND_LP2:
1444 rate = clk_get_rate(pmc->clk);
1445 break;
1446
1447 default:
1448 break;
1449 }
1450
1451 if (WARN_ON_ONCE(rate == 0))
1452 rate = 100000000;
1453
1454 if (rate != pmc->rate) {
1455 u64 ticks;
1456
1457 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1458 do_div(ticks, USEC_PER_SEC);
1459 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1460
1461 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1462 do_div(ticks, USEC_PER_SEC);
1463 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1464
1465 wmb();
1466
1467 pmc->rate = rate;
1468 }
1469
1470 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1471 value &= ~PMC_CNTRL_SIDE_EFFECT_LP0;
1472 value |= PMC_CNTRL_CPU_PWRREQ_OE;
1473 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1474 }
1475 #endif
1476
tegra_pmc_parse_dt(struct tegra_pmc * pmc,struct device_node * np)1477 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1478 {
1479 u32 value, values[2];
1480
1481 if (of_property_read_u32(np, "nvidia,suspend-mode", &value)) {
1482 } else {
1483 switch (value) {
1484 case 0:
1485 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1486 break;
1487
1488 case 1:
1489 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1490 break;
1491
1492 case 2:
1493 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1494 break;
1495
1496 default:
1497 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1498 break;
1499 }
1500 }
1501
1502 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1503
1504 if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &value))
1505 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1506
1507 pmc->cpu_good_time = value;
1508
1509 if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &value))
1510 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1511
1512 pmc->cpu_off_time = value;
1513
1514 if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time",
1515 values, ARRAY_SIZE(values)))
1516 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1517
1518 pmc->core_osc_time = values[0];
1519 pmc->core_pmu_time = values[1];
1520
1521 if (of_property_read_u32(np, "nvidia,core-pwr-off-time", &value))
1522 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1523
1524 pmc->core_off_time = value;
1525
1526 pmc->corereq_high = of_property_read_bool(np,
1527 "nvidia,core-power-req-active-high");
1528
1529 pmc->sysclkreq_high = of_property_read_bool(np,
1530 "nvidia,sys-clock-req-active-high");
1531
1532 pmc->combined_req = of_property_read_bool(np,
1533 "nvidia,combined-power-req");
1534
1535 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1536 "nvidia,cpu-pwr-good-en");
1537
1538 if (of_property_read_u32_array(np, "nvidia,lp0-vec", values,
1539 ARRAY_SIZE(values)))
1540 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1541 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1542
1543 pmc->lp0_vec_phys = values[0];
1544 pmc->lp0_vec_size = values[1];
1545
1546 return 0;
1547 }
1548
tegra_pmc_init(struct tegra_pmc * pmc)1549 static void tegra_pmc_init(struct tegra_pmc *pmc)
1550 {
1551 if (pmc->soc->init)
1552 pmc->soc->init(pmc);
1553 }
1554
tegra_pmc_init_tsense_reset(struct tegra_pmc * pmc)1555 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1556 {
1557 static const char disabled[] = "emergency thermal reset disabled";
1558 u32 pmu_addr, ctrl_id, reg_addr, reg_data, pinmux;
1559 struct device *dev = pmc->dev;
1560 struct device_node *np;
1561 u32 value, checksum;
1562
1563 if (!pmc->soc->has_tsense_reset)
1564 return;
1565
1566 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
1567 if (!np) {
1568 dev_warn(dev, "i2c-thermtrip node not found, %s.\n", disabled);
1569 return;
1570 }
1571
1572 if (of_property_read_u32(np, "nvidia,i2c-controller-id", &ctrl_id)) {
1573 dev_err(dev, "I2C controller ID missing, %s.\n", disabled);
1574 goto out;
1575 }
1576
1577 if (of_property_read_u32(np, "nvidia,bus-addr", &pmu_addr)) {
1578 dev_err(dev, "nvidia,bus-addr missing, %s.\n", disabled);
1579 goto out;
1580 }
1581
1582 if (of_property_read_u32(np, "nvidia,reg-addr", ®_addr)) {
1583 dev_err(dev, "nvidia,reg-addr missing, %s.\n", disabled);
1584 goto out;
1585 }
1586
1587 if (of_property_read_u32(np, "nvidia,reg-data", ®_data)) {
1588 dev_err(dev, "nvidia,reg-data missing, %s.\n", disabled);
1589 goto out;
1590 }
1591
1592 if (of_property_read_u32(np, "nvidia,pinmux-id", &pinmux))
1593 pinmux = 0;
1594
1595 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1596 value |= PMC_SENSOR_CTRL_SCRATCH_WRITE;
1597 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1598
1599 value = (reg_data << PMC_SCRATCH54_DATA_SHIFT) |
1600 (reg_addr << PMC_SCRATCH54_ADDR_SHIFT);
1601 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
1602
1603 value = PMC_SCRATCH55_RESET_TEGRA;
1604 value |= ctrl_id << PMC_SCRATCH55_CNTRL_ID_SHIFT;
1605 value |= pinmux << PMC_SCRATCH55_PINMUX_SHIFT;
1606 value |= pmu_addr << PMC_SCRATCH55_I2CSLV1_SHIFT;
1607
1608 /*
1609 * Calculate checksum of SCRATCH54, SCRATCH55 fields. Bits 23:16 will
1610 * contain the checksum and are currently zero, so they are not added.
1611 */
1612 checksum = reg_addr + reg_data + (value & 0xff) + ((value >> 8) & 0xff)
1613 + ((value >> 24) & 0xff);
1614 checksum &= 0xff;
1615 checksum = 0x100 - checksum;
1616
1617 value |= checksum << PMC_SCRATCH55_CHECKSUM_SHIFT;
1618
1619 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
1620
1621 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
1622 value |= PMC_SENSOR_CTRL_ENABLE_RST;
1623 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
1624
1625 dev_info(pmc->dev, "emergency thermal reset enabled\n");
1626
1627 out:
1628 of_node_put(np);
1629 }
1630
tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev * pctl_dev)1631 static int tegra_io_pad_pinctrl_get_groups_count(struct pinctrl_dev *pctl_dev)
1632 {
1633 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1634
1635 return pmc->soc->num_io_pads;
1636 }
1637
tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev * pctl,unsigned int group)1638 static const char *tegra_io_pad_pinctrl_get_group_name(struct pinctrl_dev *pctl,
1639 unsigned int group)
1640 {
1641 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
1642
1643 return pmc->soc->io_pads[group].name;
1644 }
1645
tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev * pctl_dev,unsigned int group,const unsigned int ** pins,unsigned int * num_pins)1646 static int tegra_io_pad_pinctrl_get_group_pins(struct pinctrl_dev *pctl_dev,
1647 unsigned int group,
1648 const unsigned int **pins,
1649 unsigned int *num_pins)
1650 {
1651 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1652
1653 *pins = &pmc->soc->io_pads[group].id;
1654 *num_pins = 1;
1655
1656 return 0;
1657 }
1658
1659 static const struct pinctrl_ops tegra_io_pad_pinctrl_ops = {
1660 .get_groups_count = tegra_io_pad_pinctrl_get_groups_count,
1661 .get_group_name = tegra_io_pad_pinctrl_get_group_name,
1662 .get_group_pins = tegra_io_pad_pinctrl_get_group_pins,
1663 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1664 .dt_free_map = pinconf_generic_dt_free_map,
1665 };
1666
tegra_io_pad_pinconf_get(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * config)1667 static int tegra_io_pad_pinconf_get(struct pinctrl_dev *pctl_dev,
1668 unsigned int pin, unsigned long *config)
1669 {
1670 enum pin_config_param param = pinconf_to_config_param(*config);
1671 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1672 const struct tegra_io_pad_soc *pad;
1673 int ret;
1674 u32 arg;
1675
1676 pad = tegra_io_pad_find(pmc, pin);
1677 if (!pad)
1678 return -EINVAL;
1679
1680 switch (param) {
1681 case PIN_CONFIG_POWER_SOURCE:
1682 ret = tegra_io_pad_get_voltage(pmc, pad->id);
1683 if (ret < 0)
1684 return ret;
1685
1686 arg = ret;
1687 break;
1688
1689 case PIN_CONFIG_LOW_POWER_MODE:
1690 ret = tegra_io_pad_is_powered(pmc, pad->id);
1691 if (ret < 0)
1692 return ret;
1693
1694 arg = !ret;
1695 break;
1696
1697 default:
1698 return -EINVAL;
1699 }
1700
1701 *config = pinconf_to_config_packed(param, arg);
1702
1703 return 0;
1704 }
1705
tegra_io_pad_pinconf_set(struct pinctrl_dev * pctl_dev,unsigned int pin,unsigned long * configs,unsigned int num_configs)1706 static int tegra_io_pad_pinconf_set(struct pinctrl_dev *pctl_dev,
1707 unsigned int pin, unsigned long *configs,
1708 unsigned int num_configs)
1709 {
1710 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
1711 const struct tegra_io_pad_soc *pad;
1712 enum pin_config_param param;
1713 unsigned int i;
1714 int err;
1715 u32 arg;
1716
1717 pad = tegra_io_pad_find(pmc, pin);
1718 if (!pad)
1719 return -EINVAL;
1720
1721 for (i = 0; i < num_configs; ++i) {
1722 param = pinconf_to_config_param(configs[i]);
1723 arg = pinconf_to_config_argument(configs[i]);
1724
1725 switch (param) {
1726 case PIN_CONFIG_LOW_POWER_MODE:
1727 if (arg)
1728 err = tegra_io_pad_power_disable(pad->id);
1729 else
1730 err = tegra_io_pad_power_enable(pad->id);
1731 if (err)
1732 return err;
1733 break;
1734 case PIN_CONFIG_POWER_SOURCE:
1735 if (arg != TEGRA_IO_PAD_VOLTAGE_1V8 &&
1736 arg != TEGRA_IO_PAD_VOLTAGE_3V3)
1737 return -EINVAL;
1738 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
1739 if (err)
1740 return err;
1741 break;
1742 default:
1743 return -EINVAL;
1744 }
1745 }
1746
1747 return 0;
1748 }
1749
1750 static const struct pinconf_ops tegra_io_pad_pinconf_ops = {
1751 .pin_config_get = tegra_io_pad_pinconf_get,
1752 .pin_config_set = tegra_io_pad_pinconf_set,
1753 .is_generic = true,
1754 };
1755
1756 static struct pinctrl_desc tegra_pmc_pctl_desc = {
1757 .pctlops = &tegra_io_pad_pinctrl_ops,
1758 .confops = &tegra_io_pad_pinconf_ops,
1759 };
1760
tegra_pmc_pinctrl_init(struct tegra_pmc * pmc)1761 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
1762 {
1763 int err;
1764
1765 if (!pmc->soc->num_pin_descs)
1766 return 0;
1767
1768 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
1769 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
1770 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
1771
1772 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
1773 pmc);
1774 if (IS_ERR(pmc->pctl_dev)) {
1775 err = PTR_ERR(pmc->pctl_dev);
1776 dev_err(pmc->dev, "failed to register pin controller: %d\n",
1777 err);
1778 return err;
1779 }
1780
1781 return 0;
1782 }
1783
reset_reason_show(struct device * dev,struct device_attribute * attr,char * buf)1784 static ssize_t reset_reason_show(struct device *dev,
1785 struct device_attribute *attr, char *buf)
1786 {
1787 u32 value;
1788
1789 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1790 value &= pmc->soc->regs->rst_source_mask;
1791 value >>= pmc->soc->regs->rst_source_shift;
1792
1793 if (WARN_ON(value >= pmc->soc->num_reset_sources))
1794 return sprintf(buf, "%s\n", "UNKNOWN");
1795
1796 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
1797 }
1798
1799 static DEVICE_ATTR_RO(reset_reason);
1800
reset_level_show(struct device * dev,struct device_attribute * attr,char * buf)1801 static ssize_t reset_level_show(struct device *dev,
1802 struct device_attribute *attr, char *buf)
1803 {
1804 u32 value;
1805
1806 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
1807 value &= pmc->soc->regs->rst_level_mask;
1808 value >>= pmc->soc->regs->rst_level_shift;
1809
1810 if (WARN_ON(value >= pmc->soc->num_reset_levels))
1811 return sprintf(buf, "%s\n", "UNKNOWN");
1812
1813 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
1814 }
1815
1816 static DEVICE_ATTR_RO(reset_level);
1817
tegra_pmc_reset_sysfs_init(struct tegra_pmc * pmc)1818 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
1819 {
1820 struct device *dev = pmc->dev;
1821 int err = 0;
1822
1823 if (pmc->soc->reset_sources) {
1824 err = device_create_file(dev, &dev_attr_reset_reason);
1825 if (err < 0)
1826 dev_warn(dev,
1827 "failed to create attr \"reset_reason\": %d\n",
1828 err);
1829 }
1830
1831 if (pmc->soc->reset_levels) {
1832 err = device_create_file(dev, &dev_attr_reset_level);
1833 if (err < 0)
1834 dev_warn(dev,
1835 "failed to create attr \"reset_level\": %d\n",
1836 err);
1837 }
1838 }
1839
tegra_pmc_irq_translate(struct irq_domain * domain,struct irq_fwspec * fwspec,unsigned long * hwirq,unsigned int * type)1840 static int tegra_pmc_irq_translate(struct irq_domain *domain,
1841 struct irq_fwspec *fwspec,
1842 unsigned long *hwirq,
1843 unsigned int *type)
1844 {
1845 if (WARN_ON(fwspec->param_count < 2))
1846 return -EINVAL;
1847
1848 *hwirq = fwspec->param[0];
1849 *type = fwspec->param[1];
1850
1851 return 0;
1852 }
1853
tegra_pmc_irq_alloc(struct irq_domain * domain,unsigned int virq,unsigned int num_irqs,void * data)1854 static int tegra_pmc_irq_alloc(struct irq_domain *domain, unsigned int virq,
1855 unsigned int num_irqs, void *data)
1856 {
1857 struct tegra_pmc *pmc = domain->host_data;
1858 const struct tegra_pmc_soc *soc = pmc->soc;
1859 struct irq_fwspec *fwspec = data;
1860 unsigned int i;
1861 int err = 0;
1862
1863 if (WARN_ON(num_irqs > 1))
1864 return -EINVAL;
1865
1866 for (i = 0; i < soc->num_wake_events; i++) {
1867 const struct tegra_wake_event *event = &soc->wake_events[i];
1868
1869 if (fwspec->param_count == 2) {
1870 struct irq_fwspec spec;
1871
1872 if (event->id != fwspec->param[0])
1873 continue;
1874
1875 err = irq_domain_set_hwirq_and_chip(domain, virq,
1876 event->id,
1877 &pmc->irq, pmc);
1878 if (err < 0)
1879 break;
1880
1881 spec.fwnode = &pmc->dev->of_node->fwnode;
1882 spec.param_count = 3;
1883 spec.param[0] = GIC_SPI;
1884 spec.param[1] = event->irq;
1885 spec.param[2] = fwspec->param[1];
1886
1887 err = irq_domain_alloc_irqs_parent(domain, virq,
1888 num_irqs, &spec);
1889
1890 break;
1891 }
1892
1893 if (fwspec->param_count == 3) {
1894 if (event->gpio.instance != fwspec->param[0] ||
1895 event->gpio.pin != fwspec->param[1])
1896 continue;
1897
1898 err = irq_domain_set_hwirq_and_chip(domain, virq,
1899 event->id,
1900 &pmc->irq, pmc);
1901
1902 break;
1903 }
1904 }
1905
1906 /*
1907 * For interrupts that don't have associated wake events, assign a
1908 * dummy hardware IRQ number. This is used in the ->irq_set_type()
1909 * and ->irq_set_wake() callbacks to return early for these IRQs.
1910 */
1911 if (i == soc->num_wake_events)
1912 err = irq_domain_set_hwirq_and_chip(domain, virq, ULONG_MAX,
1913 &pmc->irq, pmc);
1914
1915 return err;
1916 }
1917
1918 static const struct irq_domain_ops tegra_pmc_irq_domain_ops = {
1919 .translate = tegra_pmc_irq_translate,
1920 .alloc = tegra_pmc_irq_alloc,
1921 };
1922
tegra_pmc_irq_set_wake(struct irq_data * data,unsigned int on)1923 static int tegra_pmc_irq_set_wake(struct irq_data *data, unsigned int on)
1924 {
1925 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1926 unsigned int offset, bit;
1927 u32 value;
1928
1929 /* nothing to do if there's no associated wake event */
1930 if (WARN_ON(data->hwirq == ULONG_MAX))
1931 return 0;
1932
1933 offset = data->hwirq / 32;
1934 bit = data->hwirq % 32;
1935
1936 /* clear wake status */
1937 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
1938
1939 /* route wake to tier 2 */
1940 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
1941
1942 if (!on)
1943 value &= ~(1 << bit);
1944 else
1945 value |= 1 << bit;
1946
1947 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
1948
1949 /* enable wakeup event */
1950 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
1951
1952 return 0;
1953 }
1954
tegra_pmc_irq_set_type(struct irq_data * data,unsigned int type)1955 static int tegra_pmc_irq_set_type(struct irq_data *data, unsigned int type)
1956 {
1957 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
1958 u32 value;
1959
1960 /* nothing to do if there's no associated wake event */
1961 if (data->hwirq == ULONG_MAX)
1962 return 0;
1963
1964 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
1965
1966 switch (type) {
1967 case IRQ_TYPE_EDGE_RISING:
1968 case IRQ_TYPE_LEVEL_HIGH:
1969 value |= WAKE_AOWAKE_CNTRL_LEVEL;
1970 break;
1971
1972 case IRQ_TYPE_EDGE_FALLING:
1973 case IRQ_TYPE_LEVEL_LOW:
1974 value &= ~WAKE_AOWAKE_CNTRL_LEVEL;
1975 break;
1976
1977 case IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING:
1978 value ^= WAKE_AOWAKE_CNTRL_LEVEL;
1979 break;
1980
1981 default:
1982 return -EINVAL;
1983 }
1984
1985 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
1986
1987 return 0;
1988 }
1989
tegra_pmc_irq_init(struct tegra_pmc * pmc)1990 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
1991 {
1992 struct irq_domain *parent = NULL;
1993 struct device_node *np;
1994
1995 np = of_irq_find_parent(pmc->dev->of_node);
1996 if (np) {
1997 parent = irq_find_host(np);
1998 of_node_put(np);
1999 }
2000
2001 if (!parent)
2002 return 0;
2003
2004 pmc->irq.name = dev_name(pmc->dev);
2005 pmc->irq.irq_mask = irq_chip_mask_parent;
2006 pmc->irq.irq_unmask = irq_chip_unmask_parent;
2007 pmc->irq.irq_eoi = irq_chip_eoi_parent;
2008 pmc->irq.irq_set_affinity = irq_chip_set_affinity_parent;
2009 pmc->irq.irq_set_type = tegra_pmc_irq_set_type;
2010 pmc->irq.irq_set_wake = tegra_pmc_irq_set_wake;
2011
2012 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2013 &tegra_pmc_irq_domain_ops, pmc);
2014 if (!pmc->domain) {
2015 dev_err(pmc->dev, "failed to allocate domain\n");
2016 return -ENOMEM;
2017 }
2018
2019 return 0;
2020 }
2021
tegra_pmc_probe(struct platform_device * pdev)2022 static int tegra_pmc_probe(struct platform_device *pdev)
2023 {
2024 void __iomem *base;
2025 struct resource *res;
2026 int err;
2027
2028 /*
2029 * Early initialisation should have configured an initial
2030 * register mapping and setup the soc data pointer. If these
2031 * are not valid then something went badly wrong!
2032 */
2033 if (WARN_ON(!pmc->base || !pmc->soc))
2034 return -ENODEV;
2035
2036 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2037 if (err < 0)
2038 return err;
2039
2040 /* take over the memory region from the early initialization */
2041 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2042 base = devm_ioremap_resource(&pdev->dev, res);
2043 if (IS_ERR(base))
2044 return PTR_ERR(base);
2045
2046 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "wake");
2047 if (res) {
2048 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2049 if (IS_ERR(pmc->wake))
2050 return PTR_ERR(pmc->wake);
2051 } else {
2052 pmc->wake = base;
2053 }
2054
2055 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "aotag");
2056 if (res) {
2057 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2058 if (IS_ERR(pmc->aotag))
2059 return PTR_ERR(pmc->aotag);
2060 } else {
2061 pmc->aotag = base;
2062 }
2063
2064 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "scratch");
2065 if (res) {
2066 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2067 if (IS_ERR(pmc->scratch))
2068 return PTR_ERR(pmc->scratch);
2069 } else {
2070 pmc->scratch = base;
2071 }
2072
2073 pmc->clk = devm_clk_get(&pdev->dev, "pclk");
2074 if (IS_ERR(pmc->clk)) {
2075 err = PTR_ERR(pmc->clk);
2076
2077 if (err != -ENOENT) {
2078 dev_err(&pdev->dev, "failed to get pclk: %d\n", err);
2079 return err;
2080 }
2081
2082 pmc->clk = NULL;
2083 }
2084
2085 pmc->dev = &pdev->dev;
2086
2087 tegra_pmc_init(pmc);
2088
2089 tegra_pmc_init_tsense_reset(pmc);
2090
2091 tegra_pmc_reset_sysfs_init(pmc);
2092
2093 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2094 err = tegra_powergate_debugfs_init();
2095 if (err < 0)
2096 goto cleanup_sysfs;
2097 }
2098
2099 err = register_restart_handler(&tegra_pmc_restart_handler);
2100 if (err) {
2101 dev_err(&pdev->dev, "unable to register restart handler, %d\n",
2102 err);
2103 goto cleanup_debugfs;
2104 }
2105
2106 err = tegra_pmc_pinctrl_init(pmc);
2107 if (err)
2108 goto cleanup_restart_handler;
2109
2110 err = tegra_powergate_init(pmc, pdev->dev.of_node);
2111 if (err < 0)
2112 goto cleanup_powergates;
2113
2114 err = tegra_pmc_irq_init(pmc);
2115 if (err < 0)
2116 goto cleanup_powergates;
2117
2118 mutex_lock(&pmc->powergates_lock);
2119 iounmap(pmc->base);
2120 pmc->base = base;
2121 mutex_unlock(&pmc->powergates_lock);
2122
2123 platform_set_drvdata(pdev, pmc);
2124
2125 return 0;
2126
2127 cleanup_powergates:
2128 tegra_powergate_remove_all(pdev->dev.of_node);
2129 cleanup_restart_handler:
2130 unregister_restart_handler(&tegra_pmc_restart_handler);
2131 cleanup_debugfs:
2132 debugfs_remove(pmc->debugfs);
2133 cleanup_sysfs:
2134 device_remove_file(&pdev->dev, &dev_attr_reset_reason);
2135 device_remove_file(&pdev->dev, &dev_attr_reset_level);
2136 return err;
2137 }
2138
2139 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
tegra_pmc_suspend(struct device * dev)2140 static int tegra_pmc_suspend(struct device *dev)
2141 {
2142 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2143
2144 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
2145
2146 return 0;
2147 }
2148
tegra_pmc_resume(struct device * dev)2149 static int tegra_pmc_resume(struct device *dev)
2150 {
2151 struct tegra_pmc *pmc = dev_get_drvdata(dev);
2152
2153 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
2154
2155 return 0;
2156 }
2157
2158 static SIMPLE_DEV_PM_OPS(tegra_pmc_pm_ops, tegra_pmc_suspend, tegra_pmc_resume);
2159
2160 #endif
2161
2162 static const char * const tegra20_powergates[] = {
2163 [TEGRA_POWERGATE_CPU] = "cpu",
2164 [TEGRA_POWERGATE_3D] = "3d",
2165 [TEGRA_POWERGATE_VENC] = "venc",
2166 [TEGRA_POWERGATE_VDEC] = "vdec",
2167 [TEGRA_POWERGATE_PCIE] = "pcie",
2168 [TEGRA_POWERGATE_L2] = "l2",
2169 [TEGRA_POWERGATE_MPE] = "mpe",
2170 };
2171
2172 static const struct tegra_pmc_regs tegra20_pmc_regs = {
2173 .scratch0 = 0x50,
2174 .dpd_req = 0x1b8,
2175 .dpd_status = 0x1bc,
2176 .dpd2_req = 0x1c0,
2177 .dpd2_status = 0x1c4,
2178 .rst_status = 0x1b4,
2179 .rst_source_shift = 0x0,
2180 .rst_source_mask = 0x7,
2181 .rst_level_shift = 0x0,
2182 .rst_level_mask = 0x0,
2183 };
2184
tegra20_pmc_init(struct tegra_pmc * pmc)2185 static void tegra20_pmc_init(struct tegra_pmc *pmc)
2186 {
2187 u32 value;
2188
2189 /* Always enable CPU power request */
2190 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2191 value |= PMC_CNTRL_CPU_PWRREQ_OE;
2192 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2193
2194 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2195
2196 if (pmc->sysclkreq_high)
2197 value &= ~PMC_CNTRL_SYSCLK_POLARITY;
2198 else
2199 value |= PMC_CNTRL_SYSCLK_POLARITY;
2200
2201 /* configure the output polarity while the request is tristated */
2202 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2203
2204 /* now enable the request */
2205 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2206 value |= PMC_CNTRL_SYSCLK_OE;
2207 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2208 }
2209
tegra20_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)2210 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2211 struct device_node *np,
2212 bool invert)
2213 {
2214 u32 value;
2215
2216 value = tegra_pmc_readl(pmc, PMC_CNTRL);
2217
2218 if (invert)
2219 value |= PMC_CNTRL_INTR_POLARITY;
2220 else
2221 value &= ~PMC_CNTRL_INTR_POLARITY;
2222
2223 tegra_pmc_writel(pmc, value, PMC_CNTRL);
2224 }
2225
2226 static const struct tegra_pmc_soc tegra20_pmc_soc = {
2227 .num_powergates = ARRAY_SIZE(tegra20_powergates),
2228 .powergates = tegra20_powergates,
2229 .num_cpu_powergates = 0,
2230 .cpu_powergates = NULL,
2231 .has_tsense_reset = false,
2232 .has_gpu_clamps = false,
2233 .needs_mbist_war = false,
2234 .has_impl_33v_pwr = false,
2235 .maybe_tz_only = false,
2236 .num_io_pads = 0,
2237 .io_pads = NULL,
2238 .num_pin_descs = 0,
2239 .pin_descs = NULL,
2240 .regs = &tegra20_pmc_regs,
2241 .init = tegra20_pmc_init,
2242 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2243 .reset_sources = NULL,
2244 .num_reset_sources = 0,
2245 .reset_levels = NULL,
2246 .num_reset_levels = 0,
2247 };
2248
2249 static const char * const tegra30_powergates[] = {
2250 [TEGRA_POWERGATE_CPU] = "cpu0",
2251 [TEGRA_POWERGATE_3D] = "3d0",
2252 [TEGRA_POWERGATE_VENC] = "venc",
2253 [TEGRA_POWERGATE_VDEC] = "vdec",
2254 [TEGRA_POWERGATE_PCIE] = "pcie",
2255 [TEGRA_POWERGATE_L2] = "l2",
2256 [TEGRA_POWERGATE_MPE] = "mpe",
2257 [TEGRA_POWERGATE_HEG] = "heg",
2258 [TEGRA_POWERGATE_SATA] = "sata",
2259 [TEGRA_POWERGATE_CPU1] = "cpu1",
2260 [TEGRA_POWERGATE_CPU2] = "cpu2",
2261 [TEGRA_POWERGATE_CPU3] = "cpu3",
2262 [TEGRA_POWERGATE_CELP] = "celp",
2263 [TEGRA_POWERGATE_3D1] = "3d1",
2264 };
2265
2266 static const u8 tegra30_cpu_powergates[] = {
2267 TEGRA_POWERGATE_CPU,
2268 TEGRA_POWERGATE_CPU1,
2269 TEGRA_POWERGATE_CPU2,
2270 TEGRA_POWERGATE_CPU3,
2271 };
2272
2273 static const struct tegra_pmc_soc tegra30_pmc_soc = {
2274 .num_powergates = ARRAY_SIZE(tegra30_powergates),
2275 .powergates = tegra30_powergates,
2276 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
2277 .cpu_powergates = tegra30_cpu_powergates,
2278 .has_tsense_reset = true,
2279 .has_gpu_clamps = false,
2280 .needs_mbist_war = false,
2281 .has_impl_33v_pwr = false,
2282 .maybe_tz_only = false,
2283 .num_io_pads = 0,
2284 .io_pads = NULL,
2285 .num_pin_descs = 0,
2286 .pin_descs = NULL,
2287 .regs = &tegra20_pmc_regs,
2288 .init = tegra20_pmc_init,
2289 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2290 .reset_sources = tegra30_reset_sources,
2291 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2292 .reset_levels = NULL,
2293 .num_reset_levels = 0,
2294 };
2295
2296 static const char * const tegra114_powergates[] = {
2297 [TEGRA_POWERGATE_CPU] = "crail",
2298 [TEGRA_POWERGATE_3D] = "3d",
2299 [TEGRA_POWERGATE_VENC] = "venc",
2300 [TEGRA_POWERGATE_VDEC] = "vdec",
2301 [TEGRA_POWERGATE_MPE] = "mpe",
2302 [TEGRA_POWERGATE_HEG] = "heg",
2303 [TEGRA_POWERGATE_CPU1] = "cpu1",
2304 [TEGRA_POWERGATE_CPU2] = "cpu2",
2305 [TEGRA_POWERGATE_CPU3] = "cpu3",
2306 [TEGRA_POWERGATE_CELP] = "celp",
2307 [TEGRA_POWERGATE_CPU0] = "cpu0",
2308 [TEGRA_POWERGATE_C0NC] = "c0nc",
2309 [TEGRA_POWERGATE_C1NC] = "c1nc",
2310 [TEGRA_POWERGATE_DIS] = "dis",
2311 [TEGRA_POWERGATE_DISB] = "disb",
2312 [TEGRA_POWERGATE_XUSBA] = "xusba",
2313 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2314 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2315 };
2316
2317 static const u8 tegra114_cpu_powergates[] = {
2318 TEGRA_POWERGATE_CPU0,
2319 TEGRA_POWERGATE_CPU1,
2320 TEGRA_POWERGATE_CPU2,
2321 TEGRA_POWERGATE_CPU3,
2322 };
2323
2324 static const struct tegra_pmc_soc tegra114_pmc_soc = {
2325 .num_powergates = ARRAY_SIZE(tegra114_powergates),
2326 .powergates = tegra114_powergates,
2327 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
2328 .cpu_powergates = tegra114_cpu_powergates,
2329 .has_tsense_reset = true,
2330 .has_gpu_clamps = false,
2331 .needs_mbist_war = false,
2332 .has_impl_33v_pwr = false,
2333 .maybe_tz_only = false,
2334 .num_io_pads = 0,
2335 .io_pads = NULL,
2336 .num_pin_descs = 0,
2337 .pin_descs = NULL,
2338 .regs = &tegra20_pmc_regs,
2339 .init = tegra20_pmc_init,
2340 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2341 .reset_sources = tegra30_reset_sources,
2342 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2343 .reset_levels = NULL,
2344 .num_reset_levels = 0,
2345 };
2346
2347 static const char * const tegra124_powergates[] = {
2348 [TEGRA_POWERGATE_CPU] = "crail",
2349 [TEGRA_POWERGATE_3D] = "3d",
2350 [TEGRA_POWERGATE_VENC] = "venc",
2351 [TEGRA_POWERGATE_PCIE] = "pcie",
2352 [TEGRA_POWERGATE_VDEC] = "vdec",
2353 [TEGRA_POWERGATE_MPE] = "mpe",
2354 [TEGRA_POWERGATE_HEG] = "heg",
2355 [TEGRA_POWERGATE_SATA] = "sata",
2356 [TEGRA_POWERGATE_CPU1] = "cpu1",
2357 [TEGRA_POWERGATE_CPU2] = "cpu2",
2358 [TEGRA_POWERGATE_CPU3] = "cpu3",
2359 [TEGRA_POWERGATE_CELP] = "celp",
2360 [TEGRA_POWERGATE_CPU0] = "cpu0",
2361 [TEGRA_POWERGATE_C0NC] = "c0nc",
2362 [TEGRA_POWERGATE_C1NC] = "c1nc",
2363 [TEGRA_POWERGATE_SOR] = "sor",
2364 [TEGRA_POWERGATE_DIS] = "dis",
2365 [TEGRA_POWERGATE_DISB] = "disb",
2366 [TEGRA_POWERGATE_XUSBA] = "xusba",
2367 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2368 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2369 [TEGRA_POWERGATE_VIC] = "vic",
2370 [TEGRA_POWERGATE_IRAM] = "iram",
2371 };
2372
2373 static const u8 tegra124_cpu_powergates[] = {
2374 TEGRA_POWERGATE_CPU0,
2375 TEGRA_POWERGATE_CPU1,
2376 TEGRA_POWERGATE_CPU2,
2377 TEGRA_POWERGATE_CPU3,
2378 };
2379
2380 #define TEGRA_IO_PAD(_id, _dpd, _voltage, _name) \
2381 ((struct tegra_io_pad_soc) { \
2382 .id = (_id), \
2383 .dpd = (_dpd), \
2384 .voltage = (_voltage), \
2385 .name = (_name), \
2386 })
2387
2388 #define TEGRA_IO_PIN_DESC(_id, _dpd, _voltage, _name) \
2389 ((struct pinctrl_pin_desc) { \
2390 .number = (_id), \
2391 .name = (_name) \
2392 })
2393
2394 #define TEGRA124_IO_PAD_TABLE(_pad) \
2395 /* .id .dpd .voltage .name */ \
2396 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2397 _pad(TEGRA_IO_PAD_BB, 15, UINT_MAX, "bb"), \
2398 _pad(TEGRA_IO_PAD_CAM, 36, UINT_MAX, "cam"), \
2399 _pad(TEGRA_IO_PAD_COMP, 22, UINT_MAX, "comp"), \
2400 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2401 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csb"), \
2402 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "cse"), \
2403 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2404 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2405 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2406 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2407 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2408 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2409 _pad(TEGRA_IO_PAD_HV, 38, UINT_MAX, "hv"), \
2410 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2411 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2412 _pad(TEGRA_IO_PAD_NAND, 13, UINT_MAX, "nand"), \
2413 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2414 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2415 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2416 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2417 _pad(TEGRA_IO_PAD_SDMMC1, 33, UINT_MAX, "sdmmc1"), \
2418 _pad(TEGRA_IO_PAD_SDMMC3, 34, UINT_MAX, "sdmmc3"), \
2419 _pad(TEGRA_IO_PAD_SDMMC4, 35, UINT_MAX, "sdmmc4"), \
2420 _pad(TEGRA_IO_PAD_SYS_DDC, 58, UINT_MAX, "sys_ddc"), \
2421 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2422 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2423 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2424 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2425 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb_bias")
2426
2427 static const struct tegra_io_pad_soc tegra124_io_pads[] = {
2428 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PAD)
2429 };
2430
2431 static const struct pinctrl_pin_desc tegra124_pin_descs[] = {
2432 TEGRA124_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2433 };
2434
2435 static const struct tegra_pmc_soc tegra124_pmc_soc = {
2436 .num_powergates = ARRAY_SIZE(tegra124_powergates),
2437 .powergates = tegra124_powergates,
2438 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
2439 .cpu_powergates = tegra124_cpu_powergates,
2440 .has_tsense_reset = true,
2441 .has_gpu_clamps = true,
2442 .needs_mbist_war = false,
2443 .has_impl_33v_pwr = false,
2444 .maybe_tz_only = false,
2445 .num_io_pads = ARRAY_SIZE(tegra124_io_pads),
2446 .io_pads = tegra124_io_pads,
2447 .num_pin_descs = ARRAY_SIZE(tegra124_pin_descs),
2448 .pin_descs = tegra124_pin_descs,
2449 .regs = &tegra20_pmc_regs,
2450 .init = tegra20_pmc_init,
2451 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2452 .reset_sources = tegra30_reset_sources,
2453 .num_reset_sources = ARRAY_SIZE(tegra30_reset_sources),
2454 .reset_levels = NULL,
2455 .num_reset_levels = 0,
2456 };
2457
2458 static const char * const tegra210_powergates[] = {
2459 [TEGRA_POWERGATE_CPU] = "crail",
2460 [TEGRA_POWERGATE_3D] = "3d",
2461 [TEGRA_POWERGATE_VENC] = "venc",
2462 [TEGRA_POWERGATE_PCIE] = "pcie",
2463 [TEGRA_POWERGATE_MPE] = "mpe",
2464 [TEGRA_POWERGATE_SATA] = "sata",
2465 [TEGRA_POWERGATE_CPU1] = "cpu1",
2466 [TEGRA_POWERGATE_CPU2] = "cpu2",
2467 [TEGRA_POWERGATE_CPU3] = "cpu3",
2468 [TEGRA_POWERGATE_CPU0] = "cpu0",
2469 [TEGRA_POWERGATE_C0NC] = "c0nc",
2470 [TEGRA_POWERGATE_SOR] = "sor",
2471 [TEGRA_POWERGATE_DIS] = "dis",
2472 [TEGRA_POWERGATE_DISB] = "disb",
2473 [TEGRA_POWERGATE_XUSBA] = "xusba",
2474 [TEGRA_POWERGATE_XUSBB] = "xusbb",
2475 [TEGRA_POWERGATE_XUSBC] = "xusbc",
2476 [TEGRA_POWERGATE_VIC] = "vic",
2477 [TEGRA_POWERGATE_IRAM] = "iram",
2478 [TEGRA_POWERGATE_NVDEC] = "nvdec",
2479 [TEGRA_POWERGATE_NVJPG] = "nvjpg",
2480 [TEGRA_POWERGATE_AUD] = "aud",
2481 [TEGRA_POWERGATE_DFD] = "dfd",
2482 [TEGRA_POWERGATE_VE2] = "ve2",
2483 };
2484
2485 static const u8 tegra210_cpu_powergates[] = {
2486 TEGRA_POWERGATE_CPU0,
2487 TEGRA_POWERGATE_CPU1,
2488 TEGRA_POWERGATE_CPU2,
2489 TEGRA_POWERGATE_CPU3,
2490 };
2491
2492 #define TEGRA210_IO_PAD_TABLE(_pad) \
2493 /* .id .dpd .voltage .name */ \
2494 _pad(TEGRA_IO_PAD_AUDIO, 17, 5, "audio"), \
2495 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 18, "audio-hv"), \
2496 _pad(TEGRA_IO_PAD_CAM, 36, 10, "cam"), \
2497 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2498 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2499 _pad(TEGRA_IO_PAD_CSIC, 42, UINT_MAX, "csic"), \
2500 _pad(TEGRA_IO_PAD_CSID, 43, UINT_MAX, "csid"), \
2501 _pad(TEGRA_IO_PAD_CSIE, 44, UINT_MAX, "csie"), \
2502 _pad(TEGRA_IO_PAD_CSIF, 45, UINT_MAX, "csif"), \
2503 _pad(TEGRA_IO_PAD_DBG, 25, 19, "dbg"), \
2504 _pad(TEGRA_IO_PAD_DEBUG_NONAO, 26, UINT_MAX, "debug-nonao"), \
2505 _pad(TEGRA_IO_PAD_DMIC, 50, 20, "dmic"), \
2506 _pad(TEGRA_IO_PAD_DP, 51, UINT_MAX, "dp"), \
2507 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2508 _pad(TEGRA_IO_PAD_DSIB, 39, UINT_MAX, "dsib"), \
2509 _pad(TEGRA_IO_PAD_DSIC, 40, UINT_MAX, "dsic"), \
2510 _pad(TEGRA_IO_PAD_DSID, 41, UINT_MAX, "dsid"), \
2511 _pad(TEGRA_IO_PAD_EMMC, 35, UINT_MAX, "emmc"), \
2512 _pad(TEGRA_IO_PAD_EMMC2, 37, UINT_MAX, "emmc2"), \
2513 _pad(TEGRA_IO_PAD_GPIO, 27, 21, "gpio"), \
2514 _pad(TEGRA_IO_PAD_HDMI, 28, UINT_MAX, "hdmi"), \
2515 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2516 _pad(TEGRA_IO_PAD_LVDS, 57, UINT_MAX, "lvds"), \
2517 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2518 _pad(TEGRA_IO_PAD_PEX_BIAS, 4, UINT_MAX, "pex-bias"), \
2519 _pad(TEGRA_IO_PAD_PEX_CLK1, 5, UINT_MAX, "pex-clk1"), \
2520 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2521 _pad(TEGRA_IO_PAD_PEX_CNTRL, UINT_MAX, 11, "pex-cntrl"), \
2522 _pad(TEGRA_IO_PAD_SDMMC1, 33, 12, "sdmmc1"), \
2523 _pad(TEGRA_IO_PAD_SDMMC3, 34, 13, "sdmmc3"), \
2524 _pad(TEGRA_IO_PAD_SPI, 46, 22, "spi"), \
2525 _pad(TEGRA_IO_PAD_SPI_HV, 47, 23, "spi-hv"), \
2526 _pad(TEGRA_IO_PAD_UART, 14, 2, "uart"), \
2527 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2528 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2529 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2530 _pad(TEGRA_IO_PAD_USB3, 18, UINT_MAX, "usb3"), \
2531 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias")
2532
2533 static const struct tegra_io_pad_soc tegra210_io_pads[] = {
2534 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PAD)
2535 };
2536
2537 static const struct pinctrl_pin_desc tegra210_pin_descs[] = {
2538 TEGRA210_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2539 };
2540
2541 static const struct tegra_pmc_soc tegra210_pmc_soc = {
2542 .num_powergates = ARRAY_SIZE(tegra210_powergates),
2543 .powergates = tegra210_powergates,
2544 .num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
2545 .cpu_powergates = tegra210_cpu_powergates,
2546 .has_tsense_reset = true,
2547 .has_gpu_clamps = true,
2548 .needs_mbist_war = true,
2549 .has_impl_33v_pwr = false,
2550 .maybe_tz_only = true,
2551 .num_io_pads = ARRAY_SIZE(tegra210_io_pads),
2552 .io_pads = tegra210_io_pads,
2553 .num_pin_descs = ARRAY_SIZE(tegra210_pin_descs),
2554 .pin_descs = tegra210_pin_descs,
2555 .regs = &tegra20_pmc_regs,
2556 .init = tegra20_pmc_init,
2557 .setup_irq_polarity = tegra20_pmc_setup_irq_polarity,
2558 .reset_sources = tegra210_reset_sources,
2559 .num_reset_sources = ARRAY_SIZE(tegra210_reset_sources),
2560 .reset_levels = NULL,
2561 .num_reset_levels = 0,
2562 };
2563
2564 #define TEGRA186_IO_PAD_TABLE(_pad) \
2565 /* .id .dpd .voltage .name */ \
2566 _pad(TEGRA_IO_PAD_CSIA, 0, UINT_MAX, "csia"), \
2567 _pad(TEGRA_IO_PAD_CSIB, 1, UINT_MAX, "csib"), \
2568 _pad(TEGRA_IO_PAD_DSI, 2, UINT_MAX, "dsi"), \
2569 _pad(TEGRA_IO_PAD_MIPI_BIAS, 3, UINT_MAX, "mipi-bias"), \
2570 _pad(TEGRA_IO_PAD_PEX_CLK_BIAS, 4, UINT_MAX, "pex-clk-bias"), \
2571 _pad(TEGRA_IO_PAD_PEX_CLK3, 5, UINT_MAX, "pex-clk3"), \
2572 _pad(TEGRA_IO_PAD_PEX_CLK2, 6, UINT_MAX, "pex-clk2"), \
2573 _pad(TEGRA_IO_PAD_PEX_CLK1, 7, UINT_MAX, "pex-clk1"), \
2574 _pad(TEGRA_IO_PAD_USB0, 9, UINT_MAX, "usb0"), \
2575 _pad(TEGRA_IO_PAD_USB1, 10, UINT_MAX, "usb1"), \
2576 _pad(TEGRA_IO_PAD_USB2, 11, UINT_MAX, "usb2"), \
2577 _pad(TEGRA_IO_PAD_USB_BIAS, 12, UINT_MAX, "usb-bias"), \
2578 _pad(TEGRA_IO_PAD_UART, 14, UINT_MAX, "uart"), \
2579 _pad(TEGRA_IO_PAD_AUDIO, 17, UINT_MAX, "audio"), \
2580 _pad(TEGRA_IO_PAD_HSIC, 19, UINT_MAX, "hsic"), \
2581 _pad(TEGRA_IO_PAD_DBG, 25, UINT_MAX, "dbg"), \
2582 _pad(TEGRA_IO_PAD_HDMI_DP0, 28, UINT_MAX, "hdmi-dp0"), \
2583 _pad(TEGRA_IO_PAD_HDMI_DP1, 29, UINT_MAX, "hdmi-dp1"), \
2584 _pad(TEGRA_IO_PAD_PEX_CNTRL, 32, UINT_MAX, "pex-cntrl"), \
2585 _pad(TEGRA_IO_PAD_SDMMC2_HV, 34, 5, "sdmmc2-hv"), \
2586 _pad(TEGRA_IO_PAD_SDMMC4, 36, UINT_MAX, "sdmmc4"), \
2587 _pad(TEGRA_IO_PAD_CAM, 38, UINT_MAX, "cam"), \
2588 _pad(TEGRA_IO_PAD_DSIB, 40, UINT_MAX, "dsib"), \
2589 _pad(TEGRA_IO_PAD_DSIC, 41, UINT_MAX, "dsic"), \
2590 _pad(TEGRA_IO_PAD_DSID, 42, UINT_MAX, "dsid"), \
2591 _pad(TEGRA_IO_PAD_CSIC, 43, UINT_MAX, "csic"), \
2592 _pad(TEGRA_IO_PAD_CSID, 44, UINT_MAX, "csid"), \
2593 _pad(TEGRA_IO_PAD_CSIE, 45, UINT_MAX, "csie"), \
2594 _pad(TEGRA_IO_PAD_CSIF, 46, UINT_MAX, "csif"), \
2595 _pad(TEGRA_IO_PAD_SPI, 47, UINT_MAX, "spi"), \
2596 _pad(TEGRA_IO_PAD_UFS, 49, UINT_MAX, "ufs"), \
2597 _pad(TEGRA_IO_PAD_DMIC_HV, 52, 2, "dmic-hv"), \
2598 _pad(TEGRA_IO_PAD_EDP, 53, UINT_MAX, "edp"), \
2599 _pad(TEGRA_IO_PAD_SDMMC1_HV, 55, 4, "sdmmc1-hv"), \
2600 _pad(TEGRA_IO_PAD_SDMMC3_HV, 56, 6, "sdmmc3-hv"), \
2601 _pad(TEGRA_IO_PAD_CONN, 60, UINT_MAX, "conn"), \
2602 _pad(TEGRA_IO_PAD_AUDIO_HV, 61, 1, "audio-hv"), \
2603 _pad(TEGRA_IO_PAD_AO_HV, UINT_MAX, 0, "ao-hv")
2604
2605 static const struct tegra_io_pad_soc tegra186_io_pads[] = {
2606 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PAD)
2607 };
2608
2609 static const struct pinctrl_pin_desc tegra186_pin_descs[] = {
2610 TEGRA186_IO_PAD_TABLE(TEGRA_IO_PIN_DESC)
2611 };
2612
2613 static const struct tegra_pmc_regs tegra186_pmc_regs = {
2614 .scratch0 = 0x2000,
2615 .dpd_req = 0x74,
2616 .dpd_status = 0x78,
2617 .dpd2_req = 0x7c,
2618 .dpd2_status = 0x80,
2619 .rst_status = 0x70,
2620 .rst_source_shift = 0x2,
2621 .rst_source_mask = 0x3C,
2622 .rst_level_shift = 0x0,
2623 .rst_level_mask = 0x3,
2624 };
2625
tegra186_pmc_setup_irq_polarity(struct tegra_pmc * pmc,struct device_node * np,bool invert)2626 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
2627 struct device_node *np,
2628 bool invert)
2629 {
2630 struct resource regs;
2631 void __iomem *wake;
2632 u32 value;
2633 int index;
2634
2635 index = of_property_match_string(np, "reg-names", "wake");
2636 if (index < 0) {
2637 dev_err(pmc->dev, "failed to find PMC wake registers\n");
2638 return;
2639 }
2640
2641 of_address_to_resource(np, index, ®s);
2642
2643 wake = ioremap_nocache(regs.start, resource_size(®s));
2644 if (!wake) {
2645 dev_err(pmc->dev, "failed to map PMC wake registers\n");
2646 return;
2647 }
2648
2649 value = readl(wake + WAKE_AOWAKE_CTRL);
2650
2651 if (invert)
2652 value |= WAKE_AOWAKE_CTRL_INTR_POLARITY;
2653 else
2654 value &= ~WAKE_AOWAKE_CTRL_INTR_POLARITY;
2655
2656 writel(value, wake + WAKE_AOWAKE_CTRL);
2657
2658 iounmap(wake);
2659 }
2660
2661 static const struct tegra_wake_event tegra186_wake_events[] = {
2662 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA186_AON_GPIO(FF, 0)),
2663 TEGRA_WAKE_IRQ("rtc", 73, 10),
2664 };
2665
2666 static const struct tegra_pmc_soc tegra186_pmc_soc = {
2667 .num_powergates = 0,
2668 .powergates = NULL,
2669 .num_cpu_powergates = 0,
2670 .cpu_powergates = NULL,
2671 .has_tsense_reset = false,
2672 .has_gpu_clamps = false,
2673 .needs_mbist_war = false,
2674 .has_impl_33v_pwr = true,
2675 .maybe_tz_only = false,
2676 .num_io_pads = ARRAY_SIZE(tegra186_io_pads),
2677 .io_pads = tegra186_io_pads,
2678 .num_pin_descs = ARRAY_SIZE(tegra186_pin_descs),
2679 .pin_descs = tegra186_pin_descs,
2680 .regs = &tegra186_pmc_regs,
2681 .init = NULL,
2682 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2683 .reset_sources = tegra186_reset_sources,
2684 .num_reset_sources = ARRAY_SIZE(tegra186_reset_sources),
2685 .reset_levels = tegra186_reset_levels,
2686 .num_reset_levels = ARRAY_SIZE(tegra186_reset_levels),
2687 .num_wake_events = ARRAY_SIZE(tegra186_wake_events),
2688 .wake_events = tegra186_wake_events,
2689 };
2690
2691 static const struct tegra_io_pad_soc tegra194_io_pads[] = {
2692 { .id = TEGRA_IO_PAD_CSIA, .dpd = 0, .voltage = UINT_MAX },
2693 { .id = TEGRA_IO_PAD_CSIB, .dpd = 1, .voltage = UINT_MAX },
2694 { .id = TEGRA_IO_PAD_MIPI_BIAS, .dpd = 3, .voltage = UINT_MAX },
2695 { .id = TEGRA_IO_PAD_PEX_CLK_BIAS, .dpd = 4, .voltage = UINT_MAX },
2696 { .id = TEGRA_IO_PAD_PEX_CLK3, .dpd = 5, .voltage = UINT_MAX },
2697 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 6, .voltage = UINT_MAX },
2698 { .id = TEGRA_IO_PAD_PEX_CLK1, .dpd = 7, .voltage = UINT_MAX },
2699 { .id = TEGRA_IO_PAD_EQOS, .dpd = 8, .voltage = UINT_MAX },
2700 { .id = TEGRA_IO_PAD_PEX_CLK2_BIAS, .dpd = 9, .voltage = UINT_MAX },
2701 { .id = TEGRA_IO_PAD_PEX_CLK2, .dpd = 10, .voltage = UINT_MAX },
2702 { .id = TEGRA_IO_PAD_DAP3, .dpd = 11, .voltage = UINT_MAX },
2703 { .id = TEGRA_IO_PAD_DAP5, .dpd = 12, .voltage = UINT_MAX },
2704 { .id = TEGRA_IO_PAD_UART, .dpd = 14, .voltage = UINT_MAX },
2705 { .id = TEGRA_IO_PAD_PWR_CTL, .dpd = 15, .voltage = UINT_MAX },
2706 { .id = TEGRA_IO_PAD_SOC_GPIO53, .dpd = 16, .voltage = UINT_MAX },
2707 { .id = TEGRA_IO_PAD_AUDIO, .dpd = 17, .voltage = UINT_MAX },
2708 { .id = TEGRA_IO_PAD_GP_PWM2, .dpd = 18, .voltage = UINT_MAX },
2709 { .id = TEGRA_IO_PAD_GP_PWM3, .dpd = 19, .voltage = UINT_MAX },
2710 { .id = TEGRA_IO_PAD_SOC_GPIO12, .dpd = 20, .voltage = UINT_MAX },
2711 { .id = TEGRA_IO_PAD_SOC_GPIO13, .dpd = 21, .voltage = UINT_MAX },
2712 { .id = TEGRA_IO_PAD_SOC_GPIO10, .dpd = 22, .voltage = UINT_MAX },
2713 { .id = TEGRA_IO_PAD_UART4, .dpd = 23, .voltage = UINT_MAX },
2714 { .id = TEGRA_IO_PAD_UART5, .dpd = 24, .voltage = UINT_MAX },
2715 { .id = TEGRA_IO_PAD_DBG, .dpd = 25, .voltage = UINT_MAX },
2716 { .id = TEGRA_IO_PAD_HDMI_DP3, .dpd = 26, .voltage = UINT_MAX },
2717 { .id = TEGRA_IO_PAD_HDMI_DP2, .dpd = 27, .voltage = UINT_MAX },
2718 { .id = TEGRA_IO_PAD_HDMI_DP0, .dpd = 28, .voltage = UINT_MAX },
2719 { .id = TEGRA_IO_PAD_HDMI_DP1, .dpd = 29, .voltage = UINT_MAX },
2720 { .id = TEGRA_IO_PAD_PEX_CNTRL, .dpd = 32, .voltage = UINT_MAX },
2721 { .id = TEGRA_IO_PAD_PEX_CTL2, .dpd = 33, .voltage = UINT_MAX },
2722 { .id = TEGRA_IO_PAD_PEX_L0_RST_N, .dpd = 34, .voltage = UINT_MAX },
2723 { .id = TEGRA_IO_PAD_PEX_L1_RST_N, .dpd = 35, .voltage = UINT_MAX },
2724 { .id = TEGRA_IO_PAD_SDMMC4, .dpd = 36, .voltage = UINT_MAX },
2725 { .id = TEGRA_IO_PAD_PEX_L5_RST_N, .dpd = 37, .voltage = UINT_MAX },
2726 { .id = TEGRA_IO_PAD_CSIC, .dpd = 43, .voltage = UINT_MAX },
2727 { .id = TEGRA_IO_PAD_CSID, .dpd = 44, .voltage = UINT_MAX },
2728 { .id = TEGRA_IO_PAD_CSIE, .dpd = 45, .voltage = UINT_MAX },
2729 { .id = TEGRA_IO_PAD_CSIF, .dpd = 46, .voltage = UINT_MAX },
2730 { .id = TEGRA_IO_PAD_SPI, .dpd = 47, .voltage = UINT_MAX },
2731 { .id = TEGRA_IO_PAD_UFS, .dpd = 49, .voltage = UINT_MAX },
2732 { .id = TEGRA_IO_PAD_CSIG, .dpd = 50, .voltage = UINT_MAX },
2733 { .id = TEGRA_IO_PAD_CSIH, .dpd = 51, .voltage = UINT_MAX },
2734 { .id = TEGRA_IO_PAD_EDP, .dpd = 53, .voltage = UINT_MAX },
2735 { .id = TEGRA_IO_PAD_SDMMC1_HV, .dpd = 55, .voltage = UINT_MAX },
2736 { .id = TEGRA_IO_PAD_SDMMC3_HV, .dpd = 56, .voltage = UINT_MAX },
2737 { .id = TEGRA_IO_PAD_CONN, .dpd = 60, .voltage = UINT_MAX },
2738 { .id = TEGRA_IO_PAD_AUDIO_HV, .dpd = 61, .voltage = UINT_MAX },
2739 };
2740
2741 static const struct tegra_wake_event tegra194_wake_events[] = {
2742 TEGRA_WAKE_GPIO("power", 29, 1, TEGRA194_AON_GPIO(EE, 4)),
2743 TEGRA_WAKE_IRQ("rtc", 73, 10),
2744 };
2745
2746 static const struct tegra_pmc_soc tegra194_pmc_soc = {
2747 .num_powergates = 0,
2748 .powergates = NULL,
2749 .num_cpu_powergates = 0,
2750 .cpu_powergates = NULL,
2751 .has_tsense_reset = false,
2752 .has_gpu_clamps = false,
2753 .needs_mbist_war = false,
2754 .has_impl_33v_pwr = false,
2755 .maybe_tz_only = false,
2756 .num_io_pads = ARRAY_SIZE(tegra194_io_pads),
2757 .io_pads = tegra194_io_pads,
2758 .regs = &tegra186_pmc_regs,
2759 .init = NULL,
2760 .setup_irq_polarity = tegra186_pmc_setup_irq_polarity,
2761 .num_wake_events = ARRAY_SIZE(tegra194_wake_events),
2762 .wake_events = tegra194_wake_events,
2763 };
2764
2765 static const struct of_device_id tegra_pmc_match[] = {
2766 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
2767 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
2768 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
2769 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
2770 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
2771 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
2772 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
2773 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
2774 { }
2775 };
2776
2777 static struct platform_driver tegra_pmc_driver = {
2778 .driver = {
2779 .name = "tegra-pmc",
2780 .suppress_bind_attrs = true,
2781 .of_match_table = tegra_pmc_match,
2782 #if defined(CONFIG_PM_SLEEP) && defined(CONFIG_ARM)
2783 .pm = &tegra_pmc_pm_ops,
2784 #endif
2785 },
2786 .probe = tegra_pmc_probe,
2787 };
2788 builtin_platform_driver(tegra_pmc_driver);
2789
tegra_pmc_detect_tz_only(struct tegra_pmc * pmc)2790 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
2791 {
2792 u32 value, saved;
2793
2794 saved = readl(pmc->base + pmc->soc->regs->scratch0);
2795 value = saved ^ 0xffffffff;
2796
2797 if (value == 0xffffffff)
2798 value = 0xdeadbeef;
2799
2800 /* write pattern and read it back */
2801 writel(value, pmc->base + pmc->soc->regs->scratch0);
2802 value = readl(pmc->base + pmc->soc->regs->scratch0);
2803
2804 /* if we read all-zeroes, access is restricted to TZ only */
2805 if (value == 0) {
2806 pr_info("access to PMC is restricted to TZ\n");
2807 return true;
2808 }
2809
2810 /* restore original value */
2811 writel(saved, pmc->base + pmc->soc->regs->scratch0);
2812
2813 return false;
2814 }
2815
2816 /*
2817 * Early initialization to allow access to registers in the very early boot
2818 * process.
2819 */
tegra_pmc_early_init(void)2820 static int __init tegra_pmc_early_init(void)
2821 {
2822 const struct of_device_id *match;
2823 struct device_node *np;
2824 struct resource regs;
2825 unsigned int i;
2826 bool invert;
2827
2828 mutex_init(&pmc->powergates_lock);
2829
2830 np = of_find_matching_node_and_match(NULL, tegra_pmc_match, &match);
2831 if (!np) {
2832 /*
2833 * Fall back to legacy initialization for 32-bit ARM only. All
2834 * 64-bit ARM device tree files for Tegra are required to have
2835 * a PMC node.
2836 *
2837 * This is for backwards-compatibility with old device trees
2838 * that didn't contain a PMC node. Note that in this case the
2839 * SoC data can't be matched and therefore powergating is
2840 * disabled.
2841 */
2842 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
2843 pr_warn("DT node not found, powergating disabled\n");
2844
2845 regs.start = 0x7000e400;
2846 regs.end = 0x7000e7ff;
2847 regs.flags = IORESOURCE_MEM;
2848
2849 pr_warn("Using memory region %pR\n", ®s);
2850 } else {
2851 /*
2852 * At this point we're not running on Tegra, so play
2853 * nice with multi-platform kernels.
2854 */
2855 return 0;
2856 }
2857 } else {
2858 /*
2859 * Extract information from the device tree if we've found a
2860 * matching node.
2861 */
2862 if (of_address_to_resource(np, 0, ®s) < 0) {
2863 pr_err("failed to get PMC registers\n");
2864 of_node_put(np);
2865 return -ENXIO;
2866 }
2867 }
2868
2869 pmc->base = ioremap_nocache(regs.start, resource_size(®s));
2870 if (!pmc->base) {
2871 pr_err("failed to map PMC registers\n");
2872 of_node_put(np);
2873 return -ENXIO;
2874 }
2875
2876 if (np) {
2877 pmc->soc = match->data;
2878
2879 if (pmc->soc->maybe_tz_only)
2880 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
2881
2882 /* Create a bitmap of the available and valid partitions */
2883 for (i = 0; i < pmc->soc->num_powergates; i++)
2884 if (pmc->soc->powergates[i])
2885 set_bit(i, pmc->powergates_available);
2886
2887 /*
2888 * Invert the interrupt polarity if a PMC device tree node
2889 * exists and contains the nvidia,invert-interrupt property.
2890 */
2891 invert = of_property_read_bool(np, "nvidia,invert-interrupt");
2892
2893 pmc->soc->setup_irq_polarity(pmc, np, invert);
2894
2895 of_node_put(np);
2896 }
2897
2898 return 0;
2899 }
2900 early_initcall(tegra_pmc_early_init);
2901
