1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
4 *
5 * Authors: Shlomi Gridish <gridish@freescale.com>
6 * Li Yang <leoli@freescale.com>
7 *
8 * Description:
9 * QE UCC Slow API Set - UCC Slow specific routines implementations.
10 */
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
13 #include <linux/slab.h>
14 #include <linux/stddef.h>
15 #include <linux/interrupt.h>
16 #include <linux/err.h>
17 #include <linux/export.h>
18
19 #include <asm/io.h>
20 #include <soc/fsl/qe/immap_qe.h>
21 #include <soc/fsl/qe/qe.h>
22
23 #include <soc/fsl/qe/ucc.h>
24 #include <soc/fsl/qe/ucc_slow.h>
25
ucc_slow_get_qe_cr_subblock(int uccs_num)26 u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
27 {
28 switch (uccs_num) {
29 case 0: return QE_CR_SUBBLOCK_UCCSLOW1;
30 case 1: return QE_CR_SUBBLOCK_UCCSLOW2;
31 case 2: return QE_CR_SUBBLOCK_UCCSLOW3;
32 case 3: return QE_CR_SUBBLOCK_UCCSLOW4;
33 case 4: return QE_CR_SUBBLOCK_UCCSLOW5;
34 case 5: return QE_CR_SUBBLOCK_UCCSLOW6;
35 case 6: return QE_CR_SUBBLOCK_UCCSLOW7;
36 case 7: return QE_CR_SUBBLOCK_UCCSLOW8;
37 default: return QE_CR_SUBBLOCK_INVALID;
38 }
39 }
40 EXPORT_SYMBOL(ucc_slow_get_qe_cr_subblock);
41
ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)42 void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
43 {
44 struct ucc_slow_info *us_info = uccs->us_info;
45 u32 id;
46
47 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
48 qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
49 QE_CR_PROTOCOL_UNSPECIFIED, 0);
50 }
51 EXPORT_SYMBOL(ucc_slow_graceful_stop_tx);
52
ucc_slow_stop_tx(struct ucc_slow_private * uccs)53 void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
54 {
55 struct ucc_slow_info *us_info = uccs->us_info;
56 u32 id;
57
58 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
59 qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
60 }
61 EXPORT_SYMBOL(ucc_slow_stop_tx);
62
ucc_slow_restart_tx(struct ucc_slow_private * uccs)63 void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
64 {
65 struct ucc_slow_info *us_info = uccs->us_info;
66 u32 id;
67
68 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
69 qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
70 }
71 EXPORT_SYMBOL(ucc_slow_restart_tx);
72
ucc_slow_enable(struct ucc_slow_private * uccs,enum comm_dir mode)73 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
74 {
75 struct ucc_slow *us_regs;
76 u32 gumr_l;
77
78 us_regs = uccs->us_regs;
79
80 /* Enable reception and/or transmission on this UCC. */
81 gumr_l = in_be32(&us_regs->gumr_l);
82 if (mode & COMM_DIR_TX) {
83 gumr_l |= UCC_SLOW_GUMR_L_ENT;
84 uccs->enabled_tx = 1;
85 }
86 if (mode & COMM_DIR_RX) {
87 gumr_l |= UCC_SLOW_GUMR_L_ENR;
88 uccs->enabled_rx = 1;
89 }
90 out_be32(&us_regs->gumr_l, gumr_l);
91 }
92 EXPORT_SYMBOL(ucc_slow_enable);
93
ucc_slow_disable(struct ucc_slow_private * uccs,enum comm_dir mode)94 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
95 {
96 struct ucc_slow *us_regs;
97 u32 gumr_l;
98
99 us_regs = uccs->us_regs;
100
101 /* Disable reception and/or transmission on this UCC. */
102 gumr_l = in_be32(&us_regs->gumr_l);
103 if (mode & COMM_DIR_TX) {
104 gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
105 uccs->enabled_tx = 0;
106 }
107 if (mode & COMM_DIR_RX) {
108 gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
109 uccs->enabled_rx = 0;
110 }
111 out_be32(&us_regs->gumr_l, gumr_l);
112 }
113 EXPORT_SYMBOL(ucc_slow_disable);
114
115 /* Initialize the UCC for Slow operations
116 *
117 * The caller should initialize the following us_info
118 */
ucc_slow_init(struct ucc_slow_info * us_info,struct ucc_slow_private ** uccs_ret)119 int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
120 {
121 struct ucc_slow_private *uccs;
122 u32 i;
123 struct ucc_slow __iomem *us_regs;
124 u32 gumr;
125 struct qe_bd *bd;
126 u32 id;
127 u32 command;
128 int ret = 0;
129
130 if (!us_info)
131 return -EINVAL;
132
133 /* check if the UCC port number is in range. */
134 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
135 printk(KERN_ERR "%s: illegal UCC number\n", __func__);
136 return -EINVAL;
137 }
138
139 /*
140 * Set mrblr
141 * Check that 'max_rx_buf_length' is properly aligned (4), unless
142 * rfw is 1, meaning that QE accepts one byte at a time, unlike normal
143 * case when QE accepts 32 bits at a time.
144 */
145 if ((!us_info->rfw) &&
146 (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
147 printk(KERN_ERR "max_rx_buf_length not aligned.\n");
148 return -EINVAL;
149 }
150
151 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
152 if (!uccs) {
153 printk(KERN_ERR "%s: Cannot allocate private data\n",
154 __func__);
155 return -ENOMEM;
156 }
157
158 /* Fill slow UCC structure */
159 uccs->us_info = us_info;
160 /* Set the PHY base address */
161 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
162 if (uccs->us_regs == NULL) {
163 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
164 kfree(uccs);
165 return -ENOMEM;
166 }
167
168 uccs->saved_uccm = 0;
169 uccs->p_rx_frame = 0;
170 us_regs = uccs->us_regs;
171 uccs->p_ucce = (u16 *) & (us_regs->ucce);
172 uccs->p_uccm = (u16 *) & (us_regs->uccm);
173 #ifdef STATISTICS
174 uccs->rx_frames = 0;
175 uccs->tx_frames = 0;
176 uccs->rx_discarded = 0;
177 #endif /* STATISTICS */
178
179 /* Get PRAM base */
180 uccs->us_pram_offset =
181 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
182 if (IS_ERR_VALUE(uccs->us_pram_offset)) {
183 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
184 ucc_slow_free(uccs);
185 return -ENOMEM;
186 }
187 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
188 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol,
189 uccs->us_pram_offset);
190
191 uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
192
193 /* Set UCC to slow type */
194 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
195 if (ret) {
196 printk(KERN_ERR "%s: cannot set UCC type", __func__);
197 ucc_slow_free(uccs);
198 return ret;
199 }
200
201 out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
202
203 INIT_LIST_HEAD(&uccs->confQ);
204
205 /* Allocate BDs. */
206 uccs->rx_base_offset =
207 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
208 QE_ALIGNMENT_OF_BD);
209 if (IS_ERR_VALUE(uccs->rx_base_offset)) {
210 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
211 us_info->rx_bd_ring_len);
212 uccs->rx_base_offset = 0;
213 ucc_slow_free(uccs);
214 return -ENOMEM;
215 }
216
217 uccs->tx_base_offset =
218 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
219 QE_ALIGNMENT_OF_BD);
220 if (IS_ERR_VALUE(uccs->tx_base_offset)) {
221 printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
222 uccs->tx_base_offset = 0;
223 ucc_slow_free(uccs);
224 return -ENOMEM;
225 }
226
227 /* Init Tx bds */
228 bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
229 for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
230 /* clear bd buffer */
231 out_be32(&bd->buf, 0);
232 /* set bd status and length */
233 out_be32((u32 *) bd, 0);
234 bd++;
235 }
236 /* for last BD set Wrap bit */
237 out_be32(&bd->buf, 0);
238 out_be32((u32 *) bd, cpu_to_be32(T_W));
239
240 /* Init Rx bds */
241 bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
242 for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
243 /* set bd status and length */
244 out_be32((u32*)bd, 0);
245 /* clear bd buffer */
246 out_be32(&bd->buf, 0);
247 bd++;
248 }
249 /* for last BD set Wrap bit */
250 out_be32((u32*)bd, cpu_to_be32(R_W));
251 out_be32(&bd->buf, 0);
252
253 /* Set GUMR (For more details see the hardware spec.). */
254 /* gumr_h */
255 gumr = us_info->tcrc;
256 if (us_info->cdp)
257 gumr |= UCC_SLOW_GUMR_H_CDP;
258 if (us_info->ctsp)
259 gumr |= UCC_SLOW_GUMR_H_CTSP;
260 if (us_info->cds)
261 gumr |= UCC_SLOW_GUMR_H_CDS;
262 if (us_info->ctss)
263 gumr |= UCC_SLOW_GUMR_H_CTSS;
264 if (us_info->tfl)
265 gumr |= UCC_SLOW_GUMR_H_TFL;
266 if (us_info->rfw)
267 gumr |= UCC_SLOW_GUMR_H_RFW;
268 if (us_info->txsy)
269 gumr |= UCC_SLOW_GUMR_H_TXSY;
270 if (us_info->rtsm)
271 gumr |= UCC_SLOW_GUMR_H_RTSM;
272 out_be32(&us_regs->gumr_h, gumr);
273
274 /* gumr_l */
275 gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
276 us_info->diag | us_info->mode;
277 if (us_info->tci)
278 gumr |= UCC_SLOW_GUMR_L_TCI;
279 if (us_info->rinv)
280 gumr |= UCC_SLOW_GUMR_L_RINV;
281 if (us_info->tinv)
282 gumr |= UCC_SLOW_GUMR_L_TINV;
283 if (us_info->tend)
284 gumr |= UCC_SLOW_GUMR_L_TEND;
285 out_be32(&us_regs->gumr_l, gumr);
286
287 /* Function code registers */
288
289 /* if the data is in cachable memory, the 'global' */
290 /* in the function code should be set. */
291 uccs->us_pram->tbmr = UCC_BMR_BO_BE;
292 uccs->us_pram->rbmr = UCC_BMR_BO_BE;
293
294 /* rbase, tbase are offsets from MURAM base */
295 out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
296 out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
297
298 /* Mux clocking */
299 /* Grant Support */
300 ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
301 /* Breakpoint Support */
302 ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
303 /* Set Tsa or NMSI mode. */
304 ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
305 /* If NMSI (not Tsa), set Tx and Rx clock. */
306 if (!us_info->tsa) {
307 /* Rx clock routing */
308 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
309 COMM_DIR_RX)) {
310 printk(KERN_ERR "%s: illegal value for RX clock\n",
311 __func__);
312 ucc_slow_free(uccs);
313 return -EINVAL;
314 }
315 /* Tx clock routing */
316 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
317 COMM_DIR_TX)) {
318 printk(KERN_ERR "%s: illegal value for TX clock\n",
319 __func__);
320 ucc_slow_free(uccs);
321 return -EINVAL;
322 }
323 }
324
325 /* Set interrupt mask register at UCC level. */
326 out_be16(&us_regs->uccm, us_info->uccm_mask);
327
328 /* First, clear anything pending at UCC level,
329 * otherwise, old garbage may come through
330 * as soon as the dam is opened. */
331
332 /* Writing '1' clears */
333 out_be16(&us_regs->ucce, 0xffff);
334
335 /* Issue QE Init command */
336 if (us_info->init_tx && us_info->init_rx)
337 command = QE_INIT_TX_RX;
338 else if (us_info->init_tx)
339 command = QE_INIT_TX;
340 else
341 command = QE_INIT_RX; /* We know at least one is TRUE */
342
343 qe_issue_cmd(command, id, us_info->protocol, 0);
344
345 *uccs_ret = uccs;
346 return 0;
347 }
348 EXPORT_SYMBOL(ucc_slow_init);
349
ucc_slow_free(struct ucc_slow_private * uccs)350 void ucc_slow_free(struct ucc_slow_private * uccs)
351 {
352 if (!uccs)
353 return;
354
355 if (uccs->rx_base_offset)
356 qe_muram_free(uccs->rx_base_offset);
357
358 if (uccs->tx_base_offset)
359 qe_muram_free(uccs->tx_base_offset);
360
361 if (uccs->us_pram)
362 qe_muram_free(uccs->us_pram_offset);
363
364 if (uccs->us_regs)
365 iounmap(uccs->us_regs);
366
367 kfree(uccs);
368 }
369 EXPORT_SYMBOL(ucc_slow_free);
370
371
