1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015 MediaTek Inc.
4 * Author: Tianping.Fang <tianping.fang@mediatek.com>
5 */
6
7 #include <linux/delay.h>
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/regmap.h>
11 #include <linux/rtc.h>
12 #include <linux/irqdomain.h>
13 #include <linux/platform_device.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/io.h>
17 #include <linux/mfd/mt6397/core.h>
18
19 #define RTC_BBPU 0x0000
20 #define RTC_BBPU_CBUSY BIT(6)
21
22 #define RTC_WRTGR 0x003c
23
24 #define RTC_IRQ_STA 0x0002
25 #define RTC_IRQ_STA_AL BIT(0)
26 #define RTC_IRQ_STA_LP BIT(3)
27
28 #define RTC_IRQ_EN 0x0004
29 #define RTC_IRQ_EN_AL BIT(0)
30 #define RTC_IRQ_EN_ONESHOT BIT(2)
31 #define RTC_IRQ_EN_LP BIT(3)
32 #define RTC_IRQ_EN_ONESHOT_AL (RTC_IRQ_EN_ONESHOT | RTC_IRQ_EN_AL)
33
34 #define RTC_AL_MASK 0x0008
35 #define RTC_AL_MASK_DOW BIT(4)
36
37 #define RTC_TC_SEC 0x000a
38 /* Min, Hour, Dom... register offset to RTC_TC_SEC */
39 #define RTC_OFFSET_SEC 0
40 #define RTC_OFFSET_MIN 1
41 #define RTC_OFFSET_HOUR 2
42 #define RTC_OFFSET_DOM 3
43 #define RTC_OFFSET_DOW 4
44 #define RTC_OFFSET_MTH 5
45 #define RTC_OFFSET_YEAR 6
46 #define RTC_OFFSET_COUNT 7
47
48 #define RTC_AL_SEC 0x0018
49
50 #define RTC_PDN2 0x002e
51 #define RTC_PDN2_PWRON_ALARM BIT(4)
52
53 #define RTC_MIN_YEAR 1968
54 #define RTC_BASE_YEAR 1900
55 #define RTC_NUM_YEARS 128
56 #define RTC_MIN_YEAR_OFFSET (RTC_MIN_YEAR - RTC_BASE_YEAR)
57
58 struct mt6397_rtc {
59 struct device *dev;
60 struct rtc_device *rtc_dev;
61 struct mutex lock;
62 struct regmap *regmap;
63 int irq;
64 u32 addr_base;
65 };
66
mtk_rtc_write_trigger(struct mt6397_rtc * rtc)67 static int mtk_rtc_write_trigger(struct mt6397_rtc *rtc)
68 {
69 unsigned long timeout = jiffies + HZ;
70 int ret;
71 u32 data;
72
73 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_WRTGR, 1);
74 if (ret < 0)
75 return ret;
76
77 while (1) {
78 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_BBPU,
79 &data);
80 if (ret < 0)
81 break;
82 if (!(data & RTC_BBPU_CBUSY))
83 break;
84 if (time_after(jiffies, timeout)) {
85 ret = -ETIMEDOUT;
86 break;
87 }
88 cpu_relax();
89 }
90
91 return ret;
92 }
93
mtk_rtc_irq_handler_thread(int irq,void * data)94 static irqreturn_t mtk_rtc_irq_handler_thread(int irq, void *data)
95 {
96 struct mt6397_rtc *rtc = data;
97 u32 irqsta, irqen;
98 int ret;
99
100 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_STA, &irqsta);
101 if ((ret >= 0) && (irqsta & RTC_IRQ_STA_AL)) {
102 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
103 irqen = irqsta & ~RTC_IRQ_EN_AL;
104 mutex_lock(&rtc->lock);
105 if (regmap_write(rtc->regmap, rtc->addr_base + RTC_IRQ_EN,
106 irqen) < 0)
107 mtk_rtc_write_trigger(rtc);
108 mutex_unlock(&rtc->lock);
109
110 return IRQ_HANDLED;
111 }
112
113 return IRQ_NONE;
114 }
115
__mtk_rtc_read_time(struct mt6397_rtc * rtc,struct rtc_time * tm,int * sec)116 static int __mtk_rtc_read_time(struct mt6397_rtc *rtc,
117 struct rtc_time *tm, int *sec)
118 {
119 int ret;
120 u16 data[RTC_OFFSET_COUNT];
121
122 mutex_lock(&rtc->lock);
123 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
124 data, RTC_OFFSET_COUNT);
125 if (ret < 0)
126 goto exit;
127
128 tm->tm_sec = data[RTC_OFFSET_SEC];
129 tm->tm_min = data[RTC_OFFSET_MIN];
130 tm->tm_hour = data[RTC_OFFSET_HOUR];
131 tm->tm_mday = data[RTC_OFFSET_DOM];
132 tm->tm_mon = data[RTC_OFFSET_MTH];
133 tm->tm_year = data[RTC_OFFSET_YEAR];
134
135 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_TC_SEC, sec);
136 exit:
137 mutex_unlock(&rtc->lock);
138 return ret;
139 }
140
mtk_rtc_read_time(struct device * dev,struct rtc_time * tm)141 static int mtk_rtc_read_time(struct device *dev, struct rtc_time *tm)
142 {
143 time64_t time;
144 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
145 int days, sec, ret;
146
147 do {
148 ret = __mtk_rtc_read_time(rtc, tm, &sec);
149 if (ret < 0)
150 goto exit;
151 } while (sec < tm->tm_sec);
152
153 /* HW register use 7 bits to store year data, minus
154 * RTC_MIN_YEAR_OFFSET before write year data to register, and plus
155 * RTC_MIN_YEAR_OFFSET back after read year from register
156 */
157 tm->tm_year += RTC_MIN_YEAR_OFFSET;
158
159 /* HW register start mon from one, but tm_mon start from zero. */
160 tm->tm_mon--;
161 time = rtc_tm_to_time64(tm);
162
163 /* rtc_tm_to_time64 covert Gregorian date to seconds since
164 * 01-01-1970 00:00:00, and this date is Thursday.
165 */
166 days = div_s64(time, 86400);
167 tm->tm_wday = (days + 4) % 7;
168
169 exit:
170 return ret;
171 }
172
mtk_rtc_set_time(struct device * dev,struct rtc_time * tm)173 static int mtk_rtc_set_time(struct device *dev, struct rtc_time *tm)
174 {
175 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
176 int ret;
177 u16 data[RTC_OFFSET_COUNT];
178
179 tm->tm_year -= RTC_MIN_YEAR_OFFSET;
180 tm->tm_mon++;
181
182 data[RTC_OFFSET_SEC] = tm->tm_sec;
183 data[RTC_OFFSET_MIN] = tm->tm_min;
184 data[RTC_OFFSET_HOUR] = tm->tm_hour;
185 data[RTC_OFFSET_DOM] = tm->tm_mday;
186 data[RTC_OFFSET_MTH] = tm->tm_mon;
187 data[RTC_OFFSET_YEAR] = tm->tm_year;
188
189 mutex_lock(&rtc->lock);
190 ret = regmap_bulk_write(rtc->regmap, rtc->addr_base + RTC_TC_SEC,
191 data, RTC_OFFSET_COUNT);
192 if (ret < 0)
193 goto exit;
194
195 /* Time register write to hardware after call trigger function */
196 ret = mtk_rtc_write_trigger(rtc);
197
198 exit:
199 mutex_unlock(&rtc->lock);
200 return ret;
201 }
202
mtk_rtc_read_alarm(struct device * dev,struct rtc_wkalrm * alm)203 static int mtk_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alm)
204 {
205 struct rtc_time *tm = &alm->time;
206 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
207 u32 irqen, pdn2;
208 int ret;
209 u16 data[RTC_OFFSET_COUNT];
210
211 mutex_lock(&rtc->lock);
212 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_IRQ_EN, &irqen);
213 if (ret < 0)
214 goto err_exit;
215 ret = regmap_read(rtc->regmap, rtc->addr_base + RTC_PDN2, &pdn2);
216 if (ret < 0)
217 goto err_exit;
218
219 ret = regmap_bulk_read(rtc->regmap, rtc->addr_base + RTC_AL_SEC,
220 data, RTC_OFFSET_COUNT);
221 if (ret < 0)
222 goto err_exit;
223
224 alm->enabled = !!(irqen & RTC_IRQ_EN_AL);
225 alm->pending = !!(pdn2 & RTC_PDN2_PWRON_ALARM);
226 mutex_unlock(&rtc->lock);
227
228 tm->tm_sec = data[RTC_OFFSET_SEC];
229 tm->tm_min = data[RTC_OFFSET_MIN];
230 tm->tm_hour = data[RTC_OFFSET_HOUR];
231 tm->tm_mday = data[RTC_OFFSET_DOM];
232 tm->tm_mon = data[RTC_OFFSET_MTH];
233 tm->tm_year = data[RTC_OFFSET_YEAR];
234
235 tm->tm_year += RTC_MIN_YEAR_OFFSET;
236 tm->tm_mon--;
237
238 return 0;
239 err_exit:
240 mutex_unlock(&rtc->lock);
241 return ret;
242 }
243
mtk_rtc_set_alarm(struct device * dev,struct rtc_wkalrm * alm)244 static int mtk_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alm)
245 {
246 struct rtc_time *tm = &alm->time;
247 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
248 int ret;
249 u16 data[RTC_OFFSET_COUNT];
250
251 tm->tm_year -= RTC_MIN_YEAR_OFFSET;
252 tm->tm_mon++;
253
254 data[RTC_OFFSET_SEC] = tm->tm_sec;
255 data[RTC_OFFSET_MIN] = tm->tm_min;
256 data[RTC_OFFSET_HOUR] = tm->tm_hour;
257 data[RTC_OFFSET_DOM] = tm->tm_mday;
258 data[RTC_OFFSET_MTH] = tm->tm_mon;
259 data[RTC_OFFSET_YEAR] = tm->tm_year;
260
261 mutex_lock(&rtc->lock);
262 if (alm->enabled) {
263 ret = regmap_bulk_write(rtc->regmap,
264 rtc->addr_base + RTC_AL_SEC,
265 data, RTC_OFFSET_COUNT);
266 if (ret < 0)
267 goto exit;
268 ret = regmap_write(rtc->regmap, rtc->addr_base + RTC_AL_MASK,
269 RTC_AL_MASK_DOW);
270 if (ret < 0)
271 goto exit;
272 ret = regmap_update_bits(rtc->regmap,
273 rtc->addr_base + RTC_IRQ_EN,
274 RTC_IRQ_EN_ONESHOT_AL,
275 RTC_IRQ_EN_ONESHOT_AL);
276 if (ret < 0)
277 goto exit;
278 } else {
279 ret = regmap_update_bits(rtc->regmap,
280 rtc->addr_base + RTC_IRQ_EN,
281 RTC_IRQ_EN_ONESHOT_AL, 0);
282 if (ret < 0)
283 goto exit;
284 }
285
286 /* All alarm time register write to hardware after calling
287 * mtk_rtc_write_trigger. This can avoid race condition if alarm
288 * occur happen during writing alarm time register.
289 */
290 ret = mtk_rtc_write_trigger(rtc);
291 exit:
292 mutex_unlock(&rtc->lock);
293 return ret;
294 }
295
296 static const struct rtc_class_ops mtk_rtc_ops = {
297 .read_time = mtk_rtc_read_time,
298 .set_time = mtk_rtc_set_time,
299 .read_alarm = mtk_rtc_read_alarm,
300 .set_alarm = mtk_rtc_set_alarm,
301 };
302
mtk_rtc_probe(struct platform_device * pdev)303 static int mtk_rtc_probe(struct platform_device *pdev)
304 {
305 struct resource *res;
306 struct mt6397_chip *mt6397_chip = dev_get_drvdata(pdev->dev.parent);
307 struct mt6397_rtc *rtc;
308 int ret;
309
310 rtc = devm_kzalloc(&pdev->dev, sizeof(struct mt6397_rtc), GFP_KERNEL);
311 if (!rtc)
312 return -ENOMEM;
313
314 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
315 rtc->addr_base = res->start;
316
317 rtc->irq = platform_get_irq(pdev, 0);
318 if (rtc->irq < 0)
319 return rtc->irq;
320
321 rtc->regmap = mt6397_chip->regmap;
322 rtc->dev = &pdev->dev;
323 mutex_init(&rtc->lock);
324
325 platform_set_drvdata(pdev, rtc);
326
327 rtc->rtc_dev = devm_rtc_allocate_device(rtc->dev);
328 if (IS_ERR(rtc->rtc_dev))
329 return PTR_ERR(rtc->rtc_dev);
330
331 ret = request_threaded_irq(rtc->irq, NULL,
332 mtk_rtc_irq_handler_thread,
333 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
334 "mt6397-rtc", rtc);
335 if (ret) {
336 dev_err(&pdev->dev, "Failed to request alarm IRQ: %d: %d\n",
337 rtc->irq, ret);
338 return ret;
339 }
340
341 device_init_wakeup(&pdev->dev, 1);
342
343 rtc->rtc_dev->ops = &mtk_rtc_ops;
344
345 ret = rtc_register_device(rtc->rtc_dev);
346 if (ret)
347 goto out_free_irq;
348
349 return 0;
350
351 out_free_irq:
352 free_irq(rtc->irq, rtc);
353 return ret;
354 }
355
mtk_rtc_remove(struct platform_device * pdev)356 static int mtk_rtc_remove(struct platform_device *pdev)
357 {
358 struct mt6397_rtc *rtc = platform_get_drvdata(pdev);
359
360 free_irq(rtc->irq, rtc);
361
362 return 0;
363 }
364
365 #ifdef CONFIG_PM_SLEEP
mt6397_rtc_suspend(struct device * dev)366 static int mt6397_rtc_suspend(struct device *dev)
367 {
368 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
369
370 if (device_may_wakeup(dev))
371 enable_irq_wake(rtc->irq);
372
373 return 0;
374 }
375
mt6397_rtc_resume(struct device * dev)376 static int mt6397_rtc_resume(struct device *dev)
377 {
378 struct mt6397_rtc *rtc = dev_get_drvdata(dev);
379
380 if (device_may_wakeup(dev))
381 disable_irq_wake(rtc->irq);
382
383 return 0;
384 }
385 #endif
386
387 static SIMPLE_DEV_PM_OPS(mt6397_pm_ops, mt6397_rtc_suspend,
388 mt6397_rtc_resume);
389
390 static const struct of_device_id mt6397_rtc_of_match[] = {
391 { .compatible = "mediatek,mt6397-rtc", },
392 { }
393 };
394 MODULE_DEVICE_TABLE(of, mt6397_rtc_of_match);
395
396 static struct platform_driver mtk_rtc_driver = {
397 .driver = {
398 .name = "mt6397-rtc",
399 .of_match_table = mt6397_rtc_of_match,
400 .pm = &mt6397_pm_ops,
401 },
402 .probe = mtk_rtc_probe,
403 .remove = mtk_rtc_remove,
404 };
405
406 module_platform_driver(mtk_rtc_driver);
407
408 MODULE_LICENSE("GPL v2");
409 MODULE_AUTHOR("Tianping Fang <tianping.fang@mediatek.com>");
410 MODULE_DESCRIPTION("RTC Driver for MediaTek MT6397 PMIC");
411
