1 /*
2 * Copyright 2017 Broadcom
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14 #include <linux/err.h>
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/mod_devicetable.h>
18 #include <linux/platform_device.h>
19 #include <linux/ptp_clock_kernel.h>
20 #include <linux/types.h>
21
22 #define DTE_NCO_LOW_TIME_REG 0x00
23 #define DTE_NCO_TIME_REG 0x04
24 #define DTE_NCO_OVERFLOW_REG 0x08
25 #define DTE_NCO_INC_REG 0x0c
26
27 #define DTE_NCO_SUM2_MASK 0xffffffff
28 #define DTE_NCO_SUM2_SHIFT 4ULL
29
30 #define DTE_NCO_SUM3_MASK 0xff
31 #define DTE_NCO_SUM3_SHIFT 36ULL
32 #define DTE_NCO_SUM3_WR_SHIFT 8
33
34 #define DTE_NCO_TS_WRAP_MASK 0xfff
35 #define DTE_NCO_TS_WRAP_LSHIFT 32
36
37 #define DTE_NCO_INC_DEFAULT 0x80000000
38 #define DTE_NUM_REGS_TO_RESTORE 4
39
40 /* Full wrap around is 44bits in ns (~4.887 hrs) */
41 #define DTE_WRAP_AROUND_NSEC_SHIFT 44
42
43 /* 44 bits NCO */
44 #define DTE_NCO_MAX_NS 0xFFFFFFFFFFFLL
45
46 /* 125MHz with 3.29 reg cfg */
47 #define DTE_PPB_ADJ(ppb) (u32)(div64_u64((((u64)abs(ppb) * BIT(28)) +\
48 62500000ULL), 125000000ULL))
49
50 /* ptp dte priv structure */
51 struct ptp_dte {
52 void __iomem *regs;
53 struct ptp_clock *ptp_clk;
54 struct ptp_clock_info caps;
55 struct device *dev;
56 u32 ts_ovf_last;
57 u32 ts_wrap_cnt;
58 spinlock_t lock;
59 u32 reg_val[DTE_NUM_REGS_TO_RESTORE];
60 };
61
dte_write_nco(void __iomem * regs,s64 ns)62 static void dte_write_nco(void __iomem *regs, s64 ns)
63 {
64 u32 sum2, sum3;
65
66 sum2 = (u32)((ns >> DTE_NCO_SUM2_SHIFT) & DTE_NCO_SUM2_MASK);
67 /* compensate for ignoring sum1 */
68 if (sum2 != DTE_NCO_SUM2_MASK)
69 sum2++;
70
71 /* to write sum3, bits [15:8] needs to be written */
72 sum3 = (u32)(((ns >> DTE_NCO_SUM3_SHIFT) & DTE_NCO_SUM3_MASK) <<
73 DTE_NCO_SUM3_WR_SHIFT);
74
75 writel(0, (regs + DTE_NCO_LOW_TIME_REG));
76 writel(sum2, (regs + DTE_NCO_TIME_REG));
77 writel(sum3, (regs + DTE_NCO_OVERFLOW_REG));
78 }
79
dte_read_nco(void __iomem * regs)80 static s64 dte_read_nco(void __iomem *regs)
81 {
82 u32 sum2, sum3;
83 s64 ns;
84
85 /*
86 * ignoring sum1 (4 bits) gives a 16ns resolution, which
87 * works due to the async register read.
88 */
89 sum3 = readl(regs + DTE_NCO_OVERFLOW_REG) & DTE_NCO_SUM3_MASK;
90 sum2 = readl(regs + DTE_NCO_TIME_REG);
91 ns = ((s64)sum3 << DTE_NCO_SUM3_SHIFT) |
92 ((s64)sum2 << DTE_NCO_SUM2_SHIFT);
93
94 return ns;
95 }
96
dte_write_nco_delta(struct ptp_dte * ptp_dte,s64 delta)97 static void dte_write_nco_delta(struct ptp_dte *ptp_dte, s64 delta)
98 {
99 s64 ns;
100
101 ns = dte_read_nco(ptp_dte->regs);
102
103 /* handle wraparound conditions */
104 if ((delta < 0) && (abs(delta) > ns)) {
105 if (ptp_dte->ts_wrap_cnt) {
106 ns += DTE_NCO_MAX_NS + delta;
107 ptp_dte->ts_wrap_cnt--;
108 } else {
109 ns = 0;
110 }
111 } else {
112 ns += delta;
113 if (ns > DTE_NCO_MAX_NS) {
114 ptp_dte->ts_wrap_cnt++;
115 ns -= DTE_NCO_MAX_NS;
116 }
117 }
118
119 dte_write_nco(ptp_dte->regs, ns);
120
121 ptp_dte->ts_ovf_last = (ns >> DTE_NCO_TS_WRAP_LSHIFT) &
122 DTE_NCO_TS_WRAP_MASK;
123 }
124
dte_read_nco_with_ovf(struct ptp_dte * ptp_dte)125 static s64 dte_read_nco_with_ovf(struct ptp_dte *ptp_dte)
126 {
127 u32 ts_ovf;
128 s64 ns = 0;
129
130 ns = dte_read_nco(ptp_dte->regs);
131
132 /*Timestamp overflow: 8 LSB bits of sum3, 4 MSB bits of sum2 */
133 ts_ovf = (ns >> DTE_NCO_TS_WRAP_LSHIFT) & DTE_NCO_TS_WRAP_MASK;
134
135 /* Check for wrap around */
136 if (ts_ovf < ptp_dte->ts_ovf_last)
137 ptp_dte->ts_wrap_cnt++;
138
139 ptp_dte->ts_ovf_last = ts_ovf;
140
141 /* adjust for wraparounds */
142 ns += (s64)(BIT_ULL(DTE_WRAP_AROUND_NSEC_SHIFT) * ptp_dte->ts_wrap_cnt);
143
144 return ns;
145 }
146
ptp_dte_adjfreq(struct ptp_clock_info * ptp,s32 ppb)147 static int ptp_dte_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
148 {
149 u32 nco_incr;
150 unsigned long flags;
151 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps);
152
153 if (abs(ppb) > ptp_dte->caps.max_adj) {
154 dev_err(ptp_dte->dev, "ppb adj too big\n");
155 return -EINVAL;
156 }
157
158 if (ppb < 0)
159 nco_incr = DTE_NCO_INC_DEFAULT - DTE_PPB_ADJ(ppb);
160 else
161 nco_incr = DTE_NCO_INC_DEFAULT + DTE_PPB_ADJ(ppb);
162
163 spin_lock_irqsave(&ptp_dte->lock, flags);
164 writel(nco_incr, ptp_dte->regs + DTE_NCO_INC_REG);
165 spin_unlock_irqrestore(&ptp_dte->lock, flags);
166
167 return 0;
168 }
169
ptp_dte_adjtime(struct ptp_clock_info * ptp,s64 delta)170 static int ptp_dte_adjtime(struct ptp_clock_info *ptp, s64 delta)
171 {
172 unsigned long flags;
173 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps);
174
175 spin_lock_irqsave(&ptp_dte->lock, flags);
176 dte_write_nco_delta(ptp_dte, delta);
177 spin_unlock_irqrestore(&ptp_dte->lock, flags);
178
179 return 0;
180 }
181
ptp_dte_gettime(struct ptp_clock_info * ptp,struct timespec64 * ts)182 static int ptp_dte_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
183 {
184 unsigned long flags;
185 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps);
186
187 spin_lock_irqsave(&ptp_dte->lock, flags);
188 *ts = ns_to_timespec64(dte_read_nco_with_ovf(ptp_dte));
189 spin_unlock_irqrestore(&ptp_dte->lock, flags);
190
191 return 0;
192 }
193
ptp_dte_settime(struct ptp_clock_info * ptp,const struct timespec64 * ts)194 static int ptp_dte_settime(struct ptp_clock_info *ptp,
195 const struct timespec64 *ts)
196 {
197 unsigned long flags;
198 struct ptp_dte *ptp_dte = container_of(ptp, struct ptp_dte, caps);
199
200 spin_lock_irqsave(&ptp_dte->lock, flags);
201
202 /* Disable nco increment */
203 writel(0, ptp_dte->regs + DTE_NCO_INC_REG);
204
205 dte_write_nco(ptp_dte->regs, timespec64_to_ns(ts));
206
207 /* reset overflow and wrap counter */
208 ptp_dte->ts_ovf_last = 0;
209 ptp_dte->ts_wrap_cnt = 0;
210
211 /* Enable nco increment */
212 writel(DTE_NCO_INC_DEFAULT, ptp_dte->regs + DTE_NCO_INC_REG);
213
214 spin_unlock_irqrestore(&ptp_dte->lock, flags);
215
216 return 0;
217 }
218
ptp_dte_enable(struct ptp_clock_info * ptp,struct ptp_clock_request * rq,int on)219 static int ptp_dte_enable(struct ptp_clock_info *ptp,
220 struct ptp_clock_request *rq, int on)
221 {
222 return -EOPNOTSUPP;
223 }
224
225 static const struct ptp_clock_info ptp_dte_caps = {
226 .owner = THIS_MODULE,
227 .name = "DTE PTP timer",
228 .max_adj = 50000000,
229 .n_ext_ts = 0,
230 .n_pins = 0,
231 .pps = 0,
232 .adjfreq = ptp_dte_adjfreq,
233 .adjtime = ptp_dte_adjtime,
234 .gettime64 = ptp_dte_gettime,
235 .settime64 = ptp_dte_settime,
236 .enable = ptp_dte_enable,
237 };
238
ptp_dte_probe(struct platform_device * pdev)239 static int ptp_dte_probe(struct platform_device *pdev)
240 {
241 struct ptp_dte *ptp_dte;
242 struct device *dev = &pdev->dev;
243 struct resource *res;
244
245 ptp_dte = devm_kzalloc(dev, sizeof(struct ptp_dte), GFP_KERNEL);
246 if (!ptp_dte)
247 return -ENOMEM;
248
249 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
250 ptp_dte->regs = devm_ioremap_resource(dev, res);
251 if (IS_ERR(ptp_dte->regs))
252 return PTR_ERR(ptp_dte->regs);
253
254 spin_lock_init(&ptp_dte->lock);
255
256 ptp_dte->dev = dev;
257 ptp_dte->caps = ptp_dte_caps;
258 ptp_dte->ptp_clk = ptp_clock_register(&ptp_dte->caps, &pdev->dev);
259 if (IS_ERR(ptp_dte->ptp_clk)) {
260 dev_err(dev,
261 "%s: Failed to register ptp clock\n", __func__);
262 return PTR_ERR(ptp_dte->ptp_clk);
263 }
264
265 platform_set_drvdata(pdev, ptp_dte);
266
267 dev_info(dev, "ptp clk probe done\n");
268
269 return 0;
270 }
271
ptp_dte_remove(struct platform_device * pdev)272 static int ptp_dte_remove(struct platform_device *pdev)
273 {
274 struct ptp_dte *ptp_dte = platform_get_drvdata(pdev);
275 u8 i;
276
277 ptp_clock_unregister(ptp_dte->ptp_clk);
278
279 for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++)
280 writel(0, ptp_dte->regs + (i * sizeof(u32)));
281
282 return 0;
283 }
284
285 #ifdef CONFIG_PM_SLEEP
ptp_dte_suspend(struct device * dev)286 static int ptp_dte_suspend(struct device *dev)
287 {
288 struct ptp_dte *ptp_dte = dev_get_drvdata(dev);
289 u8 i;
290
291 for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) {
292 ptp_dte->reg_val[i] =
293 readl(ptp_dte->regs + (i * sizeof(u32)));
294 }
295
296 /* disable the nco */
297 writel(0, ptp_dte->regs + DTE_NCO_INC_REG);
298
299 return 0;
300 }
301
ptp_dte_resume(struct device * dev)302 static int ptp_dte_resume(struct device *dev)
303 {
304 struct ptp_dte *ptp_dte = dev_get_drvdata(dev);
305 u8 i;
306
307 for (i = 0; i < DTE_NUM_REGS_TO_RESTORE; i++) {
308 if ((i * sizeof(u32)) != DTE_NCO_OVERFLOW_REG)
309 writel(ptp_dte->reg_val[i],
310 (ptp_dte->regs + (i * sizeof(u32))));
311 else
312 writel(((ptp_dte->reg_val[i] &
313 DTE_NCO_SUM3_MASK) << DTE_NCO_SUM3_WR_SHIFT),
314 (ptp_dte->regs + (i * sizeof(u32))));
315 }
316
317 return 0;
318 }
319
320 static const struct dev_pm_ops ptp_dte_pm_ops = {
321 .suspend = ptp_dte_suspend,
322 .resume = ptp_dte_resume
323 };
324
325 #define PTP_DTE_PM_OPS (&ptp_dte_pm_ops)
326 #else
327 #define PTP_DTE_PM_OPS NULL
328 #endif
329
330 static const struct of_device_id ptp_dte_of_match[] = {
331 { .compatible = "brcm,ptp-dte", },
332 {},
333 };
334 MODULE_DEVICE_TABLE(of, ptp_dte_of_match);
335
336 static struct platform_driver ptp_dte_driver = {
337 .driver = {
338 .name = "ptp-dte",
339 .pm = PTP_DTE_PM_OPS,
340 .of_match_table = ptp_dte_of_match,
341 },
342 .probe = ptp_dte_probe,
343 .remove = ptp_dte_remove,
344 };
345 module_platform_driver(ptp_dte_driver);
346
347 MODULE_AUTHOR("Broadcom");
348 MODULE_DESCRIPTION("Broadcom DTE PTP Clock driver");
349 MODULE_LICENSE("GPL v2");
350
