1 // SPDX-License-Identifier: GPL-2.0-only
2 /*******************************************************************************
3 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
4 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
5 developing this code.
6
7 This only implements the mac core functions for this chip.
8
9 Copyright (C) 2007-2009 STMicroelectronics Ltd
10
11
12 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
13 *******************************************************************************/
14
15 #include <linux/crc32.h>
16 #include <linux/slab.h>
17 #include <linux/ethtool.h>
18 #include <net/dsa.h>
19 #include <asm/io.h>
20 #include "stmmac.h"
21 #include "stmmac_pcs.h"
22 #include "dwmac1000.h"
23
dwmac1000_core_init(struct mac_device_info * hw,struct net_device * dev)24 static void dwmac1000_core_init(struct mac_device_info *hw,
25 struct net_device *dev)
26 {
27 void __iomem *ioaddr = hw->pcsr;
28 u32 value = readl(ioaddr + GMAC_CONTROL);
29 int mtu = dev->mtu;
30
31 /* Configure GMAC core */
32 value |= GMAC_CORE_INIT;
33
34 /* Clear ACS bit because Ethernet switch tagging formats such as
35 * Broadcom tags can look like invalid LLC/SNAP packets and cause the
36 * hardware to truncate packets on reception.
37 */
38 if (netdev_uses_dsa(dev))
39 value &= ~GMAC_CONTROL_ACS;
40
41 if (mtu > 1500)
42 value |= GMAC_CONTROL_2K;
43 if (mtu > 2000)
44 value |= GMAC_CONTROL_JE;
45
46 if (hw->ps) {
47 value |= GMAC_CONTROL_TE;
48
49 value &= ~hw->link.speed_mask;
50 switch (hw->ps) {
51 case SPEED_1000:
52 value |= hw->link.speed1000;
53 break;
54 case SPEED_100:
55 value |= hw->link.speed100;
56 break;
57 case SPEED_10:
58 value |= hw->link.speed10;
59 break;
60 }
61 }
62
63 writel(value, ioaddr + GMAC_CONTROL);
64
65 /* Mask GMAC interrupts */
66 value = GMAC_INT_DEFAULT_MASK;
67
68 if (hw->pcs)
69 value &= ~GMAC_INT_DISABLE_PCS;
70
71 writel(value, ioaddr + GMAC_INT_MASK);
72
73 #ifdef STMMAC_VLAN_TAG_USED
74 /* Tag detection without filtering */
75 writel(0x0, ioaddr + GMAC_VLAN_TAG);
76 #endif
77 }
78
dwmac1000_rx_ipc_enable(struct mac_device_info * hw)79 static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw)
80 {
81 void __iomem *ioaddr = hw->pcsr;
82 u32 value = readl(ioaddr + GMAC_CONTROL);
83
84 if (hw->rx_csum)
85 value |= GMAC_CONTROL_IPC;
86 else
87 value &= ~GMAC_CONTROL_IPC;
88
89 writel(value, ioaddr + GMAC_CONTROL);
90
91 value = readl(ioaddr + GMAC_CONTROL);
92
93 return !!(value & GMAC_CONTROL_IPC);
94 }
95
dwmac1000_dump_regs(struct mac_device_info * hw,u32 * reg_space)96 static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)
97 {
98 void __iomem *ioaddr = hw->pcsr;
99 int i;
100
101 for (i = 0; i < 55; i++)
102 reg_space[i] = readl(ioaddr + i * 4);
103 }
104
dwmac1000_set_umac_addr(struct mac_device_info * hw,unsigned char * addr,unsigned int reg_n)105 static void dwmac1000_set_umac_addr(struct mac_device_info *hw,
106 unsigned char *addr,
107 unsigned int reg_n)
108 {
109 void __iomem *ioaddr = hw->pcsr;
110 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
111 GMAC_ADDR_LOW(reg_n));
112 }
113
dwmac1000_get_umac_addr(struct mac_device_info * hw,unsigned char * addr,unsigned int reg_n)114 static void dwmac1000_get_umac_addr(struct mac_device_info *hw,
115 unsigned char *addr,
116 unsigned int reg_n)
117 {
118 void __iomem *ioaddr = hw->pcsr;
119 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
120 GMAC_ADDR_LOW(reg_n));
121 }
122
dwmac1000_set_mchash(void __iomem * ioaddr,u32 * mcfilterbits,int mcbitslog2)123 static void dwmac1000_set_mchash(void __iomem *ioaddr, u32 *mcfilterbits,
124 int mcbitslog2)
125 {
126 int numhashregs, regs;
127
128 switch (mcbitslog2) {
129 case 6:
130 writel(mcfilterbits[0], ioaddr + GMAC_HASH_LOW);
131 writel(mcfilterbits[1], ioaddr + GMAC_HASH_HIGH);
132 return;
133 break;
134 case 7:
135 numhashregs = 4;
136 break;
137 case 8:
138 numhashregs = 8;
139 break;
140 default:
141 pr_debug("STMMAC: err in setting multicast filter\n");
142 return;
143 break;
144 }
145 for (regs = 0; regs < numhashregs; regs++)
146 writel(mcfilterbits[regs],
147 ioaddr + GMAC_EXTHASH_BASE + regs * 4);
148 }
149
dwmac1000_set_filter(struct mac_device_info * hw,struct net_device * dev)150 static void dwmac1000_set_filter(struct mac_device_info *hw,
151 struct net_device *dev)
152 {
153 void __iomem *ioaddr = (void __iomem *)dev->base_addr;
154 unsigned int value = 0;
155 unsigned int perfect_addr_number = hw->unicast_filter_entries;
156 u32 mc_filter[8];
157 int mcbitslog2 = hw->mcast_bits_log2;
158
159 pr_debug("%s: # mcasts %d, # unicast %d\n", __func__,
160 netdev_mc_count(dev), netdev_uc_count(dev));
161
162 memset(mc_filter, 0, sizeof(mc_filter));
163
164 if (dev->flags & IFF_PROMISC) {
165 value = GMAC_FRAME_FILTER_PR | GMAC_FRAME_FILTER_PCF;
166 } else if (dev->flags & IFF_ALLMULTI) {
167 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
168 } else if (!netdev_mc_empty(dev)) {
169 struct netdev_hw_addr *ha;
170
171 /* Hash filter for multicast */
172 value = GMAC_FRAME_FILTER_HMC;
173
174 netdev_for_each_mc_addr(ha, dev) {
175 /* The upper n bits of the calculated CRC are used to
176 * index the contents of the hash table. The number of
177 * bits used depends on the hardware configuration
178 * selected at core configuration time.
179 */
180 int bit_nr = bitrev32(~crc32_le(~0, ha->addr,
181 ETH_ALEN)) >>
182 (32 - mcbitslog2);
183 /* The most significant bit determines the register to
184 * use (H/L) while the other 5 bits determine the bit
185 * within the register.
186 */
187 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
188 }
189 }
190
191 value |= GMAC_FRAME_FILTER_HPF;
192 dwmac1000_set_mchash(ioaddr, mc_filter, mcbitslog2);
193
194 /* Handle multiple unicast addresses (perfect filtering) */
195 if (netdev_uc_count(dev) > perfect_addr_number)
196 /* Switch to promiscuous mode if more than unicast
197 * addresses are requested than supported by hardware.
198 */
199 value |= GMAC_FRAME_FILTER_PR;
200 else {
201 int reg = 1;
202 struct netdev_hw_addr *ha;
203
204 netdev_for_each_uc_addr(ha, dev) {
205 stmmac_set_mac_addr(ioaddr, ha->addr,
206 GMAC_ADDR_HIGH(reg),
207 GMAC_ADDR_LOW(reg));
208 reg++;
209 }
210
211 while (reg <= perfect_addr_number) {
212 writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
213 writel(0, ioaddr + GMAC_ADDR_LOW(reg));
214 reg++;
215 }
216 }
217
218 #ifdef FRAME_FILTER_DEBUG
219 /* Enable Receive all mode (to debug filtering_fail errors) */
220 value |= GMAC_FRAME_FILTER_RA;
221 #endif
222 writel(value, ioaddr + GMAC_FRAME_FILTER);
223 }
224
225
dwmac1000_flow_ctrl(struct mac_device_info * hw,unsigned int duplex,unsigned int fc,unsigned int pause_time,u32 tx_cnt)226 static void dwmac1000_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
227 unsigned int fc, unsigned int pause_time,
228 u32 tx_cnt)
229 {
230 void __iomem *ioaddr = hw->pcsr;
231 /* Set flow such that DZPQ in Mac Register 6 is 0,
232 * and unicast pause detect is enabled.
233 */
234 unsigned int flow = GMAC_FLOW_CTRL_UP;
235
236 pr_debug("GMAC Flow-Control:\n");
237 if (fc & FLOW_RX) {
238 pr_debug("\tReceive Flow-Control ON\n");
239 flow |= GMAC_FLOW_CTRL_RFE;
240 }
241 if (fc & FLOW_TX) {
242 pr_debug("\tTransmit Flow-Control ON\n");
243 flow |= GMAC_FLOW_CTRL_TFE;
244 }
245
246 if (duplex) {
247 pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
248 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
249 }
250
251 writel(flow, ioaddr + GMAC_FLOW_CTRL);
252 }
253
dwmac1000_pmt(struct mac_device_info * hw,unsigned long mode)254 static void dwmac1000_pmt(struct mac_device_info *hw, unsigned long mode)
255 {
256 void __iomem *ioaddr = hw->pcsr;
257 unsigned int pmt = 0;
258
259 if (mode & WAKE_MAGIC) {
260 pr_debug("GMAC: WOL Magic frame\n");
261 pmt |= power_down | magic_pkt_en;
262 }
263 if (mode & WAKE_UCAST) {
264 pr_debug("GMAC: WOL on global unicast\n");
265 pmt |= power_down | global_unicast | wake_up_frame_en;
266 }
267
268 writel(pmt, ioaddr + GMAC_PMT);
269 }
270
271 /* RGMII or SMII interface */
dwmac1000_rgsmii(void __iomem * ioaddr,struct stmmac_extra_stats * x)272 static void dwmac1000_rgsmii(void __iomem *ioaddr, struct stmmac_extra_stats *x)
273 {
274 u32 status;
275
276 status = readl(ioaddr + GMAC_RGSMIIIS);
277 x->irq_rgmii_n++;
278
279 /* Check the link status */
280 if (status & GMAC_RGSMIIIS_LNKSTS) {
281 int speed_value;
282
283 x->pcs_link = 1;
284
285 speed_value = ((status & GMAC_RGSMIIIS_SPEED) >>
286 GMAC_RGSMIIIS_SPEED_SHIFT);
287 if (speed_value == GMAC_RGSMIIIS_SPEED_125)
288 x->pcs_speed = SPEED_1000;
289 else if (speed_value == GMAC_RGSMIIIS_SPEED_25)
290 x->pcs_speed = SPEED_100;
291 else
292 x->pcs_speed = SPEED_10;
293
294 x->pcs_duplex = (status & GMAC_RGSMIIIS_LNKMOD_MASK);
295
296 pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
297 x->pcs_duplex ? "Full" : "Half");
298 } else {
299 x->pcs_link = 0;
300 pr_info("Link is Down\n");
301 }
302 }
303
dwmac1000_irq_status(struct mac_device_info * hw,struct stmmac_extra_stats * x)304 static int dwmac1000_irq_status(struct mac_device_info *hw,
305 struct stmmac_extra_stats *x)
306 {
307 void __iomem *ioaddr = hw->pcsr;
308 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
309 u32 intr_mask = readl(ioaddr + GMAC_INT_MASK);
310 int ret = 0;
311
312 /* Discard masked bits */
313 intr_status &= ~intr_mask;
314
315 /* Not used events (e.g. MMC interrupts) are not handled. */
316 if ((intr_status & GMAC_INT_STATUS_MMCTIS))
317 x->mmc_tx_irq_n++;
318 if (unlikely(intr_status & GMAC_INT_STATUS_MMCRIS))
319 x->mmc_rx_irq_n++;
320 if (unlikely(intr_status & GMAC_INT_STATUS_MMCCSUM))
321 x->mmc_rx_csum_offload_irq_n++;
322 if (unlikely(intr_status & GMAC_INT_DISABLE_PMT)) {
323 /* clear the PMT bits 5 and 6 by reading the PMT status reg */
324 readl(ioaddr + GMAC_PMT);
325 x->irq_receive_pmt_irq_n++;
326 }
327
328 /* MAC tx/rx EEE LPI entry/exit interrupts */
329 if (intr_status & GMAC_INT_STATUS_LPIIS) {
330 /* Clean LPI interrupt by reading the Reg 12 */
331 ret = readl(ioaddr + LPI_CTRL_STATUS);
332
333 if (ret & LPI_CTRL_STATUS_TLPIEN)
334 x->irq_tx_path_in_lpi_mode_n++;
335 if (ret & LPI_CTRL_STATUS_TLPIEX)
336 x->irq_tx_path_exit_lpi_mode_n++;
337 if (ret & LPI_CTRL_STATUS_RLPIEN)
338 x->irq_rx_path_in_lpi_mode_n++;
339 if (ret & LPI_CTRL_STATUS_RLPIEX)
340 x->irq_rx_path_exit_lpi_mode_n++;
341 }
342
343 dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
344
345 if (intr_status & PCS_RGSMIIIS_IRQ)
346 dwmac1000_rgsmii(ioaddr, x);
347
348 return ret;
349 }
350
dwmac1000_set_eee_mode(struct mac_device_info * hw,bool en_tx_lpi_clockgating)351 static void dwmac1000_set_eee_mode(struct mac_device_info *hw,
352 bool en_tx_lpi_clockgating)
353 {
354 void __iomem *ioaddr = hw->pcsr;
355 u32 value;
356
357 /*TODO - en_tx_lpi_clockgating treatment */
358
359 /* Enable the link status receive on RGMII, SGMII ore SMII
360 * receive path and instruct the transmit to enter in LPI
361 * state.
362 */
363 value = readl(ioaddr + LPI_CTRL_STATUS);
364 value |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA;
365 writel(value, ioaddr + LPI_CTRL_STATUS);
366 }
367
dwmac1000_reset_eee_mode(struct mac_device_info * hw)368 static void dwmac1000_reset_eee_mode(struct mac_device_info *hw)
369 {
370 void __iomem *ioaddr = hw->pcsr;
371 u32 value;
372
373 value = readl(ioaddr + LPI_CTRL_STATUS);
374 value &= ~(LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_LPITXA);
375 writel(value, ioaddr + LPI_CTRL_STATUS);
376 }
377
dwmac1000_set_eee_pls(struct mac_device_info * hw,int link)378 static void dwmac1000_set_eee_pls(struct mac_device_info *hw, int link)
379 {
380 void __iomem *ioaddr = hw->pcsr;
381 u32 value;
382
383 value = readl(ioaddr + LPI_CTRL_STATUS);
384
385 if (link)
386 value |= LPI_CTRL_STATUS_PLS;
387 else
388 value &= ~LPI_CTRL_STATUS_PLS;
389
390 writel(value, ioaddr + LPI_CTRL_STATUS);
391 }
392
dwmac1000_set_eee_timer(struct mac_device_info * hw,int ls,int tw)393 static void dwmac1000_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
394 {
395 void __iomem *ioaddr = hw->pcsr;
396 int value = ((tw & 0xffff)) | ((ls & 0x7ff) << 16);
397
398 /* Program the timers in the LPI timer control register:
399 * LS: minimum time (ms) for which the link
400 * status from PHY should be ok before transmitting
401 * the LPI pattern.
402 * TW: minimum time (us) for which the core waits
403 * after it has stopped transmitting the LPI pattern.
404 */
405 writel(value, ioaddr + LPI_TIMER_CTRL);
406 }
407
dwmac1000_ctrl_ane(void __iomem * ioaddr,bool ane,bool srgmi_ral,bool loopback)408 static void dwmac1000_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
409 bool loopback)
410 {
411 dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
412 }
413
dwmac1000_rane(void __iomem * ioaddr,bool restart)414 static void dwmac1000_rane(void __iomem *ioaddr, bool restart)
415 {
416 dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
417 }
418
dwmac1000_get_adv_lp(void __iomem * ioaddr,struct rgmii_adv * adv)419 static void dwmac1000_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
420 {
421 dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
422 }
423
dwmac1000_debug(void __iomem * ioaddr,struct stmmac_extra_stats * x,u32 rx_queues,u32 tx_queues)424 static void dwmac1000_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
425 u32 rx_queues, u32 tx_queues)
426 {
427 u32 value = readl(ioaddr + GMAC_DEBUG);
428
429 if (value & GMAC_DEBUG_TXSTSFSTS)
430 x->mtl_tx_status_fifo_full++;
431 if (value & GMAC_DEBUG_TXFSTS)
432 x->mtl_tx_fifo_not_empty++;
433 if (value & GMAC_DEBUG_TWCSTS)
434 x->mmtl_fifo_ctrl++;
435 if (value & GMAC_DEBUG_TRCSTS_MASK) {
436 u32 trcsts = (value & GMAC_DEBUG_TRCSTS_MASK)
437 >> GMAC_DEBUG_TRCSTS_SHIFT;
438 if (trcsts == GMAC_DEBUG_TRCSTS_WRITE)
439 x->mtl_tx_fifo_read_ctrl_write++;
440 else if (trcsts == GMAC_DEBUG_TRCSTS_TXW)
441 x->mtl_tx_fifo_read_ctrl_wait++;
442 else if (trcsts == GMAC_DEBUG_TRCSTS_READ)
443 x->mtl_tx_fifo_read_ctrl_read++;
444 else
445 x->mtl_tx_fifo_read_ctrl_idle++;
446 }
447 if (value & GMAC_DEBUG_TXPAUSED)
448 x->mac_tx_in_pause++;
449 if (value & GMAC_DEBUG_TFCSTS_MASK) {
450 u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
451 >> GMAC_DEBUG_TFCSTS_SHIFT;
452
453 if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
454 x->mac_tx_frame_ctrl_xfer++;
455 else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
456 x->mac_tx_frame_ctrl_pause++;
457 else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
458 x->mac_tx_frame_ctrl_wait++;
459 else
460 x->mac_tx_frame_ctrl_idle++;
461 }
462 if (value & GMAC_DEBUG_TPESTS)
463 x->mac_gmii_tx_proto_engine++;
464 if (value & GMAC_DEBUG_RXFSTS_MASK) {
465 u32 rxfsts = (value & GMAC_DEBUG_RXFSTS_MASK)
466 >> GMAC_DEBUG_RRCSTS_SHIFT;
467
468 if (rxfsts == GMAC_DEBUG_RXFSTS_FULL)
469 x->mtl_rx_fifo_fill_level_full++;
470 else if (rxfsts == GMAC_DEBUG_RXFSTS_AT)
471 x->mtl_rx_fifo_fill_above_thresh++;
472 else if (rxfsts == GMAC_DEBUG_RXFSTS_BT)
473 x->mtl_rx_fifo_fill_below_thresh++;
474 else
475 x->mtl_rx_fifo_fill_level_empty++;
476 }
477 if (value & GMAC_DEBUG_RRCSTS_MASK) {
478 u32 rrcsts = (value & GMAC_DEBUG_RRCSTS_MASK) >>
479 GMAC_DEBUG_RRCSTS_SHIFT;
480
481 if (rrcsts == GMAC_DEBUG_RRCSTS_FLUSH)
482 x->mtl_rx_fifo_read_ctrl_flush++;
483 else if (rrcsts == GMAC_DEBUG_RRCSTS_RSTAT)
484 x->mtl_rx_fifo_read_ctrl_read_data++;
485 else if (rrcsts == GMAC_DEBUG_RRCSTS_RDATA)
486 x->mtl_rx_fifo_read_ctrl_status++;
487 else
488 x->mtl_rx_fifo_read_ctrl_idle++;
489 }
490 if (value & GMAC_DEBUG_RWCSTS)
491 x->mtl_rx_fifo_ctrl_active++;
492 if (value & GMAC_DEBUG_RFCFCSTS_MASK)
493 x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
494 >> GMAC_DEBUG_RFCFCSTS_SHIFT;
495 if (value & GMAC_DEBUG_RPESTS)
496 x->mac_gmii_rx_proto_engine++;
497 }
498
dwmac1000_set_mac_loopback(void __iomem * ioaddr,bool enable)499 static void dwmac1000_set_mac_loopback(void __iomem *ioaddr, bool enable)
500 {
501 u32 value = readl(ioaddr + GMAC_CONTROL);
502
503 if (enable)
504 value |= GMAC_CONTROL_LM;
505 else
506 value &= ~GMAC_CONTROL_LM;
507
508 writel(value, ioaddr + GMAC_CONTROL);
509 }
510
511 const struct stmmac_ops dwmac1000_ops = {
512 .core_init = dwmac1000_core_init,
513 .set_mac = stmmac_set_mac,
514 .rx_ipc = dwmac1000_rx_ipc_enable,
515 .dump_regs = dwmac1000_dump_regs,
516 .host_irq_status = dwmac1000_irq_status,
517 .set_filter = dwmac1000_set_filter,
518 .flow_ctrl = dwmac1000_flow_ctrl,
519 .pmt = dwmac1000_pmt,
520 .set_umac_addr = dwmac1000_set_umac_addr,
521 .get_umac_addr = dwmac1000_get_umac_addr,
522 .set_eee_mode = dwmac1000_set_eee_mode,
523 .reset_eee_mode = dwmac1000_reset_eee_mode,
524 .set_eee_timer = dwmac1000_set_eee_timer,
525 .set_eee_pls = dwmac1000_set_eee_pls,
526 .debug = dwmac1000_debug,
527 .pcs_ctrl_ane = dwmac1000_ctrl_ane,
528 .pcs_rane = dwmac1000_rane,
529 .pcs_get_adv_lp = dwmac1000_get_adv_lp,
530 .set_mac_loopback = dwmac1000_set_mac_loopback,
531 };
532
dwmac1000_setup(struct stmmac_priv * priv)533 int dwmac1000_setup(struct stmmac_priv *priv)
534 {
535 struct mac_device_info *mac = priv->hw;
536
537 dev_info(priv->device, "\tDWMAC1000\n");
538
539 priv->dev->priv_flags |= IFF_UNICAST_FLT;
540 mac->pcsr = priv->ioaddr;
541 mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
542 mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
543 mac->mcast_bits_log2 = 0;
544
545 if (mac->multicast_filter_bins)
546 mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
547
548 mac->link.duplex = GMAC_CONTROL_DM;
549 mac->link.speed10 = GMAC_CONTROL_PS;
550 mac->link.speed100 = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
551 mac->link.speed1000 = 0;
552 mac->link.speed_mask = GMAC_CONTROL_PS | GMAC_CONTROL_FES;
553 mac->mii.addr = GMAC_MII_ADDR;
554 mac->mii.data = GMAC_MII_DATA;
555 mac->mii.addr_shift = 11;
556 mac->mii.addr_mask = 0x0000F800;
557 mac->mii.reg_shift = 6;
558 mac->mii.reg_mask = 0x000007C0;
559 mac->mii.clk_csr_shift = 2;
560 mac->mii.clk_csr_mask = GENMASK(5, 2);
561
562 return 0;
563 }
564
